ihs_i2c.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #ifdef CONFIG_DM_I2C
  9. #include <dm.h>
  10. #include <regmap.h>
  11. #else
  12. #include <gdsys_fpga.h>
  13. #endif
  14. #include <asm/unaligned.h>
  15. #ifdef CONFIG_DM_I2C
  16. struct ihs_i2c_priv {
  17. uint speed;
  18. struct regmap *map;
  19. };
  20. struct ihs_i2c_regs {
  21. u16 interrupt_status;
  22. u16 interrupt_enable_control;
  23. u16 write_mailbox_ext;
  24. u16 write_mailbox;
  25. u16 read_mailbox_ext;
  26. u16 read_mailbox;
  27. };
  28. #define ihs_i2c_set(map, member, val) \
  29. regmap_set(map, struct ihs_i2c_regs, member, val)
  30. #define ihs_i2c_get(map, member, valp) \
  31. regmap_get(map, struct ihs_i2c_regs, member, valp)
  32. #else /* !CONFIG_DM_I2C */
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifdef CONFIG_SYS_I2C_IHS_DUAL
  35. #define I2C_SET_REG(fld, val) \
  36. do { \
  37. if (I2C_ADAP_HWNR & 0x10) \
  38. FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  39. else \
  40. FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  41. } while (0)
  42. #else
  43. #define I2C_SET_REG(fld, val) \
  44. FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  45. #endif
  46. #ifdef CONFIG_SYS_I2C_IHS_DUAL
  47. #define I2C_GET_REG(fld, val) \
  48. do { \
  49. if (I2C_ADAP_HWNR & 0x10) \
  50. FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  51. else \
  52. FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  53. } while (0)
  54. #else
  55. #define I2C_GET_REG(fld, val) \
  56. FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  57. #endif
  58. #endif /* CONFIG_DM_I2C */
  59. enum {
  60. I2CINT_ERROR_EV = BIT(13),
  61. I2CINT_TRANSMIT_EV = BIT(14),
  62. I2CINT_RECEIVE_EV = BIT(15),
  63. };
  64. enum {
  65. I2CMB_READ = 0 << 10,
  66. I2CMB_WRITE = 1 << 10,
  67. I2CMB_1BYTE = 0 << 11,
  68. I2CMB_2BYTE = 1 << 11,
  69. I2CMB_DONT_HOLD_BUS = 0 << 13,
  70. I2CMB_HOLD_BUS = 1 << 13,
  71. I2CMB_NATIVE = 2 << 14,
  72. };
  73. enum {
  74. I2COP_WRITE = 0,
  75. I2COP_READ = 1,
  76. };
  77. #ifdef CONFIG_DM_I2C
  78. static int wait_for_int(struct udevice *dev, int read)
  79. #else
  80. static int wait_for_int(bool read)
  81. #endif
  82. {
  83. u16 val;
  84. uint ctr = 0;
  85. #ifdef CONFIG_DM_I2C
  86. struct ihs_i2c_priv *priv = dev_get_priv(dev);
  87. #endif
  88. #ifdef CONFIG_DM_I2C
  89. ihs_i2c_get(priv->map, interrupt_status, &val);
  90. #else
  91. I2C_GET_REG(interrupt_status, &val);
  92. #endif
  93. /* Wait until error or receive/transmit interrupt was raised */
  94. while (!(val & (I2CINT_ERROR_EV
  95. | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
  96. udelay(10);
  97. if (ctr++ > 5000) {
  98. debug("%s: timed out\n", __func__);
  99. return -ETIMEDOUT;
  100. }
  101. #ifdef CONFIG_DM_I2C
  102. ihs_i2c_get(priv->map, interrupt_status, &val);
  103. #else
  104. I2C_GET_REG(interrupt_status, &val);
  105. #endif
  106. }
  107. return (val & I2CINT_ERROR_EV) ? -EIO : 0;
  108. }
  109. #ifdef CONFIG_DM_I2C
  110. static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
  111. uchar *buffer, int len, int read, bool is_last)
  112. #else
  113. static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
  114. bool is_last)
  115. #endif
  116. {
  117. u16 val;
  118. u16 data;
  119. int res;
  120. #ifdef CONFIG_DM_I2C
  121. struct ihs_i2c_priv *priv = dev_get_priv(dev);
  122. #endif
  123. /* Clear interrupt status */
  124. data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
  125. #ifdef CONFIG_DM_I2C
  126. ihs_i2c_set(priv->map, interrupt_status, data);
  127. ihs_i2c_get(priv->map, interrupt_status, &val);
  128. #else
  129. I2C_SET_REG(interrupt_status, data);
  130. I2C_GET_REG(interrupt_status, &val);
  131. #endif
  132. /* If we want to write and have data, write the bytes to the mailbox */
  133. if (!read && len) {
  134. val = buffer[0];
  135. if (len > 1)
  136. val |= buffer[1] << 8;
  137. #ifdef CONFIG_DM_I2C
  138. ihs_i2c_set(priv->map, write_mailbox_ext, val);
  139. #else
  140. I2C_SET_REG(write_mailbox_ext, val);
  141. #endif
  142. }
  143. data = I2CMB_NATIVE
  144. | (read ? 0 : I2CMB_WRITE)
  145. | (chip << 1)
  146. | ((len > 1) ? I2CMB_2BYTE : 0)
  147. | (is_last ? 0 : I2CMB_HOLD_BUS);
  148. #ifdef CONFIG_DM_I2C
  149. ihs_i2c_set(priv->map, write_mailbox, data);
  150. #else
  151. I2C_SET_REG(write_mailbox, data);
  152. #endif
  153. #ifdef CONFIG_DM_I2C
  154. res = wait_for_int(dev, read);
  155. #else
  156. res = wait_for_int(read);
  157. #endif
  158. if (res) {
  159. if (res == -ETIMEDOUT)
  160. debug("%s: time out while waiting for event\n", __func__);
  161. return res;
  162. }
  163. /* If we want to read, get the bytes from the mailbox */
  164. if (read) {
  165. #ifdef CONFIG_DM_I2C
  166. ihs_i2c_get(priv->map, read_mailbox_ext, &val);
  167. #else
  168. I2C_GET_REG(read_mailbox_ext, &val);
  169. #endif
  170. buffer[0] = val & 0xff;
  171. if (len > 1)
  172. buffer[1] = val >> 8;
  173. }
  174. return 0;
  175. }
  176. #ifdef CONFIG_DM_I2C
  177. static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
  178. #else
  179. static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
  180. int read)
  181. #endif
  182. {
  183. int res;
  184. while (len) {
  185. int transfer = min(len, 2);
  186. bool is_last = len <= transfer;
  187. #ifdef CONFIG_DM_I2C
  188. res = ihs_i2c_transfer(dev, chip, data, transfer, read,
  189. hold_bus ? false : is_last);
  190. #else
  191. res = ihs_i2c_transfer(chip, data, transfer, read,
  192. hold_bus ? false : is_last);
  193. #endif
  194. if (res)
  195. return res;
  196. data += transfer;
  197. len -= transfer;
  198. }
  199. return 0;
  200. }
  201. #ifdef CONFIG_DM_I2C
  202. static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
  203. bool hold_bus)
  204. #else
  205. static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
  206. #endif
  207. {
  208. #ifdef CONFIG_DM_I2C
  209. return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
  210. #else
  211. return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
  212. #endif
  213. }
  214. #ifdef CONFIG_DM_I2C
  215. static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
  216. int alen, uchar *buffer, int len, int read)
  217. #else
  218. static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
  219. int alen, uchar *buffer, int len, int read)
  220. #endif
  221. {
  222. int res;
  223. /* Don't hold the bus if length of data to send/receive is zero */
  224. if (len <= 0)
  225. return -EINVAL;
  226. #ifdef CONFIG_DM_I2C
  227. res = ihs_i2c_address(dev, chip, addr, alen, len);
  228. #else
  229. res = ihs_i2c_address(chip, addr, alen, len);
  230. #endif
  231. if (res)
  232. return res;
  233. #ifdef CONFIG_DM_I2C
  234. return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
  235. #else
  236. return ihs_i2c_send_buffer(chip, buffer, len, false, read);
  237. #endif
  238. }
  239. #ifdef CONFIG_DM_I2C
  240. int ihs_i2c_probe(struct udevice *bus)
  241. {
  242. struct ihs_i2c_priv *priv = dev_get_priv(bus);
  243. regmap_init_mem(dev_ofnode(bus), &priv->map);
  244. return 0;
  245. }
  246. static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
  247. {
  248. struct ihs_i2c_priv *priv = dev_get_priv(bus);
  249. if (speed != priv->speed && priv->speed != 0)
  250. return -EINVAL;
  251. priv->speed = speed;
  252. return 0;
  253. }
  254. static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  255. {
  256. struct i2c_msg *dmsg, *omsg, dummy;
  257. memset(&dummy, 0, sizeof(struct i2c_msg));
  258. /* We expect either two messages (one with an offset and one with the
  259. * actucal data) or one message (just data)
  260. */
  261. if (nmsgs > 2 || nmsgs == 0) {
  262. debug("%s: Only one or two messages are supported\n", __func__);
  263. return -ENOTSUPP;
  264. }
  265. omsg = nmsgs == 1 ? &dummy : msg;
  266. dmsg = nmsgs == 1 ? msg : msg + 1;
  267. if (dmsg->flags & I2C_M_RD)
  268. return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
  269. omsg->len, dmsg->buf, dmsg->len,
  270. I2COP_READ);
  271. else
  272. return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
  273. omsg->len, dmsg->buf, dmsg->len,
  274. I2COP_WRITE);
  275. }
  276. static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  277. u32 chip_flags)
  278. {
  279. uchar buffer[2];
  280. int res;
  281. res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
  282. if (res)
  283. return res;
  284. return 0;
  285. }
  286. static const struct dm_i2c_ops ihs_i2c_ops = {
  287. .xfer = ihs_i2c_xfer,
  288. .probe_chip = ihs_i2c_probe_chip,
  289. .set_bus_speed = ihs_i2c_set_bus_speed,
  290. };
  291. static const struct udevice_id ihs_i2c_ids[] = {
  292. { .compatible = "gdsys,ihs_i2cmaster", },
  293. { /* sentinel */ }
  294. };
  295. U_BOOT_DRIVER(i2c_ihs) = {
  296. .name = "i2c_ihs",
  297. .id = UCLASS_I2C,
  298. .of_match = ihs_i2c_ids,
  299. .probe = ihs_i2c_probe,
  300. .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
  301. .ops = &ihs_i2c_ops,
  302. };
  303. #else /* CONFIG_DM_I2C */
  304. static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  305. {
  306. #ifdef CONFIG_SYS_I2C_INIT_BOARD
  307. /*
  308. * Call board specific i2c bus reset routine before accessing the
  309. * environment, which might be in a chip on that bus. For details
  310. * about this problem see doc/I2C_Edge_Conditions.
  311. */
  312. i2c_init_board();
  313. #endif
  314. }
  315. static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
  316. {
  317. uchar buffer[2];
  318. int res;
  319. res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
  320. if (res)
  321. return res;
  322. return 0;
  323. }
  324. static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  325. int alen, uchar *buffer, int len)
  326. {
  327. u8 addr_bytes[4];
  328. put_unaligned_le32(addr, addr_bytes);
  329. return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
  330. I2COP_READ);
  331. }
  332. static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  333. int alen, uchar *buffer, int len)
  334. {
  335. u8 addr_bytes[4];
  336. put_unaligned_le32(addr, addr_bytes);
  337. return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
  338. I2COP_WRITE);
  339. }
  340. static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
  341. unsigned int speed)
  342. {
  343. if (speed != adap->speed)
  344. return -EINVAL;
  345. return speed;
  346. }
  347. /*
  348. * Register IHS i2c adapters
  349. */
  350. #ifdef CONFIG_SYS_I2C_IHS_CH0
  351. U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
  352. ihs_i2c_read, ihs_i2c_write,
  353. ihs_i2c_set_bus_speed,
  354. CONFIG_SYS_I2C_IHS_SPEED_0,
  355. CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
  356. #ifdef CONFIG_SYS_I2C_IHS_DUAL
  357. U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
  358. ihs_i2c_read, ihs_i2c_write,
  359. ihs_i2c_set_bus_speed,
  360. CONFIG_SYS_I2C_IHS_SPEED_0_1,
  361. CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
  362. #endif
  363. #endif
  364. #ifdef CONFIG_SYS_I2C_IHS_CH1
  365. U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
  366. ihs_i2c_read, ihs_i2c_write,
  367. ihs_i2c_set_bus_speed,
  368. CONFIG_SYS_I2C_IHS_SPEED_1,
  369. CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
  370. #ifdef CONFIG_SYS_I2C_IHS_DUAL
  371. U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
  372. ihs_i2c_read, ihs_i2c_write,
  373. ihs_i2c_set_bus_speed,
  374. CONFIG_SYS_I2C_IHS_SPEED_1_1,
  375. CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
  376. #endif
  377. #endif
  378. #ifdef CONFIG_SYS_I2C_IHS_CH2
  379. U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
  380. ihs_i2c_read, ihs_i2c_write,
  381. ihs_i2c_set_bus_speed,
  382. CONFIG_SYS_I2C_IHS_SPEED_2,
  383. CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
  384. #ifdef CONFIG_SYS_I2C_IHS_DUAL
  385. U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
  386. ihs_i2c_read, ihs_i2c_write,
  387. ihs_i2c_set_bus_speed,
  388. CONFIG_SYS_I2C_IHS_SPEED_2_1,
  389. CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
  390. #endif
  391. #endif
  392. #ifdef CONFIG_SYS_I2C_IHS_CH3
  393. U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
  394. ihs_i2c_read, ihs_i2c_write,
  395. ihs_i2c_set_bus_speed,
  396. CONFIG_SYS_I2C_IHS_SPEED_3,
  397. CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
  398. #ifdef CONFIG_SYS_I2C_IHS_DUAL
  399. U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
  400. ihs_i2c_read, ihs_i2c_write,
  401. ihs_i2c_set_bus_speed,
  402. CONFIG_SYS_I2C_IHS_SPEED_3_1,
  403. CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
  404. #endif
  405. #endif
  406. #endif /* CONFIG_DM_I2C */