i2c-cdns.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
  4. * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
  5. *
  6. * This file is based on: drivers/i2c/zynq_i2c.c,
  7. * with added driver-model support and code cleanup.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <linux/types.h>
  12. #include <linux/io.h>
  13. #include <linux/errno.h>
  14. #include <dm/root.h>
  15. #include <i2c.h>
  16. #include <fdtdec.h>
  17. #include <mapmem.h>
  18. #include <wait_bit.h>
  19. #include <clk.h>
  20. /* i2c register set */
  21. struct cdns_i2c_regs {
  22. u32 control;
  23. u32 status;
  24. u32 address;
  25. u32 data;
  26. u32 interrupt_status;
  27. u32 transfer_size;
  28. u32 slave_mon_pause;
  29. u32 time_out;
  30. u32 interrupt_mask;
  31. u32 interrupt_enable;
  32. u32 interrupt_disable;
  33. };
  34. /* Control register fields */
  35. #define CDNS_I2C_CONTROL_RW 0x00000001
  36. #define CDNS_I2C_CONTROL_MS 0x00000002
  37. #define CDNS_I2C_CONTROL_NEA 0x00000004
  38. #define CDNS_I2C_CONTROL_ACKEN 0x00000008
  39. #define CDNS_I2C_CONTROL_HOLD 0x00000010
  40. #define CDNS_I2C_CONTROL_SLVMON 0x00000020
  41. #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
  42. #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
  43. #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
  44. #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
  45. #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
  46. /* Status register values */
  47. #define CDNS_I2C_STATUS_RXDV 0x00000020
  48. #define CDNS_I2C_STATUS_TXDV 0x00000040
  49. #define CDNS_I2C_STATUS_RXOVF 0x00000080
  50. #define CDNS_I2C_STATUS_BA 0x00000100
  51. /* Interrupt register fields */
  52. #define CDNS_I2C_INTERRUPT_COMP 0x00000001
  53. #define CDNS_I2C_INTERRUPT_DATA 0x00000002
  54. #define CDNS_I2C_INTERRUPT_NACK 0x00000004
  55. #define CDNS_I2C_INTERRUPT_TO 0x00000008
  56. #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
  57. #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
  58. #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
  59. #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
  60. #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
  61. #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
  62. CDNS_I2C_INTERRUPT_DATA | \
  63. CDNS_I2C_INTERRUPT_NACK | \
  64. CDNS_I2C_INTERRUPT_TO | \
  65. CDNS_I2C_INTERRUPT_SLVRDY | \
  66. CDNS_I2C_INTERRUPT_RXOVF | \
  67. CDNS_I2C_INTERRUPT_TXOVF | \
  68. CDNS_I2C_INTERRUPT_RXUNF | \
  69. CDNS_I2C_INTERRUPT_ARBLOST)
  70. #define CDNS_I2C_FIFO_DEPTH 16
  71. #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
  72. #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  73. #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
  74. #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
  75. #ifdef DEBUG
  76. static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  77. {
  78. int int_status;
  79. int status;
  80. int_status = readl(&cdns_i2c->interrupt_status);
  81. status = readl(&cdns_i2c->status);
  82. if (int_status || status) {
  83. debug("Status: ");
  84. if (int_status & CDNS_I2C_INTERRUPT_COMP)
  85. debug("COMP ");
  86. if (int_status & CDNS_I2C_INTERRUPT_DATA)
  87. debug("DATA ");
  88. if (int_status & CDNS_I2C_INTERRUPT_NACK)
  89. debug("NACK ");
  90. if (int_status & CDNS_I2C_INTERRUPT_TO)
  91. debug("TO ");
  92. if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
  93. debug("SLVRDY ");
  94. if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
  95. debug("RXOVF ");
  96. if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
  97. debug("TXOVF ");
  98. if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
  99. debug("RXUNF ");
  100. if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
  101. debug("ARBLOST ");
  102. if (status & CDNS_I2C_STATUS_RXDV)
  103. debug("RXDV ");
  104. if (status & CDNS_I2C_STATUS_TXDV)
  105. debug("TXDV ");
  106. if (status & CDNS_I2C_STATUS_RXOVF)
  107. debug("RXOVF ");
  108. if (status & CDNS_I2C_STATUS_BA)
  109. debug("BA ");
  110. debug("TS%d ", readl(&cdns_i2c->transfer_size));
  111. debug("\n");
  112. }
  113. }
  114. #endif
  115. struct i2c_cdns_bus {
  116. int id;
  117. unsigned int input_freq;
  118. struct cdns_i2c_regs __iomem *regs; /* register base */
  119. int hold_flag;
  120. u32 quirks;
  121. };
  122. struct cdns_i2c_platform_data {
  123. u32 quirks;
  124. };
  125. /* Wait for an interrupt */
  126. static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
  127. {
  128. int timeout, int_status;
  129. for (timeout = 0; timeout < 100; timeout++) {
  130. int_status = readl(&cdns_i2c->interrupt_status);
  131. if (int_status & mask)
  132. break;
  133. udelay(100);
  134. }
  135. /* Clear interrupt status flags */
  136. writel(int_status & mask, &cdns_i2c->interrupt_status);
  137. return int_status & mask;
  138. }
  139. #define CDNS_I2C_DIVA_MAX 4
  140. #define CDNS_I2C_DIVB_MAX 64
  141. static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
  142. unsigned int *a, unsigned int *b)
  143. {
  144. unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
  145. unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
  146. unsigned int last_error, current_error;
  147. /* calculate (divisor_a+1) x (divisor_b+1) */
  148. temp = input_clk / (22 * fscl);
  149. /*
  150. * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
  151. * the fscl input is out of range. Return error.
  152. */
  153. if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
  154. return -EINVAL;
  155. last_error = -1;
  156. for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
  157. div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
  158. if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
  159. continue;
  160. div_b--;
  161. actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
  162. if (actual_fscl > fscl)
  163. continue;
  164. current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
  165. (fscl - actual_fscl));
  166. if (last_error > current_error) {
  167. calc_div_a = div_a;
  168. calc_div_b = div_b;
  169. best_fscl = actual_fscl;
  170. last_error = current_error;
  171. }
  172. }
  173. *a = calc_div_a;
  174. *b = calc_div_b;
  175. *f = best_fscl;
  176. return 0;
  177. }
  178. static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  179. {
  180. struct i2c_cdns_bus *bus = dev_get_priv(dev);
  181. u32 div_a = 0, div_b = 0;
  182. unsigned long speed_p = speed;
  183. int ret = 0;
  184. if (speed > I2C_SPEED_FAST_RATE) {
  185. debug("%s, failed to set clock speed to %u\n", __func__,
  186. speed);
  187. return -EINVAL;
  188. }
  189. ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
  190. if (ret)
  191. return ret;
  192. debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
  193. __func__, div_a, div_b, bus->input_freq, speed, speed_p);
  194. writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
  195. (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
  196. /* Enable master mode, ack, and 7-bit addressing */
  197. setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
  198. CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
  199. return 0;
  200. }
  201. static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
  202. {
  203. return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
  204. }
  205. static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
  206. u32 len)
  207. {
  208. u8 *cur_data = data;
  209. struct cdns_i2c_regs *regs = i2c_bus->regs;
  210. u32 ret;
  211. /* Set the controller in Master transmit mode and clear FIFO */
  212. setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
  213. clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
  214. /* Check message size against FIFO depth, and set hold bus bit
  215. * if it is greater than FIFO depth
  216. */
  217. if (len > CDNS_I2C_FIFO_DEPTH)
  218. setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  219. /* Clear the interrupts in status register */
  220. writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
  221. writel(addr, &regs->address);
  222. while (len-- && !is_arbitration_lost(regs)) {
  223. writel(*(cur_data++), &regs->data);
  224. if (len && readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
  225. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  226. CDNS_I2C_INTERRUPT_ARBLOST);
  227. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  228. return -EAGAIN;
  229. if (ret & CDNS_I2C_INTERRUPT_COMP)
  230. continue;
  231. /* Release the bus */
  232. clrbits_le32(&regs->control,
  233. CDNS_I2C_CONTROL_HOLD);
  234. return -ETIMEDOUT;
  235. }
  236. }
  237. if (len && is_arbitration_lost(regs))
  238. return -EAGAIN;
  239. /* All done... release the bus */
  240. if (!i2c_bus->hold_flag)
  241. clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  242. /* Wait for the address and data to be sent */
  243. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  244. CDNS_I2C_INTERRUPT_ARBLOST);
  245. if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
  246. CDNS_I2C_INTERRUPT_COMP)))
  247. return -ETIMEDOUT;
  248. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  249. return -EAGAIN;
  250. return 0;
  251. }
  252. static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
  253. {
  254. return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
  255. }
  256. static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
  257. u32 recv_count)
  258. {
  259. u8 *cur_data = data;
  260. struct cdns_i2c_regs *regs = i2c_bus->regs;
  261. u32 curr_recv_count;
  262. int updatetx, hold_quirk;
  263. u32 ret;
  264. curr_recv_count = recv_count;
  265. /* Check for the message size against the FIFO depth */
  266. if (recv_count > CDNS_I2C_FIFO_DEPTH)
  267. setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  268. setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
  269. CDNS_I2C_CONTROL_RW);
  270. if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
  271. curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
  272. writel(curr_recv_count, &regs->transfer_size);
  273. } else {
  274. writel(recv_count, &regs->transfer_size);
  275. }
  276. /* Start reading data */
  277. writel(addr, &regs->address);
  278. updatetx = recv_count > curr_recv_count;
  279. hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
  280. while (recv_count && !is_arbitration_lost(regs)) {
  281. while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
  282. if (recv_count < CDNS_I2C_FIFO_DEPTH &&
  283. !i2c_bus->hold_flag) {
  284. clrbits_le32(&regs->control,
  285. CDNS_I2C_CONTROL_HOLD);
  286. }
  287. *(cur_data)++ = readl(&regs->data);
  288. recv_count--;
  289. curr_recv_count--;
  290. if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
  291. break;
  292. }
  293. if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
  294. /* wait while fifo is full */
  295. while (readl(&regs->transfer_size) !=
  296. (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
  297. ;
  298. /*
  299. * Check number of bytes to be received against maximum
  300. * transfer size and update register accordingly.
  301. */
  302. if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
  303. CDNS_I2C_TRANSFER_SIZE) {
  304. writel(CDNS_I2C_TRANSFER_SIZE,
  305. &regs->transfer_size);
  306. curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
  307. CDNS_I2C_FIFO_DEPTH;
  308. } else {
  309. writel(recv_count - CDNS_I2C_FIFO_DEPTH,
  310. &regs->transfer_size);
  311. curr_recv_count = recv_count;
  312. }
  313. } else if (recv_count && !hold_quirk && !curr_recv_count) {
  314. writel(addr, &regs->address);
  315. if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
  316. writel(CDNS_I2C_TRANSFER_SIZE,
  317. &regs->transfer_size);
  318. curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
  319. } else {
  320. writel(recv_count, &regs->transfer_size);
  321. curr_recv_count = recv_count;
  322. }
  323. }
  324. }
  325. /* Wait for the address and data to be sent */
  326. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  327. CDNS_I2C_INTERRUPT_ARBLOST);
  328. if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
  329. CDNS_I2C_INTERRUPT_COMP)))
  330. return -ETIMEDOUT;
  331. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  332. return -EAGAIN;
  333. return 0;
  334. }
  335. static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  336. int nmsgs)
  337. {
  338. struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
  339. int ret = 0;
  340. int count;
  341. bool hold_quirk;
  342. struct i2c_msg *message = msg;
  343. int num_msgs = nmsgs;
  344. hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
  345. if (nmsgs > 1) {
  346. /*
  347. * This controller does not give completion interrupt after a
  348. * master receive message if HOLD bit is set (repeated start),
  349. * resulting in SW timeout. Hence, if a receive message is
  350. * followed by any other message, an error is returned
  351. * indicating that this sequence is not supported.
  352. */
  353. for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
  354. if (msg[count].flags & I2C_M_RD) {
  355. printf("Can't do repeated start after a receive message\n");
  356. return -EOPNOTSUPP;
  357. }
  358. }
  359. i2c_bus->hold_flag = 1;
  360. setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
  361. } else {
  362. i2c_bus->hold_flag = 0;
  363. }
  364. debug("i2c_xfer: %d messages\n", nmsgs);
  365. for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
  366. nmsgs > 0; nmsgs--, msg++) {
  367. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  368. if (msg->flags & I2C_M_RD) {
  369. ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
  370. msg->len);
  371. } else {
  372. ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
  373. msg->len);
  374. }
  375. if (ret == -EAGAIN) {
  376. msg = message;
  377. nmsgs = num_msgs;
  378. retry++;
  379. printf("%s,arbitration lost, retrying:%d\n", __func__,
  380. retry);
  381. continue;
  382. }
  383. if (ret) {
  384. debug("i2c_write: error sending\n");
  385. return -EREMOTEIO;
  386. }
  387. }
  388. return ret;
  389. }
  390. static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
  391. {
  392. struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
  393. struct cdns_i2c_platform_data *pdata =
  394. (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
  395. struct clk clk;
  396. int ret;
  397. i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
  398. if (!i2c_bus->regs)
  399. return -ENOMEM;
  400. if (pdata)
  401. i2c_bus->quirks = pdata->quirks;
  402. ret = clk_get_by_index(dev, 0, &clk);
  403. if (ret)
  404. return ret;
  405. i2c_bus->input_freq = clk_get_rate(&clk);
  406. return 0;
  407. }
  408. static const struct dm_i2c_ops cdns_i2c_ops = {
  409. .xfer = cdns_i2c_xfer,
  410. .set_bus_speed = cdns_i2c_set_bus_speed,
  411. };
  412. static const struct cdns_i2c_platform_data r1p10_i2c_def = {
  413. .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
  414. };
  415. static const struct udevice_id cdns_i2c_of_match[] = {
  416. { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
  417. { .compatible = "cdns,i2c-r1p14" },
  418. { /* end of table */ }
  419. };
  420. U_BOOT_DRIVER(cdns_i2c) = {
  421. .name = "i2c-cdns",
  422. .id = UCLASS_I2C,
  423. .of_match = cdns_i2c_of_match,
  424. .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
  425. .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
  426. .ops = &cdns_i2c_ops,
  427. };