ast_i2c.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2020 ASPEED Technology Inc.
  4. * Copyright 2016 IBM Corporation
  5. * Copyright 2017 Google, Inc.
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <i2c.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/scu_ast2500.h>
  15. #include <linux/err.h>
  16. #include "ast_i2c.h"
  17. #define I2C_TIMEOUT_US 100000
  18. #define I2C_SLEEP_STEP_US 20
  19. #define HIGHSPEED_TTIMEOUT 3
  20. /*
  21. * Device private data
  22. */
  23. struct ast_i2c_priv {
  24. /* This device's clock */
  25. struct clk clk;
  26. /* Device registers */
  27. struct ast_i2c_regs *regs;
  28. /* I2C speed in Hz */
  29. int speed;
  30. };
  31. /*
  32. * Given desired divider ratio, return the value that needs to be set
  33. * in Clock and AC Timing Control register
  34. */
  35. static u32 get_clk_reg_val(ulong divider_ratio)
  36. {
  37. ulong inc = 0, div;
  38. ulong scl_low, scl_high, data;
  39. for (div = 0; divider_ratio >= 16; div++) {
  40. inc |= (divider_ratio & 1);
  41. divider_ratio >>= 1;
  42. }
  43. divider_ratio += inc;
  44. scl_low = (divider_ratio >> 1) - 1;
  45. scl_high = divider_ratio - scl_low - 2;
  46. data = I2CD_CACTC_BASE
  47. | (scl_high << I2CD_TCKHIGH_SHIFT)
  48. | (scl_low << I2CD_TCKLOW_SHIFT)
  49. | (div << I2CD_BASE_DIV_SHIFT);
  50. return data;
  51. }
  52. static void ast_i2c_clear_interrupts(struct udevice *dev)
  53. {
  54. struct ast_i2c_priv *priv = dev_get_priv(dev);
  55. writel(~0, &priv->regs->isr);
  56. }
  57. static void ast_i2c_init_bus(struct udevice *dev)
  58. {
  59. struct ast_i2c_priv *priv = dev_get_priv(dev);
  60. /* Reset device */
  61. writel(0, &priv->regs->fcr);
  62. /* Enable Master Mode. Assuming single-master */
  63. writel(I2CD_MASTER_EN
  64. | I2CD_M_SDA_LOCK_EN
  65. | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
  66. &priv->regs->fcr);
  67. /* Enable Interrupts */
  68. writel(I2CD_INTR_TX_ACK
  69. | I2CD_INTR_TX_NAK
  70. | I2CD_INTR_RX_DONE
  71. | I2CD_INTR_BUS_RECOVER_DONE
  72. | I2CD_INTR_NORMAL_STOP
  73. | I2CD_INTR_ABNORMAL, &priv->regs->icr);
  74. }
  75. static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
  76. {
  77. struct ast_i2c_priv *priv = dev_get_priv(dev);
  78. int ret;
  79. priv->regs = devfdt_get_addr_ptr(dev);
  80. if (IS_ERR(priv->regs))
  81. return PTR_ERR(priv->regs);
  82. ret = clk_get_by_index(dev, 0, &priv->clk);
  83. if (ret < 0) {
  84. debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
  85. ret);
  86. return ret;
  87. }
  88. return 0;
  89. }
  90. static int ast_i2c_probe(struct udevice *dev)
  91. {
  92. struct ast2500_scu *scu;
  93. debug("Enabling I2C%u\n", dev->seq);
  94. /*
  95. * Get all I2C devices out of Reset.
  96. * Only needs to be done once, but doing it for every
  97. * device does not hurt.
  98. */
  99. scu = ast_get_scu();
  100. ast_scu_unlock(scu);
  101. clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
  102. ast_scu_lock(scu);
  103. ast_i2c_init_bus(dev);
  104. return 0;
  105. }
  106. static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
  107. {
  108. struct ast_i2c_priv *priv = dev_get_priv(dev);
  109. int timeout = I2C_TIMEOUT_US;
  110. while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
  111. udelay(I2C_SLEEP_STEP_US);
  112. timeout -= I2C_SLEEP_STEP_US;
  113. }
  114. ast_i2c_clear_interrupts(dev);
  115. if (timeout <= 0)
  116. return -ETIMEDOUT;
  117. return 0;
  118. }
  119. static int ast_i2c_send_stop(struct udevice *dev)
  120. {
  121. struct ast_i2c_priv *priv = dev_get_priv(dev);
  122. writel(I2CD_M_STOP_CMD, &priv->regs->csr);
  123. return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
  124. }
  125. static int ast_i2c_wait_tx(struct udevice *dev)
  126. {
  127. struct ast_i2c_priv *priv = dev_get_priv(dev);
  128. int timeout = I2C_TIMEOUT_US;
  129. u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
  130. u32 status = readl(&priv->regs->isr) & flag;
  131. int ret = 0;
  132. while (!status && timeout > 0) {
  133. status = readl(&priv->regs->isr) & flag;
  134. udelay(I2C_SLEEP_STEP_US);
  135. timeout -= I2C_SLEEP_STEP_US;
  136. }
  137. if (status == I2CD_INTR_TX_NAK)
  138. ret = -EREMOTEIO;
  139. if (timeout <= 0)
  140. ret = -ETIMEDOUT;
  141. ast_i2c_clear_interrupts(dev);
  142. return ret;
  143. }
  144. static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
  145. {
  146. struct ast_i2c_priv *priv = dev_get_priv(dev);
  147. /* Start and Send Device Address */
  148. writel(devaddr, &priv->regs->trbbr);
  149. writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
  150. return ast_i2c_wait_tx(dev);
  151. }
  152. static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
  153. size_t len, bool send_stop)
  154. {
  155. struct ast_i2c_priv *priv = dev_get_priv(dev);
  156. u32 i2c_cmd = I2CD_M_RX_CMD;
  157. int ret;
  158. ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
  159. if (ret < 0)
  160. return ret;
  161. for (; len > 0; len--, buffer++) {
  162. if (len == 1)
  163. i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
  164. writel(i2c_cmd, &priv->regs->csr);
  165. ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
  166. if (ret < 0)
  167. return ret;
  168. *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
  169. >> I2CD_RX_DATA_SHIFT;
  170. }
  171. ast_i2c_clear_interrupts(dev);
  172. if (send_stop)
  173. return ast_i2c_send_stop(dev);
  174. return 0;
  175. }
  176. static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
  177. *buffer, size_t len, bool send_stop)
  178. {
  179. struct ast_i2c_priv *priv = dev_get_priv(dev);
  180. int ret;
  181. ret = ast_i2c_start_txn(dev, (chip_addr << 1));
  182. if (ret < 0)
  183. return ret;
  184. for (; len > 0; len--, buffer++) {
  185. writel(*buffer, &priv->regs->trbbr);
  186. writel(I2CD_M_TX_CMD, &priv->regs->csr);
  187. ret = ast_i2c_wait_tx(dev);
  188. if (ret < 0)
  189. return ret;
  190. }
  191. if (send_stop)
  192. return ast_i2c_send_stop(dev);
  193. return 0;
  194. }
  195. static int ast_i2c_deblock(struct udevice *dev)
  196. {
  197. struct ast_i2c_priv *priv = dev_get_priv(dev);
  198. struct ast_i2c_regs *regs = priv->regs;
  199. u32 csr = readl(&regs->csr);
  200. bool sda_high = csr & I2CD_SDA_LINE_STS;
  201. bool scl_high = csr & I2CD_SCL_LINE_STS;
  202. int ret = 0;
  203. if (sda_high && scl_high) {
  204. /* Bus is idle, no deblocking needed. */
  205. return 0;
  206. } else if (sda_high) {
  207. /* Send stop command */
  208. debug("Unterminated TXN in (%x), sending stop\n", csr);
  209. ret = ast_i2c_send_stop(dev);
  210. } else if (scl_high) {
  211. /* Possibly stuck slave */
  212. debug("Bus stuck (%x), attempting recovery\n", csr);
  213. writel(I2CD_BUS_RECOVER_CMD, &regs->csr);
  214. ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
  215. } else {
  216. /* Just try to reinit the device. */
  217. ast_i2c_init_bus(dev);
  218. }
  219. return ret;
  220. }
  221. static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  222. {
  223. int ret;
  224. ret = ast_i2c_deblock(dev);
  225. if (ret < 0)
  226. return ret;
  227. debug("i2c_xfer: %d messages\n", nmsgs);
  228. for (; nmsgs > 0; nmsgs--, msg++) {
  229. if (msg->flags & I2C_M_RD) {
  230. debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
  231. msg->addr, msg->len, msg->flags);
  232. ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
  233. msg->len, (nmsgs == 1));
  234. } else {
  235. debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
  236. msg->addr, msg->len, msg->flags);
  237. ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
  238. msg->len, (nmsgs == 1));
  239. }
  240. if (ret) {
  241. debug("%s: error (%d)\n", __func__, ret);
  242. return -EREMOTEIO;
  243. }
  244. }
  245. return 0;
  246. }
  247. static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
  248. {
  249. struct ast_i2c_priv *priv = dev_get_priv(dev);
  250. struct ast_i2c_regs *regs = priv->regs;
  251. ulong i2c_rate, divider;
  252. debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
  253. if (!speed) {
  254. debug("No valid speed specified\n");
  255. return -EINVAL;
  256. }
  257. i2c_rate = clk_get_rate(&priv->clk);
  258. divider = i2c_rate / speed;
  259. priv->speed = speed;
  260. if (speed > I2C_SPEED_FAST_RATE) {
  261. debug("Enable High Speed\n");
  262. setbits_le32(&regs->fcr, I2CD_M_HIGH_SPEED_EN
  263. | I2CD_M_SDA_DRIVE_1T_EN
  264. | I2CD_SDA_DRIVE_1T_EN);
  265. writel(HIGHSPEED_TTIMEOUT, &regs->cactcr2);
  266. } else {
  267. debug("Enabling Normal Speed\n");
  268. writel(I2CD_NO_TIMEOUT_CTRL, &regs->cactcr2);
  269. }
  270. writel(get_clk_reg_val(divider), &regs->cactcr1);
  271. ast_i2c_clear_interrupts(dev);
  272. return 0;
  273. }
  274. static const struct dm_i2c_ops ast_i2c_ops = {
  275. .xfer = ast_i2c_xfer,
  276. .set_bus_speed = ast_i2c_set_speed,
  277. .deblock = ast_i2c_deblock,
  278. };
  279. static const struct udevice_id ast_i2c_ids[] = {
  280. { .compatible = "aspeed,ast2400-i2c-bus" },
  281. { .compatible = "aspeed,ast2500-i2c-bus" },
  282. { },
  283. };
  284. U_BOOT_DRIVER(ast_i2c) = {
  285. .name = "ast_i2c",
  286. .id = UCLASS_I2C,
  287. .of_match = ast_i2c_ids,
  288. .probe = ast_i2c_probe,
  289. .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
  290. .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
  291. .ops = &ast_i2c_ops,
  292. };