pmc.c 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <linux/arm-smccc.h>
  8. #include <asm/io.h>
  9. #include <asm/arch-tegra/pmc.h>
  10. DECLARE_GLOBAL_DATA_PTR;
  11. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  12. static bool tegra_pmc_detect_tz_only(void)
  13. {
  14. static bool initialized = false;
  15. static bool is_tz_only = false;
  16. u32 value, saved;
  17. if (!initialized) {
  18. saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
  19. value = saved ^ 0xffffffff;
  20. if (value == 0xffffffff)
  21. value = 0xdeadbeef;
  22. /* write pattern and read it back */
  23. writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
  24. value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
  25. /* if we read all-zeroes, access is restricted to TZ only */
  26. if (value == 0) {
  27. debug("access to PMC is restricted to TZ\n");
  28. is_tz_only = true;
  29. } else {
  30. /* restore original value */
  31. writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
  32. }
  33. initialized = true;
  34. }
  35. return is_tz_only;
  36. }
  37. #endif
  38. uint32_t tegra_pmc_readl(unsigned long offset)
  39. {
  40. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  41. if (tegra_pmc_detect_tz_only()) {
  42. struct arm_smccc_res res;
  43. arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
  44. 0, 0, 0, &res);
  45. if (res.a0)
  46. printf("%s(): SMC failed: %lu\n", __func__, res.a0);
  47. return res.a1;
  48. }
  49. #endif
  50. return readl(NV_PA_PMC_BASE + offset);
  51. }
  52. void tegra_pmc_writel(u32 value, unsigned long offset)
  53. {
  54. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  55. if (tegra_pmc_detect_tz_only()) {
  56. struct arm_smccc_res res;
  57. arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
  58. value, 0, 0, 0, 0, &res);
  59. if (res.a0)
  60. printf("%s(): SMC failed: %lu\n", __func__, res.a0);
  61. return;
  62. }
  63. #endif
  64. writel(value, NV_PA_PMC_BASE + offset);
  65. }
  66. void reset_cpu(ulong addr)
  67. {
  68. u32 value;
  69. value = tegra_pmc_readl(PMC_CNTRL);
  70. value |= PMC_CNTRL_MAIN_RST;
  71. tegra_pmc_writel(value, PMC_CNTRL);
  72. }