cpu.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <asm/types.h>
  7. /* Stabilization delays, in usec */
  8. #define PLL_STABILIZATION_DELAY (300)
  9. #define IO_STABILIZATION_DELAY (1000)
  10. #if defined(CONFIG_TEGRA20)
  11. #define NVBL_PLLP_KHZ 216000
  12. #define CSITE_KHZ 144000
  13. #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
  14. defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
  15. #define NVBL_PLLP_KHZ 408000
  16. #define CSITE_KHZ 136000
  17. #else
  18. #error "Unknown Tegra chip!"
  19. #endif
  20. #define PLLX_ENABLED (1 << 30)
  21. #define CCLK_BURST_POLICY 0x20008888
  22. #define SUPER_CCLK_DIVIDER 0x80000000
  23. /* Calculate clock fractional divider value from ref and target frequencies */
  24. #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
  25. /* Calculate clock frequency value from reference and clock divider value */
  26. #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
  27. /* AVP/CPU ID */
  28. #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
  29. #define PG_UP_TAG_0 0x0
  30. #define CORESIGHT_UNLOCK 0xC5ACCE55
  31. #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
  32. #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
  33. #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
  34. #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
  35. #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
  36. #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
  37. #define FLOW_MODE_STOP 2
  38. #define HALT_COP_EVENT_JTAG (1 << 28)
  39. #define HALT_COP_EVENT_IRQ_1 (1 << 11)
  40. #define HALT_COP_EVENT_FIQ_1 (1 << 9)
  41. #define FLOW_MODE_NONE 0
  42. #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
  43. /* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
  44. #define SB_AA64_RESET_LOW 0x6000C230
  45. #define SB_AA64_RESET_HIGH 0x6000C234
  46. struct clk_pll_table {
  47. u16 n;
  48. u16 m;
  49. u8 p;
  50. u8 cpcon;
  51. };
  52. void clock_enable_coresight(int enable);
  53. void enable_cpu_clock(int enable);
  54. void halt_avp(void) __attribute__ ((noreturn));
  55. void init_pllx(void);
  56. void powerup_cpu(void);
  57. void reset_A9_cpu(int reset);
  58. void start_cpu(u32 reset_vector);
  59. int tegra_get_chip(void);
  60. int tegra_get_sku_info(void);
  61. int tegra_get_chip_sku(void);
  62. void adjust_pllp_out_freqs(void);
  63. void pmic_enable_cpu_vdd(void);