cpu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/gp_padctrl.h>
  9. #include <asm/arch/pinmux.h>
  10. #include <asm/arch/tegra.h>
  11. #include <asm/arch-tegra/clk_rst.h>
  12. #include <asm/arch-tegra/pmc.h>
  13. #include <asm/arch-tegra/scu.h>
  14. #include "cpu.h"
  15. int get_num_cpus(void)
  16. {
  17. struct apb_misc_gp_ctlr *gp;
  18. uint rev;
  19. debug("%s entry\n", __func__);
  20. gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
  21. rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
  22. switch (rev) {
  23. case CHIPID_TEGRA20:
  24. return 2;
  25. break;
  26. case CHIPID_TEGRA30:
  27. case CHIPID_TEGRA114:
  28. case CHIPID_TEGRA124:
  29. case CHIPID_TEGRA210:
  30. default:
  31. return 4;
  32. break;
  33. }
  34. }
  35. /*
  36. * Timing tables for each SOC for all four oscillator options.
  37. */
  38. struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
  39. /*
  40. * T20: 1 GHz
  41. *
  42. * Register Field Bits Width
  43. * ------------------------------
  44. * PLLX_BASE p 22:20 3
  45. * PLLX_BASE n 17: 8 10
  46. * PLLX_BASE m 4: 0 5
  47. * PLLX_MISC cpcon 11: 8 4
  48. */
  49. {
  50. { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
  51. { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
  52. { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
  53. { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
  54. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
  55. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
  56. },
  57. /*
  58. * T25: 1.2 GHz
  59. *
  60. * Register Field Bits Width
  61. * ------------------------------
  62. * PLLX_BASE p 22:20 3
  63. * PLLX_BASE n 17: 8 10
  64. * PLLX_BASE m 4: 0 5
  65. * PLLX_MISC cpcon 11: 8 4
  66. */
  67. {
  68. { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
  69. { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
  70. { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
  71. { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
  72. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
  73. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
  74. },
  75. /*
  76. * T30: 600 MHz
  77. *
  78. * Register Field Bits Width
  79. * ------------------------------
  80. * PLLX_BASE p 22:20 3
  81. * PLLX_BASE n 17: 8 10
  82. * PLLX_BASE m 4: 0 5
  83. * PLLX_MISC cpcon 11: 8 4
  84. */
  85. {
  86. { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
  87. { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
  88. { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
  89. { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
  90. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
  91. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
  92. },
  93. /*
  94. * T114: 700 MHz
  95. *
  96. * Register Field Bits Width
  97. * ------------------------------
  98. * PLLX_BASE p 23:20 4
  99. * PLLX_BASE n 15: 8 8
  100. * PLLX_BASE m 7: 0 8
  101. */
  102. {
  103. { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
  104. { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
  105. { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
  106. { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
  107. { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
  108. { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
  109. },
  110. /*
  111. * T124: 700 MHz
  112. *
  113. * Register Field Bits Width
  114. * ------------------------------
  115. * PLLX_BASE p 23:20 4
  116. * PLLX_BASE n 15: 8 8
  117. * PLLX_BASE m 7: 0 8
  118. */
  119. {
  120. { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
  121. { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
  122. { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
  123. { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
  124. { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
  125. { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
  126. },
  127. /*
  128. * T210: 700 MHz
  129. *
  130. * Register Field Bits Width
  131. * ------------------------------
  132. * PLLX_BASE p 24:20 5
  133. * PLLX_BASE n 15: 8 8
  134. * PLLX_BASE m 7: 0 8
  135. */
  136. {
  137. { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
  138. { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
  139. { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
  140. { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
  141. { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
  142. { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
  143. },
  144. };
  145. static inline void pllx_set_iddq(void)
  146. {
  147. #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
  148. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  149. u32 reg;
  150. debug("%s entry\n", __func__);
  151. /* Disable IDDQ */
  152. reg = readl(&clkrst->crc_pllx_misc3);
  153. reg &= ~PLLX_IDDQ_MASK;
  154. writel(reg, &clkrst->crc_pllx_misc3);
  155. udelay(2);
  156. debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
  157. readl(&clkrst->crc_pllx_misc3));
  158. #endif
  159. }
  160. int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
  161. u32 divp, u32 cpcon)
  162. {
  163. struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
  164. int chip = tegra_get_chip();
  165. u32 reg;
  166. debug("%s entry\n", __func__);
  167. /* If PLLX is already enabled, just return */
  168. if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
  169. debug("%s: PLLX already enabled, returning\n", __func__);
  170. return 0;
  171. }
  172. pllx_set_iddq();
  173. /* Set BYPASS, m, n and p to PLLX_BASE */
  174. reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
  175. reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
  176. writel(reg, &pll->pll_base);
  177. /* Set cpcon to PLLX_MISC */
  178. if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
  179. reg = (cpcon << pllinfo->kcp_shift);
  180. else
  181. reg = 0;
  182. /*
  183. * TODO(twarren@nvidia.com) Check which SoCs use DCCON
  184. * and add to pllinfo table if needed!
  185. */
  186. /* Set dccon to PLLX_MISC if freq > 600MHz */
  187. if (divn > 600)
  188. reg |= (1 << PLL_DCCON_SHIFT);
  189. writel(reg, &pll->pll_misc);
  190. /* Disable BYPASS */
  191. reg = readl(&pll->pll_base);
  192. reg &= ~PLL_BYPASS_MASK;
  193. writel(reg, &pll->pll_base);
  194. debug("%s: base = 0x%08X\n", __func__, reg);
  195. /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
  196. reg = readl(&pll->pll_misc);
  197. if (pllinfo->lock_ena < 32)
  198. reg |= (1 << pllinfo->lock_ena);
  199. writel(reg, &pll->pll_misc);
  200. debug("%s: misc = 0x%08X\n", __func__, reg);
  201. /* Enable PLLX last, once it's all configured */
  202. reg = readl(&pll->pll_base);
  203. reg |= PLL_ENABLE_MASK;
  204. writel(reg, &pll->pll_base);
  205. debug("%s: base final = 0x%08X\n", __func__, reg);
  206. return 0;
  207. }
  208. void init_pllx(void)
  209. {
  210. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  211. struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
  212. int soc_type, sku_info, chip_sku;
  213. enum clock_osc_freq osc;
  214. struct clk_pll_table *sel;
  215. debug("%s entry\n", __func__);
  216. /* get SOC (chip) type */
  217. soc_type = tegra_get_chip();
  218. debug("%s: SoC = 0x%02X\n", __func__, soc_type);
  219. /* get SKU info */
  220. sku_info = tegra_get_sku_info();
  221. debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
  222. /* get chip SKU, combo of the above info */
  223. chip_sku = tegra_get_chip_sku();
  224. debug("%s: Chip SKU = %d\n", __func__, chip_sku);
  225. /* get osc freq */
  226. osc = clock_get_osc_freq();
  227. debug("%s: osc = %d\n", __func__, osc);
  228. /* set pllx */
  229. sel = &tegra_pll_x_table[chip_sku][osc];
  230. pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
  231. }
  232. void enable_cpu_clock(int enable)
  233. {
  234. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  235. u32 clk;
  236. debug("%s entry\n", __func__);
  237. /*
  238. * NOTE:
  239. * Regardless of whether the request is to enable or disable the CPU
  240. * clock, every processor in the CPU complex except the master (CPU 0)
  241. * will have it's clock stopped because the AVP only talks to the
  242. * master.
  243. */
  244. if (enable) {
  245. /* Initialize PLLX */
  246. init_pllx();
  247. /* Wait until all clocks are stable */
  248. udelay(PLL_STABILIZATION_DELAY);
  249. writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
  250. writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
  251. }
  252. /*
  253. * Read the register containing the individual CPU clock enables and
  254. * always stop the clocks to CPUs > 0.
  255. */
  256. clk = readl(&clkrst->crc_clk_cpu_cmplx);
  257. clk |= 1 << CPU1_CLK_STP_SHIFT;
  258. if (get_num_cpus() == 4)
  259. clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
  260. /* Stop/Unstop the CPU clock */
  261. clk &= ~CPU0_CLK_STP_MASK;
  262. clk |= !enable << CPU0_CLK_STP_SHIFT;
  263. writel(clk, &clkrst->crc_clk_cpu_cmplx);
  264. clock_enable(PERIPH_ID_CPU);
  265. }
  266. static int is_cpu_powered(void)
  267. {
  268. return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
  269. pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
  270. }
  271. static void remove_cpu_io_clamps(void)
  272. {
  273. u32 reg;
  274. debug("%s entry\n", __func__);
  275. /* Remove the clamps on the CPU I/O signals */
  276. reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
  277. reg |= CPU_CLMP;
  278. tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
  279. /* Give I/O signals time to stabilize */
  280. udelay(IO_STABILIZATION_DELAY);
  281. }
  282. void powerup_cpu(void)
  283. {
  284. u32 reg;
  285. int timeout = IO_STABILIZATION_DELAY;
  286. debug("%s entry\n", __func__);
  287. if (!is_cpu_powered()) {
  288. /* Toggle the CPU power state (OFF -> ON) */
  289. reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
  290. pmc_pwrgate_toggle));
  291. reg &= PARTID_CP;
  292. reg |= START_CP;
  293. tegra_pmc_writel(reg,
  294. offsetof(struct pmc_ctlr,
  295. pmc_pwrgate_toggle));
  296. /* Wait for the power to come up */
  297. while (!is_cpu_powered()) {
  298. if (timeout-- == 0)
  299. printf("CPU failed to power up!\n");
  300. else
  301. udelay(10);
  302. }
  303. /*
  304. * Remove the I/O clamps from CPU power partition.
  305. * Recommended only on a Warm boot, if the CPU partition gets
  306. * power gated. Shouldn't cause any harm when called after a
  307. * cold boot according to HW, probably just redundant.
  308. */
  309. remove_cpu_io_clamps();
  310. }
  311. }
  312. void reset_A9_cpu(int reset)
  313. {
  314. /*
  315. * NOTE: Regardless of whether the request is to hold the CPU in reset
  316. * or take it out of reset, every processor in the CPU complex
  317. * except the master (CPU 0) will be held in reset because the
  318. * AVP only talks to the master. The AVP does not know that there
  319. * are multiple processors in the CPU complex.
  320. */
  321. int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
  322. int num_cpus = get_num_cpus();
  323. int cpu;
  324. debug("%s entry\n", __func__);
  325. /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
  326. for (cpu = 1; cpu < num_cpus; cpu++)
  327. reset_cmplx_set_enable(cpu, mask, 1);
  328. reset_cmplx_set_enable(0, mask, reset);
  329. /* Enable/Disable master CPU reset */
  330. reset_set_enable(PERIPH_ID_CPU, reset);
  331. }
  332. void clock_enable_coresight(int enable)
  333. {
  334. u32 rst, src = 2;
  335. debug("%s entry\n", __func__);
  336. clock_set_enable(PERIPH_ID_CORESIGHT, enable);
  337. reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
  338. if (enable) {
  339. /*
  340. * Put CoreSight on PLLP_OUT0 and divide it down as per
  341. * PLLP base frequency based on SoC type (T20/T30+).
  342. * Clock divider request would setup CSITE clock as 144MHz
  343. * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
  344. */
  345. src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
  346. clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
  347. /* Unlock the CPU CoreSight interfaces */
  348. rst = CORESIGHT_UNLOCK;
  349. writel(rst, CSITE_CPU_DBG0_LAR);
  350. writel(rst, CSITE_CPU_DBG1_LAR);
  351. if (get_num_cpus() == 4) {
  352. writel(rst, CSITE_CPU_DBG2_LAR);
  353. writel(rst, CSITE_CPU_DBG3_LAR);
  354. }
  355. }
  356. }
  357. void halt_avp(void)
  358. {
  359. debug("%s entry\n", __func__);
  360. for (;;) {
  361. writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
  362. FLOW_CTLR_HALT_COP_EVENTS);
  363. }
  364. }