virtex2.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  5. * Keith Outwater, keith_outwater@mvis.com
  6. *
  7. * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
  8. */
  9. /*
  10. * Configuration support for Xilinx Virtex2 devices. Based
  11. * on spartan2.c (Rich Ireland, rireland@enterasys.com).
  12. */
  13. #include <common.h>
  14. #include <console.h>
  15. #include <virtex2.h>
  16. #if 0
  17. #define FPGA_DEBUG
  18. #endif
  19. #ifdef FPGA_DEBUG
  20. #define PRINTF(fmt, args...) printf(fmt, ##args)
  21. #else
  22. #define PRINTF(fmt, args...)
  23. #endif
  24. /*
  25. * If the SelectMap interface can be overrun by the processor, define
  26. * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
  27. * configuration file and add board-specific support for checking BUSY status.
  28. * By default, assume that the SelectMap interface cannot be overrun.
  29. */
  30. #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
  31. #undef CONFIG_SYS_FPGA_CHECK_BUSY
  32. #endif
  33. #ifndef CONFIG_FPGA_DELAY
  34. #define CONFIG_FPGA_DELAY()
  35. #endif
  36. #ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
  37. #define CONFIG_SYS_FPGA_PROG_FEEDBACK
  38. #endif
  39. /*
  40. * Don't allow config cycle to be interrupted
  41. */
  42. #ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
  43. #undef CONFIG_SYS_FPGA_CHECK_CTRLC
  44. #endif
  45. /*
  46. * Check for errors during configuration by default
  47. */
  48. #ifndef CONFIG_SYS_FPGA_CHECK_ERROR
  49. #define CONFIG_SYS_FPGA_CHECK_ERROR
  50. #endif
  51. /*
  52. * The default timeout in mS for INIT_B to deassert after PROG_B has
  53. * been deasserted. Per the latest Virtex II Handbook (page 347), the
  54. * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
  55. * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
  56. * which yields 11.44 mS. So let's make it bigger in order to handle
  57. * an XC2V1000, if anyone can ever get ahold of one.
  58. */
  59. #ifndef CONFIG_SYS_FPGA_WAIT_INIT
  60. #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
  61. #endif
  62. /*
  63. * The default timeout for waiting for BUSY to deassert during configuration.
  64. * This is normally not necessary since for most reasonable configuration
  65. * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  66. */
  67. #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
  68. #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
  69. #endif
  70. /* Default timeout for waiting for FPGA to enter operational mode after
  71. * configuration data has been written.
  72. */
  73. #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
  74. #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
  75. #endif
  76. static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
  77. static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  78. static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
  79. static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  80. static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
  81. bitstream_type bstype)
  82. {
  83. int ret_val = FPGA_FAIL;
  84. switch (desc->iface) {
  85. case slave_serial:
  86. PRINTF("%s: Launching Slave Serial Load\n", __func__);
  87. ret_val = virtex2_ss_load(desc, buf, bsize);
  88. break;
  89. case slave_selectmap:
  90. PRINTF("%s: Launching Slave Parallel Load\n", __func__);
  91. ret_val = virtex2_ssm_load(desc, buf, bsize);
  92. break;
  93. default:
  94. printf("%s: Unsupported interface type, %d\n",
  95. __func__, desc->iface);
  96. }
  97. return ret_val;
  98. }
  99. static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  100. {
  101. int ret_val = FPGA_FAIL;
  102. switch (desc->iface) {
  103. case slave_serial:
  104. PRINTF("%s: Launching Slave Serial Dump\n", __func__);
  105. ret_val = virtex2_ss_dump(desc, buf, bsize);
  106. break;
  107. case slave_parallel:
  108. PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
  109. ret_val = virtex2_ssm_dump(desc, buf, bsize);
  110. break;
  111. default:
  112. printf("%s: Unsupported interface type, %d\n",
  113. __func__, desc->iface);
  114. }
  115. return ret_val;
  116. }
  117. static int virtex2_info(xilinx_desc *desc)
  118. {
  119. return FPGA_SUCCESS;
  120. }
  121. /*
  122. * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
  123. * is as follows:
  124. * 1. Set the FPGA's PROG_B line low.
  125. * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
  126. * 3. Write data to the SelectMap port. If INIT_B goes low at any time
  127. * this process, a configuration error (most likely CRC failure) has
  128. * ocurred. At this point a status word may be read from the
  129. * SelectMap interface to determine the source of the problem (You
  130. * could, for instance, put this in your 'abort' function handler).
  131. * 4. After all data has been written, test the state of the FPGA
  132. * INIT_B and DONE lines. If both are high, configuration has
  133. * succeeded. Congratulations!
  134. */
  135. static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
  136. {
  137. unsigned long ts;
  138. PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
  139. __func__, __LINE__, fn);
  140. if (!fn) {
  141. printf("%s:%d: NULL Interface function table!\n",
  142. __func__, __LINE__);
  143. return FPGA_FAIL;
  144. }
  145. /* Gotta split this one up (so the stack won't blow??) */
  146. PRINTF("%s:%d: Function Table:\n"
  147. " base 0x%p\n"
  148. " struct 0x%p\n"
  149. " pre 0x%p\n"
  150. " prog 0x%p\n"
  151. " init 0x%p\n"
  152. " error 0x%p\n",
  153. __func__, __LINE__,
  154. &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
  155. PRINTF(" clock 0x%p\n"
  156. " cs 0x%p\n"
  157. " write 0x%p\n"
  158. " rdata 0x%p\n"
  159. " wdata 0x%p\n"
  160. " busy 0x%p\n"
  161. " abort 0x%p\n"
  162. " post 0x%p\n\n",
  163. fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
  164. fn->busy, fn->abort, fn->post);
  165. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  166. printf("Initializing FPGA Device %d...\n", cookie);
  167. #endif
  168. /*
  169. * Run the pre configuration function if there is one.
  170. */
  171. if (*fn->pre)
  172. (*fn->pre)(cookie);
  173. /*
  174. * Assert the program line. The minimum pulse width for
  175. * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
  176. * There is no maximum value for the pulse width. Check to make
  177. * sure that INIT_B goes low after assertion of PROG_B
  178. */
  179. (*fn->pgm)(true, true, cookie);
  180. udelay(10);
  181. ts = get_timer(0);
  182. do {
  183. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
  184. printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
  185. __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
  186. (*fn->abort)(cookie);
  187. return FPGA_FAIL;
  188. }
  189. } while (!(*fn->init)(cookie));
  190. (*fn->pgm)(false, true, cookie);
  191. CONFIG_FPGA_DELAY();
  192. if (fn->clk)
  193. (*fn->clk)(true, true, cookie);
  194. /*
  195. * Start a timer and wait for INIT_B to go high
  196. */
  197. ts = get_timer(0);
  198. do {
  199. CONFIG_FPGA_DELAY();
  200. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
  201. printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
  202. __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
  203. (*fn->abort)(cookie);
  204. return FPGA_FAIL;
  205. }
  206. } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
  207. if (fn->wr)
  208. (*fn->wr)(true, true, cookie);
  209. if (fn->cs)
  210. (*fn->cs)(true, true, cookie);
  211. mdelay(10);
  212. return FPGA_SUCCESS;
  213. }
  214. static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
  215. int cookie)
  216. {
  217. int ret_val = FPGA_SUCCESS;
  218. int num_done = 0;
  219. unsigned long ts;
  220. /*
  221. * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
  222. */
  223. CONFIG_FPGA_DELAY();
  224. if (fn->cs)
  225. (*fn->cs)(false, true, cookie);
  226. if (fn->wr)
  227. (*fn->wr)(false, true, cookie);
  228. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  229. putc('\n');
  230. #endif
  231. /*
  232. * Check for successful configuration. FPGA INIT_B and DONE
  233. * should both be high upon successful configuration. Continue pulsing
  234. * clock with data set to all ones until DONE is asserted and for 8
  235. * clock cycles afterwards.
  236. */
  237. ts = get_timer(0);
  238. while (true) {
  239. if ((*fn->done)(cookie) == FPGA_SUCCESS &&
  240. !((*fn->init)(cookie))) {
  241. if (num_done++ >= 8)
  242. break;
  243. }
  244. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
  245. printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
  246. __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
  247. (*fn->abort)(cookie);
  248. ret_val = FPGA_FAIL;
  249. break;
  250. }
  251. if (fn->wbulkdata) {
  252. unsigned char dummy = 0xff;
  253. (*fn->wbulkdata)(&dummy, 1, true, cookie);
  254. } else {
  255. (*fn->wdata)(0xff, true, cookie);
  256. CONFIG_FPGA_DELAY();
  257. (*fn->clk)(false, true, cookie);
  258. CONFIG_FPGA_DELAY();
  259. (*fn->clk)(true, true, cookie);
  260. }
  261. }
  262. if (ret_val == FPGA_SUCCESS) {
  263. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  264. printf("Initialization of FPGA device %d complete\n", cookie);
  265. #endif
  266. /*
  267. * Run the post configuration function if there is one.
  268. */
  269. if (*fn->post)
  270. (*fn->post)(cookie);
  271. } else {
  272. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  273. printf("** Initialization of FPGA device %d FAILED\n",
  274. cookie);
  275. #endif
  276. }
  277. return ret_val;
  278. }
  279. static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
  280. {
  281. int ret_val = FPGA_FAIL;
  282. xilinx_virtex2_slave_fns *fn = desc->iface_fns;
  283. size_t bytecount = 0;
  284. unsigned char *data = (unsigned char *)buf;
  285. int cookie = desc->cookie;
  286. ret_val = virtex2_slave_pre(fn, cookie);
  287. if (ret_val != FPGA_SUCCESS)
  288. return ret_val;
  289. /*
  290. * Load the data byte by byte
  291. */
  292. while (bytecount < bsize) {
  293. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  294. if (ctrlc()) {
  295. (*fn->abort)(cookie);
  296. return FPGA_FAIL;
  297. }
  298. #endif
  299. if ((*fn->done)(cookie) == FPGA_SUCCESS) {
  300. PRINTF("%s:%d:done went active early, bytecount = %d\n",
  301. __func__, __LINE__, bytecount);
  302. break;
  303. }
  304. #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
  305. if ((*fn->init)(cookie)) {
  306. printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
  307. __func__, __LINE__);
  308. printf("%zu = buffer offset, %zu = buffer size\n",
  309. bytecount, bsize);
  310. (*fn->abort)(cookie);
  311. return FPGA_FAIL;
  312. }
  313. #endif
  314. (*fn->wdata)(data[bytecount++], true, cookie);
  315. CONFIG_FPGA_DELAY();
  316. /*
  317. * Cycle the clock pin
  318. */
  319. (*fn->clk)(false, true, cookie);
  320. CONFIG_FPGA_DELAY();
  321. (*fn->clk)(true, true, cookie);
  322. #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
  323. ts = get_timer(0);
  324. while ((*fn->busy)(cookie)) {
  325. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
  326. printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
  327. __func__, __LINE__,
  328. CONFIG_SYS_FPGA_WAIT_BUSY);
  329. (*fn->abort)(cookie);
  330. return FPGA_FAIL;
  331. }
  332. }
  333. #endif
  334. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  335. if (bytecount % (bsize / 40) == 0)
  336. putc('.');
  337. #endif
  338. }
  339. return virtex2_slave_post(fn, cookie);
  340. }
  341. /*
  342. * Read the FPGA configuration data
  343. */
  344. static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  345. {
  346. int ret_val = FPGA_FAIL;
  347. xilinx_virtex2_slave_fns *fn = desc->iface_fns;
  348. if (fn) {
  349. unsigned char *data = (unsigned char *)buf;
  350. size_t bytecount = 0;
  351. int cookie = desc->cookie;
  352. printf("Starting Dump of FPGA Device %d...\n", cookie);
  353. (*fn->cs)(true, true, cookie);
  354. (*fn->clk)(true, true, cookie);
  355. while (bytecount < bsize) {
  356. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  357. if (ctrlc()) {
  358. (*fn->abort)(cookie);
  359. return FPGA_FAIL;
  360. }
  361. #endif
  362. /*
  363. * Cycle the clock and read the data
  364. */
  365. (*fn->clk)(false, true, cookie);
  366. (*fn->clk)(true, true, cookie);
  367. (*fn->rdata)(&data[bytecount++], cookie);
  368. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  369. if (bytecount % (bsize / 40) == 0)
  370. putc('.');
  371. #endif
  372. }
  373. /*
  374. * Deassert CS_B and cycle the clock to deselect the device.
  375. */
  376. (*fn->cs)(false, false, cookie);
  377. (*fn->clk)(false, true, cookie);
  378. (*fn->clk)(true, true, cookie);
  379. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  380. putc('\n');
  381. #endif
  382. puts("Done.\n");
  383. } else {
  384. printf("%s:%d: NULL Interface function table!\n",
  385. __func__, __LINE__);
  386. }
  387. return ret_val;
  388. }
  389. static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
  390. {
  391. int ret_val = FPGA_FAIL;
  392. xilinx_virtex2_slave_fns *fn = desc->iface_fns;
  393. unsigned char *data = (unsigned char *)buf;
  394. int cookie = desc->cookie;
  395. ret_val = virtex2_slave_pre(fn, cookie);
  396. if (ret_val != FPGA_SUCCESS)
  397. return ret_val;
  398. if (fn->wbulkdata) {
  399. /* Load the data in a single chunk */
  400. (*fn->wbulkdata)(data, bsize, true, cookie);
  401. } else {
  402. size_t bytecount = 0;
  403. /*
  404. * Load the data bit by bit
  405. */
  406. while (bytecount < bsize) {
  407. unsigned char curr_data = data[bytecount++];
  408. int bit;
  409. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  410. if (ctrlc()) {
  411. (*fn->abort) (cookie);
  412. return FPGA_FAIL;
  413. }
  414. #endif
  415. if ((*fn->done)(cookie) == FPGA_SUCCESS) {
  416. PRINTF("%s:%d:done went active early, bytecount = %d\n",
  417. __func__, __LINE__, bytecount);
  418. break;
  419. }
  420. #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
  421. if ((*fn->init)(cookie)) {
  422. printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
  423. __func__, __LINE__);
  424. printf("%zu = buffer offset, %zu = buffer size\n",
  425. bytecount, bsize);
  426. (*fn->abort)(cookie);
  427. return FPGA_FAIL;
  428. }
  429. #endif
  430. for (bit = 7; bit >= 0; --bit) {
  431. unsigned char curr_bit = (curr_data >> bit) & 1;
  432. (*fn->wdata)(curr_bit, true, cookie);
  433. CONFIG_FPGA_DELAY();
  434. (*fn->clk)(false, true, cookie);
  435. CONFIG_FPGA_DELAY();
  436. (*fn->clk)(true, true, cookie);
  437. }
  438. /* Slave serial never uses a busy pin */
  439. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  440. if (bytecount % (bsize / 40) == 0)
  441. putc('.');
  442. #endif
  443. }
  444. }
  445. return virtex2_slave_post(fn, cookie);
  446. }
  447. static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  448. {
  449. printf("%s: Slave Serial Dumping is unsupported\n", __func__);
  450. return FPGA_FAIL;
  451. }
  452. /* vim: set ts=4 tw=78: */
  453. struct xilinx_fpga_op virtex2_op = {
  454. .load = virtex2_load,
  455. .dump = virtex2_dump,
  456. .info = virtex2_info,
  457. };