rk_vop.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright 2014 Rockchip Inc.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <video.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-rockchip/clock.h>
  17. #include <asm/arch-rockchip/edp_rk3288.h>
  18. #include <asm/arch-rockchip/vop_rk3288.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/uclass-internal.h>
  21. #include <power/regulator.h>
  22. #include "rk_vop.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. enum vop_pol {
  25. HSYNC_POSITIVE = 0,
  26. VSYNC_POSITIVE = 1,
  27. DEN_NEGATIVE = 2,
  28. DCLK_INVERT = 3
  29. };
  30. static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
  31. int fb_bits_per_pixel,
  32. const struct display_timing *edid)
  33. {
  34. u32 lb_mode;
  35. u32 rgb_mode;
  36. u32 hactive = edid->hactive.typ;
  37. u32 vactive = edid->vactive.typ;
  38. writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
  39. &regs->win0_act_info);
  40. writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
  41. V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
  42. &regs->win0_dsp_st);
  43. writel(V_DSP_WIDTH(hactive - 1) |
  44. V_DSP_HEIGHT(vactive - 1),
  45. &regs->win0_dsp_info);
  46. clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
  47. V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
  48. switch (fb_bits_per_pixel) {
  49. case 16:
  50. rgb_mode = RGB565;
  51. writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
  52. break;
  53. case 24:
  54. rgb_mode = RGB888;
  55. writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
  56. break;
  57. case 32:
  58. default:
  59. rgb_mode = ARGB8888;
  60. writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
  61. break;
  62. }
  63. if (hactive > 2560)
  64. lb_mode = LB_RGB_3840X2;
  65. else if (hactive > 1920)
  66. lb_mode = LB_RGB_2560X4;
  67. else if (hactive > 1280)
  68. lb_mode = LB_RGB_1920X5;
  69. else
  70. lb_mode = LB_RGB_1280X8;
  71. clrsetbits_le32(&regs->win0_ctrl0,
  72. M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
  73. V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
  74. V_WIN0_EN(1));
  75. writel(fbbase, &regs->win0_yrgb_mst);
  76. writel(0x01, &regs->reg_cfg_done); /* enable reg config */
  77. }
  78. static void rkvop_set_pin_polarity(struct udevice *dev,
  79. enum vop_modes mode, u32 polarity)
  80. {
  81. struct rkvop_driverdata *ops =
  82. (struct rkvop_driverdata *)dev_get_driver_data(dev);
  83. if (ops->set_pin_polarity)
  84. ops->set_pin_polarity(dev, mode, polarity);
  85. }
  86. static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
  87. {
  88. struct rk_vop_priv *priv = dev_get_priv(dev);
  89. struct rk3288_vop *regs = priv->regs;
  90. /* remove from standby */
  91. clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));
  92. switch (mode) {
  93. case VOP_MODE_HDMI:
  94. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  95. V_HDMI_OUT_EN(1));
  96. break;
  97. case VOP_MODE_EDP:
  98. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  99. V_EDP_OUT_EN(1));
  100. break;
  101. case VOP_MODE_LVDS:
  102. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  103. V_RGB_OUT_EN(1));
  104. break;
  105. case VOP_MODE_MIPI:
  106. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  107. V_MIPI_OUT_EN(1));
  108. break;
  109. default:
  110. debug("%s: unsupported output mode %x\n", __func__, mode);
  111. }
  112. }
  113. static void rkvop_mode_set(struct udevice *dev,
  114. const struct display_timing *edid,
  115. enum vop_modes mode)
  116. {
  117. struct rk_vop_priv *priv = dev_get_priv(dev);
  118. struct rk3288_vop *regs = priv->regs;
  119. struct rkvop_driverdata *data =
  120. (struct rkvop_driverdata *)dev_get_driver_data(dev);
  121. u32 hactive = edid->hactive.typ;
  122. u32 vactive = edid->vactive.typ;
  123. u32 hsync_len = edid->hsync_len.typ;
  124. u32 hback_porch = edid->hback_porch.typ;
  125. u32 vsync_len = edid->vsync_len.typ;
  126. u32 vback_porch = edid->vback_porch.typ;
  127. u32 hfront_porch = edid->hfront_porch.typ;
  128. u32 vfront_porch = edid->vfront_porch.typ;
  129. int mode_flags;
  130. u32 pin_polarity;
  131. pin_polarity = BIT(DCLK_INVERT);
  132. if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
  133. pin_polarity |= BIT(HSYNC_POSITIVE);
  134. if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
  135. pin_polarity |= BIT(VSYNC_POSITIVE);
  136. rkvop_set_pin_polarity(dev, mode, pin_polarity);
  137. rkvop_enable_output(dev, mode);
  138. mode_flags = 0; /* RGB888 */
  139. if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
  140. (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
  141. mode_flags = 15; /* RGBaaa */
  142. clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
  143. V_DSP_OUT_MODE(mode_flags));
  144. writel(V_HSYNC(hsync_len) |
  145. V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
  146. &regs->dsp_htotal_hs_end);
  147. writel(V_HEAP(hsync_len + hback_porch + hactive) |
  148. V_HASP(hsync_len + hback_porch),
  149. &regs->dsp_hact_st_end);
  150. writel(V_VSYNC(vsync_len) |
  151. V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
  152. &regs->dsp_vtotal_vs_end);
  153. writel(V_VAEP(vsync_len + vback_porch + vactive)|
  154. V_VASP(vsync_len + vback_porch),
  155. &regs->dsp_vact_st_end);
  156. writel(V_HEAP(hsync_len + hback_porch + hactive) |
  157. V_HASP(hsync_len + hback_porch),
  158. &regs->post_dsp_hact_info);
  159. writel(V_VAEP(vsync_len + vback_porch + vactive)|
  160. V_VASP(vsync_len + vback_porch),
  161. &regs->post_dsp_vact_info);
  162. writel(0x01, &regs->reg_cfg_done); /* enable reg config */
  163. }
  164. /**
  165. * rk_display_init() - Try to enable the given display device
  166. *
  167. * This function performs many steps:
  168. * - Finds the display device being referenced by @ep_node
  169. * - Puts the VOP's ID into its uclass platform data
  170. * - Probes the device to set it up
  171. * - Reads the EDID timing information
  172. * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
  173. * - Enables the display (the display device handles this and will do different
  174. * things depending on the display type)
  175. * - Tells the uclass about the display resolution so that the console will
  176. * appear correctly
  177. *
  178. * @dev: VOP device that we want to connect to the display
  179. * @fbbase: Frame buffer address
  180. * @ep_node: Device tree node to process - this is the offset of an endpoint
  181. * node within the VOP's 'port' list.
  182. * @return 0 if OK, -ve if something went wrong
  183. */
  184. static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
  185. {
  186. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  187. struct rk_vop_priv *priv = dev_get_priv(dev);
  188. int vop_id, remote_vop_id;
  189. struct rk3288_vop *regs = priv->regs;
  190. struct display_timing timing;
  191. struct udevice *disp;
  192. int ret;
  193. u32 remote_phandle;
  194. struct display_plat *disp_uc_plat;
  195. struct clk clk;
  196. enum video_log2_bpp l2bpp;
  197. ofnode remote;
  198. debug("%s(%s, %lu, %s)\n", __func__,
  199. dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
  200. vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
  201. debug("vop_id=%d\n", vop_id);
  202. ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
  203. if (ret)
  204. return ret;
  205. remote = ofnode_get_by_phandle(remote_phandle);
  206. if (!ofnode_valid(remote))
  207. return -EINVAL;
  208. remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
  209. debug("remote vop_id=%d\n", remote_vop_id);
  210. /*
  211. * The remote-endpoint references into a subnode of the encoder
  212. * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
  213. * the following (assume 'hdmi_in_vopl' to be referenced):
  214. *
  215. * hdmi: hdmi@ff940000 {
  216. * ports {
  217. * hdmi_in: port {
  218. * hdmi_in_vopb: endpoint@0 { ... };
  219. * hdmi_in_vopl: endpoint@1 { ... };
  220. * }
  221. * }
  222. * }
  223. *
  224. * The original code had 3 steps of "walking the parent", but
  225. * a much better (as in: less likely to break if the DTS
  226. * changes) way of doing this is to "find the enclosing device
  227. * of UCLASS_DISPLAY".
  228. */
  229. while (ofnode_valid(remote)) {
  230. remote = ofnode_get_parent(remote);
  231. if (!ofnode_valid(remote)) {
  232. debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
  233. __func__, dev_read_name(dev));
  234. return -EINVAL;
  235. }
  236. uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
  237. if (disp)
  238. break;
  239. };
  240. disp_uc_plat = dev_get_uclass_platdata(disp);
  241. debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
  242. if (display_in_use(disp)) {
  243. debug(" - device in use\n");
  244. return -EBUSY;
  245. }
  246. disp_uc_plat->source_id = remote_vop_id;
  247. disp_uc_plat->src_dev = dev;
  248. ret = device_probe(disp);
  249. if (ret) {
  250. debug("%s: device '%s' display won't probe (ret=%d)\n",
  251. __func__, dev->name, ret);
  252. return ret;
  253. }
  254. ret = display_read_timing(disp, &timing);
  255. if (ret) {
  256. debug("%s: Failed to read timings\n", __func__);
  257. return ret;
  258. }
  259. ret = clk_get_by_index(dev, 1, &clk);
  260. if (!ret)
  261. ret = clk_set_rate(&clk, timing.pixelclock.typ);
  262. if (IS_ERR_VALUE(ret)) {
  263. debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
  264. return ret;
  265. }
  266. /* Set bitwidth for vop display according to vop mode */
  267. switch (vop_id) {
  268. case VOP_MODE_EDP:
  269. case VOP_MODE_LVDS:
  270. l2bpp = VIDEO_BPP16;
  271. break;
  272. case VOP_MODE_HDMI:
  273. case VOP_MODE_MIPI:
  274. l2bpp = VIDEO_BPP32;
  275. break;
  276. default:
  277. l2bpp = VIDEO_BPP16;
  278. }
  279. rkvop_mode_set(dev, &timing, vop_id);
  280. rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
  281. ret = display_enable(disp, 1 << l2bpp, &timing);
  282. if (ret)
  283. return ret;
  284. uc_priv->xsize = timing.hactive.typ;
  285. uc_priv->ysize = timing.vactive.typ;
  286. uc_priv->bpix = l2bpp;
  287. debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
  288. return 0;
  289. }
  290. void rk_vop_probe_regulators(struct udevice *dev,
  291. const char * const *names, int cnt)
  292. {
  293. int i, ret;
  294. const char *name;
  295. struct udevice *reg;
  296. for (i = 0; i < cnt; ++i) {
  297. name = names[i];
  298. debug("%s: probing regulator '%s'\n", dev->name, name);
  299. ret = regulator_autoset_by_name(name, &reg);
  300. if (!ret)
  301. ret = regulator_set_enable(reg, true);
  302. }
  303. }
  304. int rk_vop_probe(struct udevice *dev)
  305. {
  306. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  307. struct rk_vop_priv *priv = dev_get_priv(dev);
  308. int ret = 0;
  309. ofnode port, node;
  310. /* Before relocation we don't need to do anything */
  311. if (!(gd->flags & GD_FLG_RELOC))
  312. return 0;
  313. priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
  314. /*
  315. * Try all the ports until we find one that works. In practice this
  316. * tries EDP first if available, then HDMI.
  317. *
  318. * Note that rockchip_vop_set_clk() always uses NPLL as the source
  319. * clock so it is currently not possible to use more than one display
  320. * device simultaneously.
  321. */
  322. port = dev_read_subnode(dev, "port");
  323. if (!ofnode_valid(port)) {
  324. debug("%s(%s): 'port' subnode not found\n",
  325. __func__, dev_read_name(dev));
  326. return -EINVAL;
  327. }
  328. for (node = ofnode_first_subnode(port);
  329. ofnode_valid(node);
  330. node = dev_read_next_subnode(node)) {
  331. ret = rk_display_init(dev, plat->base, node);
  332. if (ret)
  333. debug("Device failed: ret=%d\n", ret);
  334. if (!ret)
  335. break;
  336. }
  337. video_set_flush_dcache(dev, 1);
  338. return ret;
  339. }
  340. int rk_vop_bind(struct udevice *dev)
  341. {
  342. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  343. plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
  344. CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
  345. return 0;
  346. }