rk_mipi.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
  4. * Author: Eric Gao <eric.gao@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <panel.h>
  12. #include <regmap.h>
  13. #include "rk_mipi.h"
  14. #include <syscon.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <dm/uclass-internal.h>
  18. #include <linux/kernel.h>
  19. #include <asm/arch-rockchip/clock.h>
  20. #include <asm/arch-rockchip/cru_rk3399.h>
  21. #include <asm/arch-rockchip/grf_rk3399.h>
  22. #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int rk_mipi_read_timing(struct udevice *dev,
  25. struct display_timing *timing)
  26. {
  27. int ret;
  28. ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
  29. 0, timing);
  30. if (ret) {
  31. debug("%s: Failed to decode display timing (ret=%d)\n",
  32. __func__, ret);
  33. return -EINVAL;
  34. }
  35. return 0;
  36. }
  37. /*
  38. * Register write function used only for mipi dsi controller.
  39. * Parameter:
  40. * @regs: mipi controller address
  41. * @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
  42. * use define in rk_mipi.h directly for this parameter
  43. * @val: value that will be write to specified bits of register
  44. */
  45. static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
  46. {
  47. u32 dat;
  48. u32 mask;
  49. u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
  50. u32 bits = (reg >> BITS_SHIFT) & 0xff;
  51. uintptr_t addr = (reg >> ADDR_SHIFT) + regs;
  52. /* Mask for specifiled bits,the corresponding bits will be clear */
  53. mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
  54. /* Make sure val in the available range */
  55. val &= ~(0xffffffff << bits);
  56. /* Get register's original val */
  57. dat = readl(addr);
  58. /* Clear specified bits */
  59. dat &= mask;
  60. /* Fill specified bits */
  61. dat |= val << offset;
  62. writel(dat, addr);
  63. }
  64. int rk_mipi_dsi_enable(struct udevice *dev,
  65. const struct display_timing *timing)
  66. {
  67. int node, timing_node;
  68. int val;
  69. struct rk_mipi_priv *priv = dev_get_priv(dev);
  70. uintptr_t regs = priv->regs;
  71. u32 txbyte_clk = priv->txbyte_clk;
  72. u32 txesc_clk = priv->txesc_clk;
  73. txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
  74. /* Set Display timing parameter */
  75. rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
  76. rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
  77. rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
  78. + timing->hback_porch.typ + timing->hactive.typ
  79. + timing->hfront_porch.typ));
  80. rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
  81. rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
  82. rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
  83. rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
  84. /* Set Signal Polarity */
  85. val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
  86. rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
  87. val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
  88. rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
  89. val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
  90. rk_mipi_dsi_write(regs, DATAEN_ACTIVE_LOW, val);
  91. val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
  92. rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
  93. /* Set video mode */
  94. rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
  95. /* Set video mode transmission type as burst mode */
  96. rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
  97. /* Set pix num in a video package */
  98. rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
  99. /* Set dpi color coding depth 24 bit */
  100. timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
  101. "display-timings");
  102. node = fdt_first_subnode(gd->fdt_blob, timing_node);
  103. val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
  104. switch (val) {
  105. case 16:
  106. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
  107. break;
  108. case 24:
  109. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
  110. break;
  111. case 30:
  112. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
  113. break;
  114. default:
  115. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
  116. }
  117. /* Enable low power mode */
  118. rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
  119. rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
  120. rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
  121. rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
  122. rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
  123. rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
  124. /* Division for timeout counter clk */
  125. rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
  126. /* Tx esc clk division from txbyte clk */
  127. rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
  128. /* Timeout count for hs<->lp transation between Line period */
  129. rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
  130. /* Phy State transfer timing */
  131. rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
  132. rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
  133. rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
  134. rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
  135. rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
  136. /* Power on */
  137. rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
  138. return 0;
  139. }
  140. /* rk mipi dphy write function. It is used to write test data to dphy */
  141. static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,
  142. unsigned char *test_data, unsigned char size)
  143. {
  144. int i = 0;
  145. /* Write Test code */
  146. rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
  147. rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
  148. rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
  149. rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
  150. rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
  151. /* Write Test data */
  152. for (i = 0; i < size; i++) {
  153. rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
  154. rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
  155. rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
  156. }
  157. }
  158. /*
  159. * Mipi dphy config function. Calculate the suitable prediv, feedback div,
  160. * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
  161. * and then enable phy.
  162. */
  163. int rk_mipi_phy_enable(struct udevice *dev)
  164. {
  165. int i;
  166. struct rk_mipi_priv *priv = dev_get_priv(dev);
  167. uintptr_t regs = priv->regs;
  168. u64 fbdiv;
  169. u64 prediv = 1;
  170. u32 max_fbdiv = 512;
  171. u32 max_prediv, min_prediv;
  172. u64 ddr_clk = priv->phy_clk;
  173. u32 refclk = priv->ref_clk;
  174. u32 remain = refclk;
  175. unsigned char test_data[2] = {0};
  176. int freq_rang[][2] = {
  177. {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
  178. {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
  179. {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
  180. {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
  181. {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
  182. {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
  183. {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
  184. {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
  185. {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
  186. {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
  187. };
  188. /* Shutdown mode */
  189. rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
  190. rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
  191. rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
  192. /* Pll locking */
  193. rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
  194. /* config cp and lfp */
  195. test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
  196. rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
  197. test_data[0] = 0x8;
  198. rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
  199. test_data[0] = 0x80 | 0x40;
  200. rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
  201. /* select the suitable value for fsfreqrang reg */
  202. for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
  203. if (ddr_clk / (MHz) <= freq_rang[i][0])
  204. break;
  205. }
  206. if (i == ARRAY_SIZE(freq_rang)) {
  207. debug("%s: Dphy freq out of range!\n", __func__);
  208. return -EINVAL;
  209. }
  210. test_data[0] = freq_rang[i][1] << 1;
  211. rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
  212. /*
  213. * Calculate the best ddrclk and it's corresponding div value. If the
  214. * given pixelclock is great than 250M, ddrclk will be fix 1500M.
  215. * Otherwise,
  216. * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
  217. * according to spec.
  218. */
  219. max_prediv = (refclk / (5 * MHz));
  220. min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
  221. debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
  222. min_prediv);
  223. if (max_prediv < min_prediv) {
  224. debug("%s: Invalid refclk value\n", __func__);
  225. return -EINVAL;
  226. }
  227. /* Calculate the best refclk and feedback division value for dphy pll */
  228. for (i = min_prediv; i < max_prediv; i++) {
  229. if ((ddr_clk * i % refclk < remain) &&
  230. (ddr_clk * i / refclk) < max_fbdiv) {
  231. prediv = i;
  232. remain = ddr_clk * i % refclk;
  233. }
  234. }
  235. fbdiv = ddr_clk * prediv / refclk;
  236. ddr_clk = refclk * fbdiv / prediv;
  237. priv->phy_clk = ddr_clk;
  238. debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
  239. __func__, refclk, prediv, fbdiv, ddr_clk);
  240. /* config prediv and feedback reg */
  241. test_data[0] = prediv - 1;
  242. rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
  243. test_data[0] = (fbdiv - 1) & 0x1f;
  244. rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
  245. test_data[0] = (fbdiv - 1) >> 5 | 0x80;
  246. rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
  247. test_data[0] = 0x30;
  248. rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
  249. /* rest config */
  250. test_data[0] = 0x4d;
  251. rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
  252. test_data[0] = 0x3d;
  253. rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
  254. test_data[0] = 0xdf;
  255. rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
  256. test_data[0] = 0x7;
  257. rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
  258. test_data[0] = 0x80 | 0x7;
  259. rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
  260. test_data[0] = 0x80 | 15;
  261. rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
  262. test_data, 1);
  263. test_data[0] = 0x80 | 85;
  264. rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
  265. test_data, 1);
  266. test_data[0] = 0x40 | 10;
  267. rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
  268. test_data, 1);
  269. /* enter into stop mode */
  270. rk_mipi_dsi_write(regs, N_LANES, 0x03);
  271. rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
  272. rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
  273. rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
  274. rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
  275. return 0;
  276. }