rk3399_mipi.c 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
  4. * Author: Eric Gao <eric.gao@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <panel.h>
  12. #include <regmap.h>
  13. #include "rk_mipi.h"
  14. #include <syscon.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <dm/uclass-internal.h>
  18. #include <linux/kernel.h>
  19. #include <asm/arch-rockchip/clock.h>
  20. #include <asm/arch-rockchip/cru_rk3399.h>
  21. #include <asm/arch-rockchip/grf_rk3399.h>
  22. #include <asm/arch-rockchip/hardware.h>
  23. #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
  24. /* Select mipi dsi source, big or little vop */
  25. static int rk_mipi_dsi_source_select(struct udevice *dev)
  26. {
  27. struct rk_mipi_priv *priv = dev_get_priv(dev);
  28. struct rk3399_grf_regs *grf = priv->grf;
  29. struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
  30. /* Select the video source */
  31. switch (disp_uc_plat->source_id) {
  32. case VOP_B:
  33. rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
  34. GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
  35. break;
  36. case VOP_L:
  37. rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
  38. GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
  39. break;
  40. default:
  41. debug("%s: Invalid VOP id\n", __func__);
  42. return -EINVAL;
  43. }
  44. return 0;
  45. }
  46. /* Setup mipi dphy working mode */
  47. static void rk_mipi_dphy_mode_set(struct udevice *dev)
  48. {
  49. struct rk_mipi_priv *priv = dev_get_priv(dev);
  50. struct rk3399_grf_regs *grf = priv->grf;
  51. int val;
  52. /* Set Controller as TX mode */
  53. val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
  54. rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
  55. /* Exit tx stop mode */
  56. val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
  57. rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
  58. /* Disable turnequest */
  59. val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
  60. rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
  61. }
  62. /*
  63. * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
  64. * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
  65. * enable backlight.
  66. */
  67. static int rk_display_enable(struct udevice *dev, int panel_bpp,
  68. const struct display_timing *timing)
  69. {
  70. int ret;
  71. struct rk_mipi_priv *priv = dev_get_priv(dev);
  72. /* Fill the mipi controller parameter */
  73. priv->ref_clk = 24 * MHz;
  74. priv->sys_clk = priv->ref_clk;
  75. priv->pix_clk = timing->pixelclock.typ;
  76. priv->phy_clk = priv->pix_clk * 6;
  77. priv->txbyte_clk = priv->phy_clk / 8;
  78. priv->txesc_clk = 20 * MHz;
  79. /* Select vop port, big or little */
  80. rk_mipi_dsi_source_select(dev);
  81. /* Set mipi dphy work mode */
  82. rk_mipi_dphy_mode_set(dev);
  83. /* Config and enable mipi dsi according to timing */
  84. ret = rk_mipi_dsi_enable(dev, timing);
  85. if (ret) {
  86. debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
  87. __func__, ret);
  88. return ret;
  89. }
  90. /* Config and enable mipi phy */
  91. ret = rk_mipi_phy_enable(dev);
  92. if (ret) {
  93. debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
  94. __func__, ret);
  95. return ret;
  96. }
  97. /* Enable backlight */
  98. ret = panel_enable_backlight(priv->panel);
  99. if (ret) {
  100. debug("%s: panel_enable_backlight() failed (err=%d)\n",
  101. __func__, ret);
  102. return ret;
  103. }
  104. return 0;
  105. }
  106. static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
  107. {
  108. struct rk_mipi_priv *priv = dev_get_priv(dev);
  109. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  110. if (IS_ERR_OR_NULL(priv->grf)) {
  111. debug("%s: Get syscon grf failed (ret=%p)\n",
  112. __func__, priv->grf);
  113. return -ENXIO;
  114. }
  115. priv->regs = dev_read_addr(dev);
  116. if (priv->regs == FDT_ADDR_T_NONE) {
  117. debug("%s: Get MIPI dsi address failed\n", __func__);
  118. return -ENXIO;
  119. }
  120. return 0;
  121. }
  122. /*
  123. * Probe function: check panel existence and readingit's timing. Then config
  124. * mipi dsi controller and enable it according to the timing parameter.
  125. */
  126. static int rk_mipi_probe(struct udevice *dev)
  127. {
  128. int ret;
  129. struct rk_mipi_priv *priv = dev_get_priv(dev);
  130. ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
  131. &priv->panel);
  132. if (ret) {
  133. debug("%s: Can not find panel (err=%d)\n", __func__, ret);
  134. return ret;
  135. }
  136. return 0;
  137. }
  138. static const struct dm_display_ops rk_mipi_dsi_ops = {
  139. .read_timing = rk_mipi_read_timing,
  140. .enable = rk_display_enable,
  141. };
  142. static const struct udevice_id rk_mipi_dsi_ids[] = {
  143. { .compatible = "rockchip,rk3399_mipi_dsi" },
  144. { }
  145. };
  146. U_BOOT_DRIVER(rk_mipi_dsi) = {
  147. .name = "rk_mipi_dsi",
  148. .id = UCLASS_DISPLAY,
  149. .of_match = rk_mipi_dsi_ids,
  150. .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
  151. .probe = rk_mipi_probe,
  152. .ops = &rk_mipi_dsi_ops,
  153. .priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
  154. };