rk3288_mipi.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
  4. * Author: Eric Gao <eric.gao@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <panel.h>
  12. #include <regmap.h>
  13. #include "rk_mipi.h"
  14. #include <syscon.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <dm/uclass-internal.h>
  18. #include <linux/kernel.h>
  19. #include <asm/arch-rockchip/clock.h>
  20. #include <asm/arch-rockchip/cru_rk3288.h>
  21. #include <asm/arch-rockchip/grf_rk3288.h>
  22. #include <asm/arch-rockchip/hardware.h>
  23. #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
  24. #define MHz 1000000
  25. /* Select mipi dsi source, big or little vop */
  26. static int rk_mipi_dsi_source_select(struct udevice *dev)
  27. {
  28. struct rk_mipi_priv *priv = dev_get_priv(dev);
  29. struct rk3288_grf *grf = priv->grf;
  30. struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
  31. /* Select the video source */
  32. switch (disp_uc_plat->source_id) {
  33. case VOP_B:
  34. rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
  35. RK3288_DSI0_LCDC_SEL_BIG
  36. << RK3288_DSI0_LCDC_SEL_SHIFT);
  37. break;
  38. case VOP_L:
  39. rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
  40. RK3288_DSI0_LCDC_SEL_LIT
  41. << RK3288_DSI0_LCDC_SEL_SHIFT);
  42. break;
  43. default:
  44. debug("%s: Invalid VOP id\n", __func__);
  45. return -EINVAL;
  46. }
  47. return 0;
  48. }
  49. /* Setup mipi dphy working mode */
  50. static void rk_mipi_dphy_mode_set(struct udevice *dev)
  51. {
  52. struct rk_mipi_priv *priv = dev_get_priv(dev);
  53. struct rk3288_grf *grf = priv->grf;
  54. int val;
  55. /* Set Controller as TX mode */
  56. val = RK3288_DPHY_TX0_RXMODE_DIS << RK3288_DPHY_TX0_RXMODE_SHIFT;
  57. rk_clrsetreg(&grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val);
  58. /* Exit tx stop mode */
  59. val |= RK3288_DPHY_TX0_TXSTOPMODE_EN
  60. << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT;
  61. rk_clrsetreg(&grf->soc_con8,
  62. RK3288_DPHY_TX0_TXSTOPMODE_MASK, val);
  63. /* Disable turnequest */
  64. val |= RK3288_DPHY_TX0_TURNREQUEST_EN
  65. << RK3288_DPHY_TX0_TURNREQUEST_SHIFT;
  66. rk_clrsetreg(&grf->soc_con8,
  67. RK3288_DPHY_TX0_TURNREQUEST_MASK, val);
  68. }
  69. /*
  70. * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
  71. * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
  72. * enable backlight.
  73. */
  74. static int rk_mipi_enable(struct udevice *dev, int panel_bpp,
  75. const struct display_timing *timing)
  76. {
  77. int ret;
  78. struct rk_mipi_priv *priv = dev_get_priv(dev);
  79. /* Fill the mipi controller parameter */
  80. priv->ref_clk = 24 * MHz;
  81. priv->sys_clk = priv->ref_clk;
  82. priv->pix_clk = timing->pixelclock.typ;
  83. priv->phy_clk = priv->pix_clk * 6;
  84. priv->txbyte_clk = priv->phy_clk / 8;
  85. priv->txesc_clk = 20 * MHz;
  86. /* Select vop port, big or little */
  87. rk_mipi_dsi_source_select(dev);
  88. /* Set mipi dphy work mode */
  89. rk_mipi_dphy_mode_set(dev);
  90. /* Config and enable mipi dsi according to timing */
  91. ret = rk_mipi_dsi_enable(dev, timing);
  92. if (ret) {
  93. debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
  94. __func__, ret);
  95. return ret;
  96. }
  97. /* Config and enable mipi phy */
  98. ret = rk_mipi_phy_enable(dev);
  99. if (ret) {
  100. debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
  101. __func__, ret);
  102. return ret;
  103. }
  104. /* Enable backlight */
  105. ret = panel_enable_backlight(priv->panel);
  106. if (ret) {
  107. debug("%s: panel_enable_backlight() failed (err=%d)\n",
  108. __func__, ret);
  109. return ret;
  110. }
  111. return 0;
  112. }
  113. static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
  114. {
  115. struct rk_mipi_priv *priv = dev_get_priv(dev);
  116. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  117. if (IS_ERR_OR_NULL(priv->grf)) {
  118. debug("%s: Get syscon grf failed (ret=%p)\n",
  119. __func__, priv->grf);
  120. return -ENXIO;
  121. }
  122. priv->regs = dev_read_addr(dev);
  123. if (priv->regs == FDT_ADDR_T_NONE) {
  124. debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__,
  125. priv->regs);
  126. return -ENXIO;
  127. }
  128. return 0;
  129. }
  130. /*
  131. * Probe function: check panel existence and readingit's timing. Then config
  132. * mipi dsi controller and enable it according to the timing parameter.
  133. */
  134. static int rk_mipi_probe(struct udevice *dev)
  135. {
  136. int ret;
  137. struct rk_mipi_priv *priv = dev_get_priv(dev);
  138. ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
  139. &priv->panel);
  140. if (ret) {
  141. debug("%s: Can not find panel (err=%d)\n", __func__, ret);
  142. return ret;
  143. }
  144. return 0;
  145. }
  146. static const struct dm_display_ops rk_mipi_dsi_ops = {
  147. .read_timing = rk_mipi_read_timing,
  148. .enable = rk_mipi_enable,
  149. };
  150. static const struct udevice_id rk_mipi_dsi_ids[] = {
  151. { .compatible = "rockchip,rk3288_mipi_dsi" },
  152. { }
  153. };
  154. U_BOOT_DRIVER(rk_mipi_dsi) = {
  155. .name = "rk_mipi_dsi",
  156. .id = UCLASS_DISPLAY,
  157. .of_match = rk_mipi_dsi_ids,
  158. .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
  159. .probe = rk_mipi_probe,
  160. .ops = &rk_mipi_dsi_ops,
  161. .priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
  162. };