rk_spi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * spi driver for rockchip
  4. *
  5. * (C) 2019 Theobroma Systems Design und Consulting GmbH
  6. *
  7. * (C) Copyright 2015 Google, Inc
  8. *
  9. * (C) Copyright 2008-2013 Rockchip Electronics
  10. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  11. */
  12. #include <common.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <dt-structs.h>
  16. #include <errno.h>
  17. #include <spi.h>
  18. #include <linux/errno.h>
  19. #include <asm/io.h>
  20. #include <asm/arch-rockchip/clock.h>
  21. #include <asm/arch-rockchip/periph.h>
  22. #include <dm/pinctrl.h>
  23. #include "rk_spi.h"
  24. /* Change to 1 to output registers at the start of each transaction */
  25. #define DEBUG_RK_SPI 0
  26. struct rockchip_spi_params {
  27. /* RXFIFO overruns and TXFIFO underruns stop the master clock */
  28. bool master_manages_fifo;
  29. };
  30. struct rockchip_spi_platdata {
  31. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  32. struct dtd_rockchip_rk3288_spi of_plat;
  33. #endif
  34. s32 frequency; /* Default clock frequency, -1 for none */
  35. fdt_addr_t base;
  36. uint deactivate_delay_us; /* Delay to wait after deactivate */
  37. uint activate_delay_us; /* Delay to wait after activate */
  38. };
  39. struct rockchip_spi_priv {
  40. struct rockchip_spi *regs;
  41. struct clk clk;
  42. unsigned int max_freq;
  43. unsigned int mode;
  44. ulong last_transaction_us; /* Time of last transaction end */
  45. unsigned int speed_hz;
  46. unsigned int last_speed_hz;
  47. uint input_rate;
  48. };
  49. #define SPI_FIFO_DEPTH 32
  50. static void rkspi_dump_regs(struct rockchip_spi *regs)
  51. {
  52. debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  53. debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  54. debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  55. debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  56. debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  57. debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  58. debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  59. debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  60. debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  61. debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  62. debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  63. debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  64. debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  65. debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  66. debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  67. }
  68. static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  69. {
  70. writel(enable ? 1 : 0, &regs->enr);
  71. }
  72. static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  73. {
  74. /*
  75. * We should try not to exceed the speed requested by the caller:
  76. * when selecting a divider, we need to make sure we round up.
  77. */
  78. uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
  79. /* The baudrate register (BAUDR) is defined as a 32bit register where
  80. * the upper 16bit are reserved and having 'Fsclk_out' in the lower
  81. * 16bits with 'Fsclk_out' defined as follows:
  82. *
  83. * Fsclk_out = Fspi_clk/ SCKDV
  84. * Where SCKDV is any even value between 2 and 65534.
  85. */
  86. if (clk_div > 0xfffe) {
  87. clk_div = 0xfffe;
  88. debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
  89. __func__, speed, priv->input_rate / clk_div);
  90. }
  91. /* Round up to the next even 16bit number */
  92. clk_div = (clk_div + 1) & 0xfffe;
  93. debug("spi speed %u, div %u\n", speed, clk_div);
  94. clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
  95. priv->last_speed_hz = speed;
  96. }
  97. static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
  98. {
  99. unsigned long start;
  100. start = get_timer(0);
  101. while (readl(&regs->sr) & SR_BUSY) {
  102. if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
  103. debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
  104. return -ETIMEDOUT;
  105. }
  106. }
  107. return 0;
  108. }
  109. static void spi_cs_activate(struct udevice *dev, uint cs)
  110. {
  111. struct udevice *bus = dev->parent;
  112. struct rockchip_spi_platdata *plat = bus->platdata;
  113. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  114. struct rockchip_spi *regs = priv->regs;
  115. /* If it's too soon to do another transaction, wait */
  116. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  117. ulong delay_us; /* The delay completed so far */
  118. delay_us = timer_get_us() - priv->last_transaction_us;
  119. if (delay_us < plat->deactivate_delay_us) {
  120. ulong additional_delay_us =
  121. plat->deactivate_delay_us - delay_us;
  122. debug("%s: delaying by %ld us\n",
  123. __func__, additional_delay_us);
  124. udelay(additional_delay_us);
  125. }
  126. }
  127. debug("activate cs%u\n", cs);
  128. writel(1 << cs, &regs->ser);
  129. if (plat->activate_delay_us)
  130. udelay(plat->activate_delay_us);
  131. }
  132. static void spi_cs_deactivate(struct udevice *dev, uint cs)
  133. {
  134. struct udevice *bus = dev->parent;
  135. struct rockchip_spi_platdata *plat = bus->platdata;
  136. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  137. struct rockchip_spi *regs = priv->regs;
  138. debug("deactivate cs%u\n", cs);
  139. writel(0, &regs->ser);
  140. /* Remember time of this transaction so we can honour the bus delay */
  141. if (plat->deactivate_delay_us)
  142. priv->last_transaction_us = timer_get_us();
  143. }
  144. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  145. static int conv_of_platdata(struct udevice *dev)
  146. {
  147. struct rockchip_spi_platdata *plat = dev->platdata;
  148. struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
  149. struct rockchip_spi_priv *priv = dev_get_priv(dev);
  150. int ret;
  151. plat->base = dtplat->reg[0];
  152. plat->frequency = 20000000;
  153. ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
  154. if (ret < 0)
  155. return ret;
  156. dev->req_seq = 0;
  157. return 0;
  158. }
  159. #endif
  160. static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
  161. {
  162. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  163. struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
  164. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  165. int ret;
  166. plat->base = dev_read_addr(bus);
  167. ret = clk_get_by_index(bus, 0, &priv->clk);
  168. if (ret < 0) {
  169. debug("%s: Could not get clock for %s: %d\n", __func__,
  170. bus->name, ret);
  171. return ret;
  172. }
  173. plat->frequency =
  174. dev_read_u32_default(bus, "spi-max-frequency", 50000000);
  175. plat->deactivate_delay_us =
  176. dev_read_u32_default(bus, "spi-deactivate-delay", 0);
  177. plat->activate_delay_us =
  178. dev_read_u32_default(bus, "spi-activate-delay", 0);
  179. debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
  180. __func__, (uint)plat->base, plat->frequency,
  181. plat->deactivate_delay_us);
  182. #endif
  183. return 0;
  184. }
  185. static int rockchip_spi_calc_modclk(ulong max_freq)
  186. {
  187. /*
  188. * While this is not strictly correct for the RK3368, as the
  189. * GPLL will be 576MHz, things will still work, as the
  190. * clk_set_rate(...) implementation in our clock-driver will
  191. * chose the next closest rate not exceeding what we request
  192. * based on the output of this function.
  193. */
  194. unsigned div;
  195. const unsigned long gpll_hz = 594000000UL;
  196. /*
  197. * We need to find an input clock that provides at least twice
  198. * the maximum frequency and can be generated from the assumed
  199. * speed of GPLL (594MHz) using an integer divider.
  200. *
  201. * To give us more achievable bitrates at higher speeds (these
  202. * are generated by dividing by an even 16-bit integer from
  203. * this frequency), we try to have an input frequency of at
  204. * least 4x our max_freq.
  205. */
  206. div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
  207. return gpll_hz / div;
  208. }
  209. static int rockchip_spi_probe(struct udevice *bus)
  210. {
  211. struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
  212. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  213. int ret;
  214. debug("%s: probe\n", __func__);
  215. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  216. ret = conv_of_platdata(bus);
  217. if (ret)
  218. return ret;
  219. #endif
  220. priv->regs = (struct rockchip_spi *)plat->base;
  221. priv->last_transaction_us = timer_get_us();
  222. priv->max_freq = plat->frequency;
  223. /* Clamp the value from the DTS against any hardware limits */
  224. if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
  225. priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
  226. /* Find a module-input clock that fits with the max_freq setting */
  227. ret = clk_set_rate(&priv->clk,
  228. rockchip_spi_calc_modclk(priv->max_freq));
  229. if (ret < 0) {
  230. debug("%s: Failed to set clock: %d\n", __func__, ret);
  231. return ret;
  232. }
  233. priv->input_rate = ret;
  234. debug("%s: rate = %u\n", __func__, priv->input_rate);
  235. return 0;
  236. }
  237. static int rockchip_spi_claim_bus(struct udevice *dev)
  238. {
  239. struct udevice *bus = dev->parent;
  240. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  241. struct rockchip_spi *regs = priv->regs;
  242. uint ctrlr0;
  243. /* Disable the SPI hardware */
  244. rkspi_enable_chip(regs, false);
  245. if (priv->speed_hz != priv->last_speed_hz)
  246. rkspi_set_clk(priv, priv->speed_hz);
  247. /* Operation Mode */
  248. ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
  249. /* Data Frame Size */
  250. ctrlr0 |= DFS_8BIT << DFS_SHIFT;
  251. /* set SPI mode 0..3 */
  252. if (priv->mode & SPI_CPOL)
  253. ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
  254. if (priv->mode & SPI_CPHA)
  255. ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
  256. /* Chip Select Mode */
  257. ctrlr0 |= CSM_KEEP << CSM_SHIFT;
  258. /* SSN to Sclk_out delay */
  259. ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
  260. /* Serial Endian Mode */
  261. ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
  262. /* First Bit Mode */
  263. ctrlr0 |= FBM_MSB << FBM_SHIFT;
  264. /* Byte and Halfword Transform */
  265. ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
  266. /* Rxd Sample Delay */
  267. ctrlr0 |= 0 << RXDSD_SHIFT;
  268. /* Frame Format */
  269. ctrlr0 |= FRF_SPI << FRF_SHIFT;
  270. /* Tx and Rx mode */
  271. ctrlr0 |= TMOD_TR << TMOD_SHIFT;
  272. writel(ctrlr0, &regs->ctrlr0);
  273. return 0;
  274. }
  275. static int rockchip_spi_release_bus(struct udevice *dev)
  276. {
  277. struct udevice *bus = dev->parent;
  278. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  279. rkspi_enable_chip(priv->regs, false);
  280. return 0;
  281. }
  282. static inline int rockchip_spi_16bit_reader(struct udevice *dev,
  283. u8 **din, int *len)
  284. {
  285. struct udevice *bus = dev->parent;
  286. const struct rockchip_spi_params * const data =
  287. (void *)dev_get_driver_data(bus);
  288. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  289. struct rockchip_spi *regs = priv->regs;
  290. const u32 saved_ctrlr0 = readl(&regs->ctrlr0);
  291. #if defined(DEBUG)
  292. u32 statistics_rxlevels[33] = { };
  293. #endif
  294. u32 frames = *len / 2;
  295. u8 *in = (u8 *)(*din);
  296. u32 max_chunk_size = SPI_FIFO_DEPTH;
  297. if (!frames)
  298. return 0;
  299. /*
  300. * If we know that the hardware will manage RXFIFO overruns
  301. * (i.e. stop the SPI clock until there's space in the FIFO),
  302. * we the allow largest possible chunk size that can be
  303. * represented in CTRLR1.
  304. */
  305. if (data && data->master_manages_fifo)
  306. max_chunk_size = 0x10000;
  307. // rockchip_spi_configure(dev, mode, size)
  308. rkspi_enable_chip(regs, false);
  309. clrsetbits_le32(&regs->ctrlr0,
  310. TMOD_MASK << TMOD_SHIFT,
  311. TMOD_RO << TMOD_SHIFT);
  312. /* 16bit data frame size */
  313. clrsetbits_le32(&regs->ctrlr0, DFS_MASK, DFS_16BIT);
  314. /* Update caller's context */
  315. const u32 bytes_to_process = 2 * frames;
  316. *din += bytes_to_process;
  317. *len -= bytes_to_process;
  318. /* Process our frames */
  319. while (frames) {
  320. u32 chunk_size = min(frames, max_chunk_size);
  321. frames -= chunk_size;
  322. writew(chunk_size - 1, &regs->ctrlr1);
  323. rkspi_enable_chip(regs, true);
  324. do {
  325. u32 rx_level = readw(&regs->rxflr);
  326. #if defined(DEBUG)
  327. statistics_rxlevels[rx_level]++;
  328. #endif
  329. chunk_size -= rx_level;
  330. while (rx_level--) {
  331. u16 val = readw(regs->rxdr);
  332. *in++ = val & 0xff;
  333. *in++ = val >> 8;
  334. }
  335. } while (chunk_size);
  336. rkspi_enable_chip(regs, false);
  337. }
  338. #if defined(DEBUG)
  339. debug("%s: observed rx_level during processing:\n", __func__);
  340. for (int i = 0; i <= 32; ++i)
  341. if (statistics_rxlevels[i])
  342. debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
  343. #endif
  344. /* Restore the original transfer setup and return error-free. */
  345. writel(saved_ctrlr0, &regs->ctrlr0);
  346. return 0;
  347. }
  348. static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
  349. const void *dout, void *din, unsigned long flags)
  350. {
  351. struct udevice *bus = dev->parent;
  352. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  353. struct rockchip_spi *regs = priv->regs;
  354. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  355. int len = bitlen >> 3;
  356. const u8 *out = dout;
  357. u8 *in = din;
  358. int toread, towrite;
  359. int ret = 0;
  360. debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
  361. len, flags);
  362. if (DEBUG_RK_SPI)
  363. rkspi_dump_regs(regs);
  364. /* Assert CS before transfer */
  365. if (flags & SPI_XFER_BEGIN)
  366. spi_cs_activate(dev, slave_plat->cs);
  367. /*
  368. * To ensure fast loading of firmware images (e.g. full U-Boot
  369. * stage, ATF, Linux kernel) from SPI flash, we optimise the
  370. * case of read-only transfers by using the full 16bits of each
  371. * FIFO element.
  372. */
  373. if (!out)
  374. ret = rockchip_spi_16bit_reader(dev, &in, &len);
  375. /* This is the original 8bit reader/writer code */
  376. while (len > 0) {
  377. int todo = min(len, 0x10000);
  378. rkspi_enable_chip(regs, false);
  379. writel(todo - 1, &regs->ctrlr1);
  380. rkspi_enable_chip(regs, true);
  381. toread = todo;
  382. towrite = todo;
  383. while (toread || towrite) {
  384. u32 status = readl(&regs->sr);
  385. if (towrite && !(status & SR_TF_FULL)) {
  386. writel(out ? *out++ : 0, regs->txdr);
  387. towrite--;
  388. }
  389. if (toread && !(status & SR_RF_EMPT)) {
  390. u32 byte = readl(regs->rxdr);
  391. if (in)
  392. *in++ = byte;
  393. toread--;
  394. }
  395. }
  396. /*
  397. * In case that there's a transmit-component, we need to wait
  398. * until the control goes idle before we can disable the SPI
  399. * control logic (as this will implictly flush the FIFOs).
  400. */
  401. if (out) {
  402. ret = rkspi_wait_till_not_busy(regs);
  403. if (ret)
  404. break;
  405. }
  406. len -= todo;
  407. }
  408. /* Deassert CS after transfer */
  409. if (flags & SPI_XFER_END)
  410. spi_cs_deactivate(dev, slave_plat->cs);
  411. rkspi_enable_chip(regs, false);
  412. return ret;
  413. }
  414. static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
  415. {
  416. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  417. /* Clamp to the maximum frequency specified in the DTS */
  418. if (speed > priv->max_freq)
  419. speed = priv->max_freq;
  420. priv->speed_hz = speed;
  421. return 0;
  422. }
  423. static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
  424. {
  425. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  426. priv->mode = mode;
  427. return 0;
  428. }
  429. static const struct dm_spi_ops rockchip_spi_ops = {
  430. .claim_bus = rockchip_spi_claim_bus,
  431. .release_bus = rockchip_spi_release_bus,
  432. .xfer = rockchip_spi_xfer,
  433. .set_speed = rockchip_spi_set_speed,
  434. .set_mode = rockchip_spi_set_mode,
  435. /*
  436. * cs_info is not needed, since we require all chip selects to be
  437. * in the device tree explicitly
  438. */
  439. };
  440. const struct rockchip_spi_params rk3399_spi_params = {
  441. .master_manages_fifo = true,
  442. };
  443. static const struct udevice_id rockchip_spi_ids[] = {
  444. { .compatible = "rockchip,rk3288-spi" },
  445. { .compatible = "rockchip,rk3368-spi",
  446. .data = (ulong)&rk3399_spi_params },
  447. { .compatible = "rockchip,rk3399-spi",
  448. .data = (ulong)&rk3399_spi_params },
  449. { }
  450. };
  451. U_BOOT_DRIVER(rockchip_spi) = {
  452. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  453. .name = "rockchip_rk3288_spi",
  454. #else
  455. .name = "rockchip_spi",
  456. #endif
  457. .id = UCLASS_SPI,
  458. .of_match = rockchip_spi_ids,
  459. .ops = &rockchip_spi_ops,
  460. .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
  461. .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
  462. .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
  463. .probe = rockchip_spi_probe,
  464. };