sdram_rk3288.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. * Copyright 2014 Rockchip Inc.
  5. *
  6. * Adapted from coreboot.
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <dt-structs.h>
  12. #include <errno.h>
  13. #include <ram.h>
  14. #include <regmap.h>
  15. #include <syscon.h>
  16. #include <asm/io.h>
  17. #include <asm/arch-rockchip/clock.h>
  18. #include <asm/arch-rockchip/cru_rk3288.h>
  19. #include <asm/arch-rockchip/ddr_rk3288.h>
  20. #include <asm/arch-rockchip/grf_rk3288.h>
  21. #include <asm/arch-rockchip/pmu_rk3288.h>
  22. #include <asm/arch-rockchip/sdram.h>
  23. #include <asm/arch-rockchip/sdram_common.h>
  24. #include <linux/err.h>
  25. #include <power/regulator.h>
  26. #include <power/rk8xx_pmic.h>
  27. struct chan_info {
  28. struct rk3288_ddr_pctl *pctl;
  29. struct rk3288_ddr_publ *publ;
  30. struct rk3288_msch *msch;
  31. };
  32. struct dram_info {
  33. struct chan_info chan[2];
  34. struct ram_info info;
  35. struct clk ddr_clk;
  36. struct rk3288_cru *cru;
  37. struct rk3288_grf *grf;
  38. struct rk3288_sgrf *sgrf;
  39. struct rk3288_pmu *pmu;
  40. bool is_veyron;
  41. };
  42. struct rk3288_sdram_params {
  43. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  44. struct dtd_rockchip_rk3288_dmc of_plat;
  45. #endif
  46. struct rk3288_sdram_channel ch[2];
  47. struct rk3288_sdram_pctl_timing pctl_timing;
  48. struct rk3288_sdram_phy_timing phy_timing;
  49. struct rk3288_base_params base;
  50. int num_channels;
  51. struct regmap *map;
  52. };
  53. const int ddrconf_table[] = {
  54. /* row col,bw */
  55. 0,
  56. ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  57. ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  58. ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  59. ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  60. ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  61. ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  62. ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  63. ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  64. ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  65. ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  66. 0,
  67. 0,
  68. 0,
  69. 0,
  70. ((4 << 4) | 2),
  71. };
  72. #define TEST_PATTEN 0x5aa5f00f
  73. #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
  74. #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
  75. #ifdef CONFIG_SPL_BUILD
  76. static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  77. {
  78. int i;
  79. for (i = 0; i < n / sizeof(u32); i++) {
  80. writel(*src, dest);
  81. src++;
  82. dest++;
  83. }
  84. }
  85. static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
  86. {
  87. u32 phy_ctl_srstn_shift = 4 + 5 * ch;
  88. u32 ctl_psrstn_shift = 3 + 5 * ch;
  89. u32 ctl_srstn_shift = 2 + 5 * ch;
  90. u32 phy_psrstn_shift = 1 + 5 * ch;
  91. u32 phy_srstn_shift = 5 * ch;
  92. rk_clrsetreg(&cru->cru_softrst_con[10],
  93. 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
  94. 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
  95. 1 << phy_srstn_shift,
  96. phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
  97. ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
  98. phy << phy_srstn_shift);
  99. }
  100. static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
  101. {
  102. u32 phy_ctl_srstn_shift = 4 + 5 * ch;
  103. rk_clrsetreg(&cru->cru_softrst_con[10],
  104. 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
  105. }
  106. static void phy_pctrl_reset(struct rk3288_cru *cru,
  107. struct rk3288_ddr_publ *publ,
  108. int channel)
  109. {
  110. int i;
  111. ddr_reset(cru, channel, 1, 1);
  112. udelay(1);
  113. clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
  114. for (i = 0; i < 4; i++)
  115. clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
  116. udelay(10);
  117. setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
  118. for (i = 0; i < 4; i++)
  119. setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
  120. udelay(10);
  121. ddr_reset(cru, channel, 1, 0);
  122. udelay(10);
  123. ddr_reset(cru, channel, 0, 0);
  124. udelay(10);
  125. }
  126. static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
  127. u32 freq)
  128. {
  129. int i;
  130. if (freq <= 250000000) {
  131. if (freq <= 150000000)
  132. clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
  133. else
  134. setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
  135. setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
  136. for (i = 0; i < 4; i++)
  137. setbits_le32(&publ->datx8[i].dxdllcr,
  138. DXDLLCR_DLLDIS);
  139. setbits_le32(&publ->pir, PIR_DLLBYP);
  140. } else {
  141. clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
  142. clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
  143. for (i = 0; i < 4; i++) {
  144. clrbits_le32(&publ->datx8[i].dxdllcr,
  145. DXDLLCR_DLLDIS);
  146. }
  147. clrbits_le32(&publ->pir, PIR_DLLBYP);
  148. }
  149. }
  150. static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
  151. {
  152. writel(DFI_INIT_START, &pctl->dfistcfg0);
  153. writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
  154. &pctl->dfistcfg1);
  155. writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
  156. writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
  157. &pctl->dfilpcfg0);
  158. writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
  159. writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
  160. writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
  161. writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
  162. writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
  163. writel(1, &pctl->dfitphyupdtype0);
  164. /* cs0 and cs1 write odt enable */
  165. writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
  166. &pctl->dfiodtcfg);
  167. /* odt write length */
  168. writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
  169. /* phyupd and ctrlupd disabled */
  170. writel(0, &pctl->dfiupdcfg);
  171. }
  172. static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable)
  173. {
  174. uint val = 0;
  175. if (enable) {
  176. val = 1 << (channel ? DDR1_16BIT_EN_SHIFT :
  177. DDR0_16BIT_EN_SHIFT);
  178. }
  179. rk_clrsetreg(&grf->soc_con0,
  180. 1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT),
  181. val);
  182. }
  183. static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel,
  184. bool ddr3_mode)
  185. {
  186. uint mask, val;
  187. mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT);
  188. val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT :
  189. MSCH0_MAINDDR3_SHIFT);
  190. rk_clrsetreg(&grf->soc_con0, mask, val);
  191. }
  192. static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel,
  193. bool enable, bool enable_bst, bool enable_odt)
  194. {
  195. uint mask;
  196. bool disable_bst = !enable_bst;
  197. mask = channel ?
  198. (1 << LPDDR3_EN1_SHIFT | 1 << UPCTL1_BST_DIABLE_SHIFT |
  199. 1 << UPCTL1_LPDDR3_ODT_EN_SHIFT) :
  200. (1 << LPDDR3_EN0_SHIFT | 1 << UPCTL0_BST_DIABLE_SHIFT |
  201. 1 << UPCTL0_LPDDR3_ODT_EN_SHIFT);
  202. rk_clrsetreg(&grf->soc_con2, mask,
  203. enable << (channel ? LPDDR3_EN1_SHIFT : LPDDR3_EN0_SHIFT) |
  204. disable_bst << (channel ? UPCTL1_BST_DIABLE_SHIFT :
  205. UPCTL0_BST_DIABLE_SHIFT) |
  206. enable_odt << (channel ? UPCTL1_LPDDR3_ODT_EN_SHIFT :
  207. UPCTL0_LPDDR3_ODT_EN_SHIFT));
  208. }
  209. static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
  210. struct rk3288_sdram_params *sdram_params,
  211. struct rk3288_grf *grf)
  212. {
  213. unsigned int burstlen;
  214. burstlen = (sdram_params->base.noc_timing >> 18) & 0x7;
  215. copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
  216. sizeof(sdram_params->pctl_timing));
  217. switch (sdram_params->base.dramtype) {
  218. case LPDDR3:
  219. writel(sdram_params->pctl_timing.tcl - 1,
  220. &pctl->dfitrddataen);
  221. writel(sdram_params->pctl_timing.tcwl,
  222. &pctl->dfitphywrlat);
  223. burstlen >>= 1;
  224. writel(LPDDR2_S4 | 0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
  225. LPDDR2_EN | burstlen << BURSTLENGTH_SHIFT |
  226. (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
  227. 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
  228. &pctl->mcfg);
  229. ddr_set_ddr3_mode(grf, channel, false);
  230. ddr_set_enable(grf, channel, true);
  231. ddr_set_en_bst_odt(grf, channel, true, false,
  232. sdram_params->base.odt);
  233. break;
  234. case DDR3:
  235. if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
  236. writel(sdram_params->pctl_timing.tcl - 3,
  237. &pctl->dfitrddataen);
  238. } else {
  239. writel(sdram_params->pctl_timing.tcl - 2,
  240. &pctl->dfitrddataen);
  241. }
  242. writel(sdram_params->pctl_timing.tcwl - 1,
  243. &pctl->dfitphywrlat);
  244. writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
  245. DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
  246. 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
  247. &pctl->mcfg);
  248. ddr_set_ddr3_mode(grf, channel, true);
  249. ddr_set_enable(grf, channel, true);
  250. ddr_set_en_bst_odt(grf, channel, false, true, false);
  251. break;
  252. }
  253. setbits_le32(&pctl->scfg, 1);
  254. }
  255. static void phy_cfg(const struct chan_info *chan, int channel,
  256. struct rk3288_sdram_params *sdram_params)
  257. {
  258. struct rk3288_ddr_publ *publ = chan->publ;
  259. struct rk3288_msch *msch = chan->msch;
  260. uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
  261. u32 dinit2, tmp;
  262. int i;
  263. dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
  264. /* DDR PHY Timing */
  265. copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
  266. sizeof(sdram_params->phy_timing));
  267. writel(sdram_params->base.noc_timing, &msch->ddrtiming);
  268. writel(0x3f, &msch->readlatency);
  269. writel(sdram_params->base.noc_activate, &msch->activate);
  270. writel(2 << BUSWRTORD_SHIFT | 2 << BUSRDTOWR_SHIFT |
  271. 1 << BUSRDTORD_SHIFT, &msch->devtodev);
  272. writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
  273. DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
  274. 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
  275. writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
  276. DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
  277. &publ->ptr[1]);
  278. writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
  279. DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
  280. &publ->ptr[2]);
  281. switch (sdram_params->base.dramtype) {
  282. case LPDDR3:
  283. clrsetbits_le32(&publ->pgcr, 0x1F,
  284. 0 << PGCR_DFTLMT_SHIFT |
  285. 0 << PGCR_DFTCMP_SHIFT |
  286. 1 << PGCR_DQSCFG_SHIFT |
  287. 0 << PGCR_ITMDMD_SHIFT);
  288. /* DDRMODE select LPDDR3 */
  289. clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
  290. DDRMD_LPDDR2_LPDDR3 << DDRMD_SHIFT);
  291. clrsetbits_le32(&publ->dxccr,
  292. DQSNRES_MASK << DQSNRES_SHIFT |
  293. DQSRES_MASK << DQSRES_SHIFT,
  294. 4 << DQSRES_SHIFT | 0xc << DQSNRES_SHIFT);
  295. tmp = readl(&publ->dtpr[1]);
  296. tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) -
  297. ((tmp >> TDQSCK_SHIFT) & TDQSCK_MASK);
  298. clrsetbits_le32(&publ->dsgcr,
  299. DQSGE_MASK << DQSGE_SHIFT |
  300. DQSGX_MASK << DQSGX_SHIFT,
  301. tmp << DQSGE_SHIFT | tmp << DQSGX_SHIFT);
  302. break;
  303. case DDR3:
  304. clrbits_le32(&publ->pgcr, 0x1f);
  305. clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
  306. DDRMD_DDR3 << DDRMD_SHIFT);
  307. break;
  308. }
  309. if (sdram_params->base.odt) {
  310. /*dynamic RTT enable */
  311. for (i = 0; i < 4; i++)
  312. setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
  313. } else {
  314. /*dynamic RTT disable */
  315. for (i = 0; i < 4; i++)
  316. clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
  317. }
  318. }
  319. static void phy_init(struct rk3288_ddr_publ *publ)
  320. {
  321. setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
  322. | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
  323. udelay(1);
  324. while ((readl(&publ->pgsr) &
  325. (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
  326. (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
  327. ;
  328. }
  329. static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
  330. u32 cmd, u32 arg)
  331. {
  332. writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
  333. udelay(1);
  334. while (readl(&pctl->mcmd) & START_CMD)
  335. ;
  336. }
  337. static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
  338. u32 rank, u32 cmd, u32 ma, u32 op)
  339. {
  340. send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
  341. (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
  342. }
  343. static void memory_init(struct rk3288_ddr_publ *publ,
  344. u32 dramtype)
  345. {
  346. setbits_le32(&publ->pir,
  347. (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
  348. | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
  349. | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
  350. udelay(1);
  351. while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
  352. != (PGSR_IDONE | PGSR_DLDONE))
  353. ;
  354. }
  355. static void move_to_config_state(struct rk3288_ddr_publ *publ,
  356. struct rk3288_ddr_pctl *pctl)
  357. {
  358. unsigned int state;
  359. while (1) {
  360. state = readl(&pctl->stat) & PCTL_STAT_MSK;
  361. switch (state) {
  362. case LOW_POWER:
  363. writel(WAKEUP_STATE, &pctl->sctl);
  364. while ((readl(&pctl->stat) & PCTL_STAT_MSK)
  365. != ACCESS)
  366. ;
  367. /* wait DLL lock */
  368. while ((readl(&publ->pgsr) & PGSR_DLDONE)
  369. != PGSR_DLDONE)
  370. ;
  371. /*
  372. * if at low power state,need wakeup first,
  373. * and then enter the config
  374. * so here no break.
  375. */
  376. case ACCESS:
  377. /* no break */
  378. case INIT_MEM:
  379. writel(CFG_STATE, &pctl->sctl);
  380. while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
  381. ;
  382. break;
  383. case CONFIG:
  384. return;
  385. default:
  386. break;
  387. }
  388. }
  389. }
  390. static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
  391. u32 n, struct rk3288_grf *grf)
  392. {
  393. struct rk3288_ddr_pctl *pctl = chan->pctl;
  394. struct rk3288_ddr_publ *publ = chan->publ;
  395. struct rk3288_msch *msch = chan->msch;
  396. if (n == 1) {
  397. setbits_le32(&pctl->ppcfg, 1);
  398. rk_setreg(&grf->soc_con0, 1 << (8 + channel));
  399. setbits_le32(&msch->ddrtiming, 1 << 31);
  400. /* Data Byte disable*/
  401. clrbits_le32(&publ->datx8[2].dxgcr, 1);
  402. clrbits_le32(&publ->datx8[3].dxgcr, 1);
  403. /* disable DLL */
  404. setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
  405. setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
  406. } else {
  407. clrbits_le32(&pctl->ppcfg, 1);
  408. rk_clrreg(&grf->soc_con0, 1 << (8 + channel));
  409. clrbits_le32(&msch->ddrtiming, 1 << 31);
  410. /* Data Byte enable*/
  411. setbits_le32(&publ->datx8[2].dxgcr, 1);
  412. setbits_le32(&publ->datx8[3].dxgcr, 1);
  413. /* enable DLL */
  414. clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
  415. clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
  416. /* reset DLL */
  417. clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
  418. clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
  419. udelay(10);
  420. setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
  421. setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
  422. }
  423. setbits_le32(&pctl->dfistcfg0, 1 << 2);
  424. }
  425. static int data_training(const struct chan_info *chan, int channel,
  426. struct rk3288_sdram_params *sdram_params)
  427. {
  428. unsigned int j;
  429. int ret = 0;
  430. u32 rank;
  431. int i;
  432. u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
  433. struct rk3288_ddr_publ *publ = chan->publ;
  434. struct rk3288_ddr_pctl *pctl = chan->pctl;
  435. /* disable auto refresh */
  436. writel(0, &pctl->trefi);
  437. if (sdram_params->base.dramtype != LPDDR3)
  438. setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
  439. rank = sdram_params->ch[channel].rank | 1;
  440. for (j = 0; j < ARRAY_SIZE(step); j++) {
  441. /*
  442. * trigger QSTRN and RVTRN
  443. * clear DTDONE status
  444. */
  445. setbits_le32(&publ->pir, PIR_CLRSR);
  446. /* trigger DTT */
  447. setbits_le32(&publ->pir,
  448. PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
  449. PIR_CLRSR);
  450. udelay(1);
  451. /* wait echo byte DTDONE */
  452. while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
  453. != rank)
  454. ;
  455. while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
  456. != rank)
  457. ;
  458. if (!(readl(&pctl->ppcfg) & 1)) {
  459. while ((readl(&publ->datx8[2].dxgsr[0])
  460. & rank) != rank)
  461. ;
  462. while ((readl(&publ->datx8[3].dxgsr[0])
  463. & rank) != rank)
  464. ;
  465. }
  466. if (readl(&publ->pgsr) &
  467. (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
  468. ret = -1;
  469. break;
  470. }
  471. }
  472. /* send some auto refresh to complement the lost while DTT */
  473. for (i = 0; i < (rank > 1 ? 8 : 4); i++)
  474. send_command(pctl, rank, REF_CMD, 0);
  475. if (sdram_params->base.dramtype != LPDDR3)
  476. clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
  477. /* resume auto refresh */
  478. writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
  479. return ret;
  480. }
  481. static void move_to_access_state(const struct chan_info *chan)
  482. {
  483. struct rk3288_ddr_publ *publ = chan->publ;
  484. struct rk3288_ddr_pctl *pctl = chan->pctl;
  485. unsigned int state;
  486. while (1) {
  487. state = readl(&pctl->stat) & PCTL_STAT_MSK;
  488. switch (state) {
  489. case LOW_POWER:
  490. if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
  491. LP_TRIG_MASK) == 1)
  492. return;
  493. writel(WAKEUP_STATE, &pctl->sctl);
  494. while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
  495. ;
  496. /* wait DLL lock */
  497. while ((readl(&publ->pgsr) & PGSR_DLDONE)
  498. != PGSR_DLDONE)
  499. ;
  500. break;
  501. case INIT_MEM:
  502. writel(CFG_STATE, &pctl->sctl);
  503. while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
  504. ;
  505. case CONFIG:
  506. writel(GO_STATE, &pctl->sctl);
  507. while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
  508. ;
  509. break;
  510. case ACCESS:
  511. return;
  512. default:
  513. break;
  514. }
  515. }
  516. }
  517. static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
  518. struct rk3288_sdram_params *sdram_params)
  519. {
  520. struct rk3288_ddr_publ *publ = chan->publ;
  521. if (sdram_params->ch[chnum].bk == 3)
  522. clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
  523. 1 << PDQ_SHIFT);
  524. else
  525. clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
  526. writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
  527. }
  528. static void dram_all_config(const struct dram_info *dram,
  529. struct rk3288_sdram_params *sdram_params)
  530. {
  531. unsigned int chan;
  532. u32 sys_reg = 0;
  533. sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
  534. sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
  535. for (chan = 0; chan < sdram_params->num_channels; chan++) {
  536. const struct rk3288_sdram_channel *info =
  537. &sdram_params->ch[chan];
  538. sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
  539. sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
  540. sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
  541. sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
  542. sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
  543. sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
  544. sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
  545. sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
  546. sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
  547. dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
  548. }
  549. writel(sys_reg, &dram->pmu->sys_reg[2]);
  550. rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
  551. }
  552. static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
  553. struct rk3288_sdram_params *sdram_params)
  554. {
  555. int reg;
  556. int need_trainig = 0;
  557. const struct chan_info *chan = &dram->chan[channel];
  558. struct rk3288_ddr_publ *publ = chan->publ;
  559. if (data_training(chan, channel, sdram_params) < 0) {
  560. reg = readl(&publ->datx8[0].dxgsr[0]);
  561. /* Check the result for rank 0 */
  562. if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
  563. debug("data training fail!\n");
  564. return -EIO;
  565. } else if ((channel == 1) &&
  566. (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
  567. sdram_params->num_channels = 1;
  568. }
  569. /* Check the result for rank 1 */
  570. if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
  571. sdram_params->ch[channel].rank = 1;
  572. clrsetbits_le32(&publ->pgcr, 0xF << 18,
  573. sdram_params->ch[channel].rank << 18);
  574. need_trainig = 1;
  575. }
  576. reg = readl(&publ->datx8[2].dxgsr[0]);
  577. if (reg & (1 << 4)) {
  578. sdram_params->ch[channel].bw = 1;
  579. set_bandwidth_ratio(chan, channel,
  580. sdram_params->ch[channel].bw,
  581. dram->grf);
  582. need_trainig = 1;
  583. }
  584. }
  585. /* Assume the Die bit width are the same with the chip bit width */
  586. sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
  587. if (need_trainig &&
  588. (data_training(chan, channel, sdram_params) < 0)) {
  589. if (sdram_params->base.dramtype == LPDDR3) {
  590. ddr_phy_ctl_reset(dram->cru, channel, 1);
  591. udelay(10);
  592. ddr_phy_ctl_reset(dram->cru, channel, 0);
  593. udelay(10);
  594. }
  595. debug("2nd data training failed!");
  596. return -EIO;
  597. }
  598. return 0;
  599. }
  600. static int sdram_col_row_detect(struct dram_info *dram, int channel,
  601. struct rk3288_sdram_params *sdram_params)
  602. {
  603. int row, col;
  604. unsigned int addr;
  605. const struct chan_info *chan = &dram->chan[channel];
  606. struct rk3288_ddr_pctl *pctl = chan->pctl;
  607. struct rk3288_ddr_publ *publ = chan->publ;
  608. int ret = 0;
  609. /* Detect col */
  610. for (col = 11; col >= 9; col--) {
  611. writel(0, CONFIG_SYS_SDRAM_BASE);
  612. addr = CONFIG_SYS_SDRAM_BASE +
  613. (1 << (col + sdram_params->ch[channel].bw - 1));
  614. writel(TEST_PATTEN, addr);
  615. if ((readl(addr) == TEST_PATTEN) &&
  616. (readl(CONFIG_SYS_SDRAM_BASE) == 0))
  617. break;
  618. }
  619. if (col == 8) {
  620. printf("Col detect error\n");
  621. ret = -EINVAL;
  622. goto out;
  623. } else {
  624. sdram_params->ch[channel].col = col;
  625. }
  626. move_to_config_state(publ, pctl);
  627. writel(4, &chan->msch->ddrconf);
  628. move_to_access_state(chan);
  629. /* Detect row*/
  630. for (row = 16; row >= 12; row--) {
  631. writel(0, CONFIG_SYS_SDRAM_BASE);
  632. addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
  633. writel(TEST_PATTEN, addr);
  634. if ((readl(addr) == TEST_PATTEN) &&
  635. (readl(CONFIG_SYS_SDRAM_BASE) == 0))
  636. break;
  637. }
  638. if (row == 11) {
  639. printf("Row detect error\n");
  640. ret = -EINVAL;
  641. } else {
  642. sdram_params->ch[channel].cs1_row = row;
  643. sdram_params->ch[channel].row_3_4 = 0;
  644. debug("chn %d col %d, row %d\n", channel, col, row);
  645. sdram_params->ch[channel].cs0_row = row;
  646. }
  647. out:
  648. return ret;
  649. }
  650. static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params)
  651. {
  652. int i, tmp, size, ret = 0;
  653. tmp = sdram_params->ch[0].col - 9;
  654. tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
  655. tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);
  656. size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
  657. for (i = 0; i < size; i++)
  658. if (tmp == ddrconf_table[i])
  659. break;
  660. if (i >= size) {
  661. printf("niu config not found\n");
  662. ret = -EINVAL;
  663. } else {
  664. sdram_params->base.ddrconfig = i;
  665. }
  666. return ret;
  667. }
  668. static int sdram_get_stride(struct rk3288_sdram_params *sdram_params)
  669. {
  670. int stride = -1;
  671. int ret = 0;
  672. long cap = sdram_params->num_channels * (1u <<
  673. (sdram_params->ch[0].cs0_row +
  674. sdram_params->ch[0].col +
  675. (sdram_params->ch[0].rank - 1) +
  676. sdram_params->ch[0].bw +
  677. 3 - 20));
  678. switch (cap) {
  679. case 512:
  680. stride = 0;
  681. break;
  682. case 1024:
  683. stride = 5;
  684. break;
  685. case 2048:
  686. stride = 9;
  687. break;
  688. case 4096:
  689. stride = 0xd;
  690. break;
  691. default:
  692. stride = -1;
  693. printf("could not find correct stride, cap error!\n");
  694. ret = -EINVAL;
  695. break;
  696. }
  697. sdram_params->base.stride = stride;
  698. return ret;
  699. }
  700. static int sdram_init(struct dram_info *dram,
  701. struct rk3288_sdram_params *sdram_params)
  702. {
  703. int channel;
  704. int zqcr;
  705. int ret;
  706. debug("%s start\n", __func__);
  707. if ((sdram_params->base.dramtype == DDR3 &&
  708. sdram_params->base.ddr_freq > 800000000) ||
  709. (sdram_params->base.dramtype == LPDDR3 &&
  710. sdram_params->base.ddr_freq > 533000000)) {
  711. debug("SDRAM frequency is too high!");
  712. return -E2BIG;
  713. }
  714. debug("ddr clk dpll\n");
  715. ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
  716. debug("ret=%d\n", ret);
  717. if (ret) {
  718. debug("Could not set DDR clock\n");
  719. return ret;
  720. }
  721. for (channel = 0; channel < 2; channel++) {
  722. const struct chan_info *chan = &dram->chan[channel];
  723. struct rk3288_ddr_pctl *pctl = chan->pctl;
  724. struct rk3288_ddr_publ *publ = chan->publ;
  725. /* map all the 4GB space to the current channel */
  726. if (channel)
  727. rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17);
  728. else
  729. rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a);
  730. phy_pctrl_reset(dram->cru, publ, channel);
  731. phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
  732. dfi_cfg(pctl, sdram_params->base.dramtype);
  733. pctl_cfg(channel, pctl, sdram_params, dram->grf);
  734. phy_cfg(chan, channel, sdram_params);
  735. phy_init(publ);
  736. writel(POWER_UP_START, &pctl->powctl);
  737. while (!(readl(&pctl->powstat) & POWER_UP_DONE))
  738. ;
  739. memory_init(publ, sdram_params->base.dramtype);
  740. move_to_config_state(publ, pctl);
  741. if (sdram_params->base.dramtype == LPDDR3) {
  742. send_command(pctl, 3, DESELECT_CMD, 0);
  743. udelay(1);
  744. send_command(pctl, 3, PREA_CMD, 0);
  745. udelay(1);
  746. send_command_op(pctl, 3, MRS_CMD, 63, 0xfc);
  747. udelay(1);
  748. send_command_op(pctl, 3, MRS_CMD, 1,
  749. sdram_params->phy_timing.mr[1]);
  750. udelay(1);
  751. send_command_op(pctl, 3, MRS_CMD, 2,
  752. sdram_params->phy_timing.mr[2]);
  753. udelay(1);
  754. send_command_op(pctl, 3, MRS_CMD, 3,
  755. sdram_params->phy_timing.mr[3]);
  756. udelay(1);
  757. }
  758. /* Using 32bit bus width for detect */
  759. sdram_params->ch[channel].bw = 2;
  760. set_bandwidth_ratio(chan, channel,
  761. sdram_params->ch[channel].bw, dram->grf);
  762. /*
  763. * set cs, using n=3 for detect
  764. * CS0, n=1
  765. * CS1, n=2
  766. * CS0 & CS1, n = 3
  767. */
  768. sdram_params->ch[channel].rank = 2,
  769. clrsetbits_le32(&publ->pgcr, 0xF << 18,
  770. (sdram_params->ch[channel].rank | 1) << 18);
  771. /* DS=40ohm,ODT=155ohm */
  772. zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
  773. 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
  774. 0x19 << PD_OUTPUT_SHIFT;
  775. writel(zqcr, &publ->zq1cr[0]);
  776. writel(zqcr, &publ->zq0cr[0]);
  777. if (sdram_params->base.dramtype == LPDDR3) {
  778. /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
  779. udelay(10);
  780. send_command_op(pctl,
  781. sdram_params->ch[channel].rank | 1,
  782. MRS_CMD, 11,
  783. sdram_params->base.odt ? 3 : 0);
  784. if (channel == 0) {
  785. writel(0, &pctl->mrrcfg0);
  786. send_command_op(pctl, 1, MRR_CMD, 8, 0);
  787. /* S8 */
  788. if ((readl(&pctl->mrrstat0) & 0x3) != 3) {
  789. debug("failed!");
  790. return -EREMOTEIO;
  791. }
  792. }
  793. }
  794. /* Detect the rank and bit-width with data-training */
  795. sdram_rank_bw_detect(dram, channel, sdram_params);
  796. if (sdram_params->base.dramtype == LPDDR3) {
  797. u32 i;
  798. writel(0, &pctl->mrrcfg0);
  799. for (i = 0; i < 17; i++)
  800. send_command_op(pctl, 1, MRR_CMD, i, 0);
  801. }
  802. writel(15, &chan->msch->ddrconf);
  803. move_to_access_state(chan);
  804. /* DDR3 and LPDDR3 are always 8 bank, no need detect */
  805. sdram_params->ch[channel].bk = 3;
  806. /* Detect Col and Row number*/
  807. ret = sdram_col_row_detect(dram, channel, sdram_params);
  808. if (ret)
  809. goto error;
  810. }
  811. /* Find NIU DDR configuration */
  812. ret = sdram_get_niu_config(sdram_params);
  813. if (ret)
  814. goto error;
  815. /* Find stride setting */
  816. ret = sdram_get_stride(sdram_params);
  817. if (ret)
  818. goto error;
  819. dram_all_config(dram, sdram_params);
  820. debug("%s done\n", __func__);
  821. return 0;
  822. error:
  823. printf("DRAM init failed!\n");
  824. hang();
  825. }
  826. # ifdef CONFIG_ROCKCHIP_FAST_SPL
  827. static int veyron_init(struct dram_info *priv)
  828. {
  829. struct udevice *pmic;
  830. int ret;
  831. ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
  832. if (ret)
  833. return ret;
  834. /* Slowly raise to max CPU voltage to prevent overshoot */
  835. ret = rk8xx_spl_configure_buck(pmic, 1, 1200000);
  836. if (ret)
  837. return ret;
  838. udelay(175);/* Must wait for voltage to stabilize, 2mV/us */
  839. ret = rk8xx_spl_configure_buck(pmic, 1, 1400000);
  840. if (ret)
  841. return ret;
  842. udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
  843. rk3288_clk_configure_cpu(priv->cru, priv->grf);
  844. return 0;
  845. }
  846. # endif
  847. static int setup_sdram(struct udevice *dev)
  848. {
  849. struct dram_info *priv = dev_get_priv(dev);
  850. struct rk3288_sdram_params *params = dev_get_platdata(dev);
  851. # ifdef CONFIG_ROCKCHIP_FAST_SPL
  852. if (priv->is_veyron) {
  853. int ret;
  854. ret = veyron_init(priv);
  855. if (ret)
  856. return ret;
  857. }
  858. # endif
  859. return sdram_init(priv, params);
  860. }
  861. static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
  862. {
  863. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  864. struct rk3288_sdram_params *params = dev_get_platdata(dev);
  865. int ret;
  866. /* Rk3288 supports dual-channel, set default channel num to 2 */
  867. params->num_channels = 2;
  868. ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
  869. (u32 *)&params->pctl_timing,
  870. sizeof(params->pctl_timing) / sizeof(u32));
  871. if (ret) {
  872. debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
  873. return -EINVAL;
  874. }
  875. ret = dev_read_u32_array(dev, "rockchip,phy-timing",
  876. (u32 *)&params->phy_timing,
  877. sizeof(params->phy_timing) / sizeof(u32));
  878. if (ret) {
  879. debug("%s: Cannot read rockchip,phy-timing\n", __func__);
  880. return -EINVAL;
  881. }
  882. ret = dev_read_u32_array(dev, "rockchip,sdram-params",
  883. (u32 *)&params->base,
  884. sizeof(params->base) / sizeof(u32));
  885. if (ret) {
  886. debug("%s: Cannot read rockchip,sdram-params\n", __func__);
  887. return -EINVAL;
  888. }
  889. #ifdef CONFIG_ROCKCHIP_FAST_SPL
  890. struct dram_info *priv = dev_get_priv(dev);
  891. priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron");
  892. #endif
  893. ret = regmap_init_mem(dev_ofnode(dev), &params->map);
  894. if (ret)
  895. return ret;
  896. #endif
  897. return 0;
  898. }
  899. #endif /* CONFIG_SPL_BUILD */
  900. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  901. static int conv_of_platdata(struct udevice *dev)
  902. {
  903. struct rk3288_sdram_params *plat = dev_get_platdata(dev);
  904. struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
  905. int ret;
  906. memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
  907. sizeof(plat->pctl_timing));
  908. memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
  909. sizeof(plat->phy_timing));
  910. memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
  911. /* Rk3288 supports dual-channel, set default channel num to 2 */
  912. plat->num_channels = 2;
  913. ret = regmap_init_mem_platdata(dev, of_plat->reg,
  914. ARRAY_SIZE(of_plat->reg) / 2,
  915. &plat->map);
  916. if (ret)
  917. return ret;
  918. return 0;
  919. }
  920. #endif
  921. static int rk3288_dmc_probe(struct udevice *dev)
  922. {
  923. #ifdef CONFIG_SPL_BUILD
  924. struct rk3288_sdram_params *plat = dev_get_platdata(dev);
  925. struct udevice *dev_clk;
  926. struct regmap *map;
  927. int ret;
  928. #endif
  929. struct dram_info *priv = dev_get_priv(dev);
  930. priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
  931. #ifdef CONFIG_SPL_BUILD
  932. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  933. ret = conv_of_platdata(dev);
  934. if (ret)
  935. return ret;
  936. #endif
  937. map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
  938. if (IS_ERR(map))
  939. return PTR_ERR(map);
  940. priv->chan[0].msch = regmap_get_range(map, 0);
  941. priv->chan[1].msch = (struct rk3288_msch *)
  942. (regmap_get_range(map, 0) + 0x80);
  943. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  944. priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  945. priv->chan[0].pctl = regmap_get_range(plat->map, 0);
  946. priv->chan[0].publ = regmap_get_range(plat->map, 1);
  947. priv->chan[1].pctl = regmap_get_range(plat->map, 2);
  948. priv->chan[1].publ = regmap_get_range(plat->map, 3);
  949. ret = rockchip_get_clk(&dev_clk);
  950. if (ret)
  951. return ret;
  952. priv->ddr_clk.id = CLK_DDR;
  953. ret = clk_request(dev_clk, &priv->ddr_clk);
  954. if (ret)
  955. return ret;
  956. priv->cru = rockchip_get_cru();
  957. if (IS_ERR(priv->cru))
  958. return PTR_ERR(priv->cru);
  959. ret = setup_sdram(dev);
  960. if (ret)
  961. return ret;
  962. #else
  963. priv->info.base = CONFIG_SYS_SDRAM_BASE;
  964. priv->info.size = rockchip_sdram_size(
  965. (phys_addr_t)&priv->pmu->sys_reg[2]);
  966. #endif
  967. return 0;
  968. }
  969. static int rk3288_dmc_get_info(struct udevice *dev, struct ram_info *info)
  970. {
  971. struct dram_info *priv = dev_get_priv(dev);
  972. *info = priv->info;
  973. return 0;
  974. }
  975. static struct ram_ops rk3288_dmc_ops = {
  976. .get_info = rk3288_dmc_get_info,
  977. };
  978. static const struct udevice_id rk3288_dmc_ids[] = {
  979. { .compatible = "rockchip,rk3288-dmc" },
  980. { }
  981. };
  982. U_BOOT_DRIVER(dmc_rk3288) = {
  983. .name = "rockchip_rk3288_dmc",
  984. .id = UCLASS_RAM,
  985. .of_match = rk3288_dmc_ids,
  986. .ops = &rk3288_dmc_ops,
  987. #ifdef CONFIG_SPL_BUILD
  988. .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
  989. #endif
  990. .probe = rk3288_dmc_probe,
  991. .priv_auto_alloc_size = sizeof(struct dram_info),
  992. #ifdef CONFIG_SPL_BUILD
  993. .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
  994. #endif
  995. };