rk_pwm.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <div64.h>
  9. #include <dm.h>
  10. #include <pwm.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/pwm.h>
  15. #include <power/regulator.h>
  16. struct rk_pwm_priv {
  17. struct rk3288_pwm *regs;
  18. ulong freq;
  19. uint enable_conf;
  20. };
  21. static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
  22. {
  23. struct rk_pwm_priv *priv = dev_get_priv(dev);
  24. debug("%s: polarity=%u\n", __func__, polarity);
  25. priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
  26. if (polarity)
  27. priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
  28. else
  29. priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
  30. return 0;
  31. }
  32. static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  33. uint duty_ns)
  34. {
  35. struct rk_pwm_priv *priv = dev_get_priv(dev);
  36. struct rk3288_pwm *regs = priv->regs;
  37. unsigned long period, duty;
  38. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  39. writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
  40. PWM_CONTINUOUS | priv->enable_conf |
  41. RK_PWM_DISABLE,
  42. &regs->ctrl);
  43. period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
  44. duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
  45. writel(period, &regs->period_hpr);
  46. writel(duty, &regs->duty_lpr);
  47. debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
  48. return 0;
  49. }
  50. static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  51. {
  52. struct rk_pwm_priv *priv = dev_get_priv(dev);
  53. struct rk3288_pwm *regs = priv->regs;
  54. debug("%s: Enable '%s'\n", __func__, dev->name);
  55. clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
  56. return 0;
  57. }
  58. static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
  59. {
  60. struct rk_pwm_priv *priv = dev_get_priv(dev);
  61. priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
  62. return 0;
  63. }
  64. static int rk_pwm_probe(struct udevice *dev)
  65. {
  66. struct rk_pwm_priv *priv = dev_get_priv(dev);
  67. struct clk clk;
  68. int ret = 0;
  69. ret = clk_get_by_index(dev, 0, &clk);
  70. if (ret < 0) {
  71. debug("%s get clock fail!\n", __func__);
  72. return -EINVAL;
  73. }
  74. priv->freq = clk_get_rate(&clk);
  75. priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
  76. return 0;
  77. }
  78. static const struct pwm_ops rk_pwm_ops = {
  79. .set_invert = rk_pwm_set_invert,
  80. .set_config = rk_pwm_set_config,
  81. .set_enable = rk_pwm_set_enable,
  82. };
  83. static const struct udevice_id rk_pwm_ids[] = {
  84. { .compatible = "rockchip,rk3288-pwm" },
  85. { }
  86. };
  87. U_BOOT_DRIVER(rk_pwm) = {
  88. .name = "rk_pwm",
  89. .id = UCLASS_PWM,
  90. .of_match = rk_pwm_ids,
  91. .ops = &rk_pwm_ops,
  92. .ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
  93. .probe = rk_pwm_probe,
  94. .priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
  95. };