rockchip_dw_mmc.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2013 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <dt-structs.h>
  9. #include <dwmmc.h>
  10. #include <errno.h>
  11. #include <mapmem.h>
  12. #include <pwrseq.h>
  13. #include <syscon.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/arch-rockchip/periph.h>
  17. #include <linux/err.h>
  18. struct rockchip_mmc_plat {
  19. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  20. struct dtd_rockchip_rk3288_dw_mshc dtplat;
  21. #endif
  22. struct mmc_config cfg;
  23. struct mmc mmc;
  24. };
  25. struct rockchip_dwmmc_priv {
  26. struct clk clk;
  27. struct dwmci_host host;
  28. int fifo_depth;
  29. bool fifo_mode;
  30. u32 minmax[2];
  31. };
  32. static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
  33. {
  34. struct udevice *dev = host->priv;
  35. struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  36. int ret;
  37. ret = clk_set_rate(&priv->clk, freq);
  38. if (ret < 0) {
  39. debug("%s: err=%d\n", __func__, ret);
  40. return ret;
  41. }
  42. return freq;
  43. }
  44. static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
  45. {
  46. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  47. struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  48. struct dwmci_host *host = &priv->host;
  49. host->name = dev->name;
  50. host->ioaddr = dev_read_addr_ptr(dev);
  51. host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
  52. host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
  53. host->priv = dev;
  54. /* use non-removeable as sdcard and emmc as judgement */
  55. if (dev_read_bool(dev, "non-removable"))
  56. host->dev_index = 0;
  57. else
  58. host->dev_index = 1;
  59. priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
  60. if (priv->fifo_depth < 0)
  61. return -EINVAL;
  62. priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
  63. /*
  64. * 'clock-freq-min-max' is deprecated
  65. * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
  66. */
  67. if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
  68. int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
  69. if (val < 0)
  70. return val;
  71. priv->minmax[0] = 400000; /* 400 kHz */
  72. priv->minmax[1] = val;
  73. } else {
  74. debug("%s: 'clock-freq-min-max' property was deprecated.\n",
  75. __func__);
  76. }
  77. #endif
  78. return 0;
  79. }
  80. static int rockchip_dwmmc_probe(struct udevice *dev)
  81. {
  82. struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
  83. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  84. struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  85. struct dwmci_host *host = &priv->host;
  86. struct udevice *pwr_dev __maybe_unused;
  87. int ret;
  88. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  89. struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
  90. host->name = dev->name;
  91. host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  92. host->buswidth = dtplat->bus_width;
  93. host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
  94. host->priv = dev;
  95. host->dev_index = 0;
  96. priv->fifo_depth = dtplat->fifo_depth;
  97. priv->fifo_mode = 0;
  98. priv->minmax[0] = 400000; /* 400 kHz */
  99. priv->minmax[1] = dtplat->max_frequency;
  100. ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
  101. if (ret < 0)
  102. return ret;
  103. #else
  104. ret = clk_get_by_index(dev, 0, &priv->clk);
  105. if (ret < 0)
  106. return ret;
  107. #endif
  108. host->fifoth_val = MSIZE(0x2) |
  109. RX_WMARK(priv->fifo_depth / 2 - 1) |
  110. TX_WMARK(priv->fifo_depth / 2);
  111. host->fifo_mode = priv->fifo_mode;
  112. #ifdef CONFIG_PWRSEQ
  113. /* Enable power if needed */
  114. ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
  115. &pwr_dev);
  116. if (!ret) {
  117. ret = pwrseq_set_power(pwr_dev, true);
  118. if (ret)
  119. return ret;
  120. }
  121. #endif
  122. dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
  123. host->mmc = &plat->mmc;
  124. host->mmc->priv = &priv->host;
  125. host->mmc->dev = dev;
  126. upriv->mmc = host->mmc;
  127. return dwmci_probe(dev);
  128. }
  129. static int rockchip_dwmmc_bind(struct udevice *dev)
  130. {
  131. struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
  132. return dwmci_bind(dev, &plat->mmc, &plat->cfg);
  133. }
  134. static const struct udevice_id rockchip_dwmmc_ids[] = {
  135. { .compatible = "rockchip,rk2928-dw-mshc" },
  136. { .compatible = "rockchip,rk3288-dw-mshc" },
  137. { }
  138. };
  139. U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
  140. .name = "rockchip_rk3288_dw_mshc",
  141. .id = UCLASS_MMC,
  142. .of_match = rockchip_dwmmc_ids,
  143. .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
  144. .ops = &dm_dwmci_ops,
  145. .bind = rockchip_dwmmc_bind,
  146. .probe = rockchip_dwmmc_probe,
  147. .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
  148. .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
  149. };
  150. #ifdef CONFIG_PWRSEQ
  151. static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
  152. {
  153. struct gpio_desc reset;
  154. int ret;
  155. ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
  156. if (ret)
  157. return ret;
  158. dm_gpio_set_value(&reset, 1);
  159. udelay(1);
  160. dm_gpio_set_value(&reset, 0);
  161. udelay(200);
  162. return 0;
  163. }
  164. static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
  165. .set_power = rockchip_dwmmc_pwrseq_set_power,
  166. };
  167. static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
  168. { .compatible = "mmc-pwrseq-emmc" },
  169. { }
  170. };
  171. U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
  172. .name = "mmc_pwrseq_emmc",
  173. .id = UCLASS_PWRSEQ,
  174. .of_match = rockchip_dwmmc_pwrseq_ids,
  175. .ops = &rockchip_dwmmc_pwrseq_ops,
  176. };
  177. #endif