clk_rv1108.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  4. * Author: Andy Yan <andy.yan@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <bitfield.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/cru_rv1108.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <dm/lists.h>
  17. #include <dt-bindings/clock/rv1108-cru.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. enum {
  20. VCO_MAX_HZ = 2400U * 1000000,
  21. VCO_MIN_HZ = 600 * 1000000,
  22. OUTPUT_MAX_HZ = 2400U * 1000000,
  23. OUTPUT_MIN_HZ = 24 * 1000000,
  24. };
  25. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  26. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  27. .refdiv = _refdiv,\
  28. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  29. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  30. _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
  31. OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
  32. #hz "Hz cannot be hit with PLL "\
  33. "divisors on line " __stringify(__LINE__));
  34. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  35. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  36. /* use integer mode */
  37. static inline int rv1108_pll_id(enum rk_clk_id clk_id)
  38. {
  39. int id = 0;
  40. switch (clk_id) {
  41. case CLK_ARM:
  42. case CLK_DDR:
  43. id = clk_id - 1;
  44. break;
  45. case CLK_GENERAL:
  46. id = 2;
  47. break;
  48. default:
  49. printf("invalid pll id:%d\n", clk_id);
  50. id = -1;
  51. break;
  52. }
  53. return id;
  54. }
  55. static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id,
  56. const struct pll_div *div)
  57. {
  58. int pll_id = rv1108_pll_id(clk_id);
  59. struct rv1108_pll *pll = &cru->pll[pll_id];
  60. /* All PLLs have same VCO and output frequency range restrictions. */
  61. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  62. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  63. debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
  64. pll, div->fbdiv, div->refdiv, div->postdiv1,
  65. div->postdiv2, vco_hz, output_hz);
  66. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  67. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  68. /*
  69. * When power on or changing PLL setting,
  70. * we must force PLL into slow mode to ensure output stable clock.
  71. */
  72. rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
  73. WORK_MODE_SLOW << WORK_MODE_SHIFT);
  74. /* use integer mode */
  75. rk_setreg(&pll->con3, 1 << DSMPD_SHIFT);
  76. /* Power down */
  77. rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
  78. rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);
  79. rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK,
  80. (div->postdiv1 << POSTDIV1_SHIFT |
  81. div->postdiv2 << POSTDIV2_SHIFT |
  82. div->refdiv << REFDIV_SHIFT));
  83. rk_clrsetreg(&pll->con2, FRACDIV_MASK,
  84. (div->refdiv << REFDIV_SHIFT));
  85. /* Power Up */
  86. rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
  87. /* waiting for pll lock */
  88. while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT))
  89. udelay(1);
  90. /*
  91. * set PLL into normal mode.
  92. */
  93. rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
  94. WORK_MODE_NORMAL << WORK_MODE_SHIFT);
  95. return 0;
  96. }
  97. static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
  98. enum rk_clk_id clk_id)
  99. {
  100. uint32_t refdiv, fbdiv, postdiv1, postdiv2;
  101. uint32_t con0, con1, con3;
  102. int pll_id = rv1108_pll_id(clk_id);
  103. struct rv1108_pll *pll = &cru->pll[pll_id];
  104. uint32_t freq;
  105. con3 = readl(&pll->con3);
  106. if (con3 & WORK_MODE_MASK) {
  107. con0 = readl(&pll->con0);
  108. con1 = readl(&pll->con1);
  109. fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
  110. postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
  111. postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
  112. refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK;
  113. freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  114. } else {
  115. freq = OSC_HZ;
  116. }
  117. return freq;
  118. }
  119. static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
  120. {
  121. uint32_t con = readl(&cru->clksel_con[24]);
  122. ulong pll_rate;
  123. uint8_t div;
  124. if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
  125. pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  126. else
  127. pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
  128. /*default set 50MHZ for gmac*/
  129. if (!rate)
  130. rate = 50000000;
  131. div = DIV_ROUND_UP(pll_rate, rate) - 1;
  132. if (div <= 0x1f)
  133. rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
  134. div << MAC_CLK_DIV_SHIFT);
  135. else
  136. debug("Unsupported div for gmac:%d\n", div);
  137. return DIV_TO_RATE(pll_rate, div);
  138. }
  139. static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
  140. {
  141. u32 con = readl(&cru->clksel_con[27]);
  142. u32 pll_rate;
  143. u32 div;
  144. if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
  145. pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  146. else
  147. pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
  148. div = DIV_ROUND_UP(pll_rate, rate) - 1;
  149. if (div <= 0x3f)
  150. rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
  151. div << SFC_CLK_DIV_SHIFT);
  152. else
  153. debug("Unsupported sfc clk rate:%d\n", rate);
  154. return DIV_TO_RATE(pll_rate, div);
  155. }
  156. static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
  157. {
  158. u32 div, val;
  159. val = readl(&cru->clksel_con[22]);
  160. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  161. CLK_SARADC_DIV_CON_WIDTH);
  162. return DIV_TO_RATE(OSC_HZ, div);
  163. }
  164. static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
  165. {
  166. int src_clk_div;
  167. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  168. assert(src_clk_div < 128);
  169. rk_clrsetreg(&cru->clksel_con[22],
  170. CLK_SARADC_DIV_CON_MASK,
  171. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  172. return rv1108_saradc_get_clk(cru);
  173. }
  174. static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru)
  175. {
  176. u32 div, val;
  177. val = readl(&cru->clksel_con[28]);
  178. div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT,
  179. CLK_VIO_DIV_CON_WIDTH);
  180. return DIV_TO_RATE(GPLL_HZ, div);
  181. }
  182. static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz)
  183. {
  184. int src_clk_div;
  185. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
  186. assert(src_clk_div < 32);
  187. rk_clrsetreg(&cru->clksel_con[28],
  188. ACLK_VIO1_CLK_DIV_MASK | ACLK_VIO1_PLL_SEL_MASK,
  189. (src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) |
  190. (VIO_PLL_SEL_GPLL << ACLK_VIO1_PLL_SEL_SHIFT));
  191. return rv1108_aclk_vio1_get_clk(cru);
  192. }
  193. static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru)
  194. {
  195. u32 div, val;
  196. val = readl(&cru->clksel_con[28]);
  197. div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT,
  198. CLK_VIO_DIV_CON_WIDTH);
  199. return DIV_TO_RATE(GPLL_HZ, div);
  200. }
  201. static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz)
  202. {
  203. int src_clk_div;
  204. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
  205. assert(src_clk_div < 32);
  206. rk_clrsetreg(&cru->clksel_con[28],
  207. ACLK_VIO0_CLK_DIV_MASK | ACLK_VIO0_PLL_SEL_MASK,
  208. (src_clk_div << ACLK_VIO0_CLK_DIV_SHIFT) |
  209. (VIO_PLL_SEL_GPLL << ACLK_VIO0_PLL_SEL_SHIFT));
  210. /*HCLK_VIO default div = 4*/
  211. rk_clrsetreg(&cru->clksel_con[29],
  212. HCLK_VIO_CLK_DIV_MASK,
  213. 3 << HCLK_VIO_CLK_DIV_SHIFT);
  214. /*PCLK_VIO default div = 4*/
  215. rk_clrsetreg(&cru->clksel_con[29],
  216. PCLK_VIO_CLK_DIV_MASK,
  217. 3 << PCLK_VIO_CLK_DIV_SHIFT);
  218. return rv1108_aclk_vio0_get_clk(cru);
  219. }
  220. static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru)
  221. {
  222. u32 div, val;
  223. val = readl(&cru->clksel_con[32]);
  224. div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT,
  225. DCLK_VOP_DIV_CON_WIDTH);
  226. return DIV_TO_RATE(GPLL_HZ, div);
  227. }
  228. static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz)
  229. {
  230. int src_clk_div;
  231. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
  232. assert(src_clk_div < 64);
  233. rk_clrsetreg(&cru->clksel_con[32],
  234. DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK |
  235. DCLK_VOP_SEL_SHIFT,
  236. (src_clk_div << DCLK_VOP_CLK_DIV_SHIFT) |
  237. (DCLK_VOP_PLL_SEL_GPLL << DCLK_VOP_PLL_SEL_SHIFT) |
  238. (DCLK_VOP_SEL_PLL << DCLK_VOP_SEL_SHIFT));
  239. return rv1108_dclk_vop_get_clk(cru);
  240. }
  241. static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru)
  242. {
  243. u32 div, val;
  244. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  245. val = readl(&cru->clksel_con[2]);
  246. div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT,
  247. ACLK_BUS_DIV_CON_WIDTH);
  248. return DIV_TO_RATE(parent_rate, div);
  249. }
  250. static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz)
  251. {
  252. int src_clk_div;
  253. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  254. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  255. assert(src_clk_div < 32);
  256. rk_clrsetreg(&cru->clksel_con[2],
  257. ACLK_BUS_DIV_CON_MASK | ACLK_BUS_PLL_SEL_MASK,
  258. (src_clk_div << ACLK_BUS_DIV_CON_SHIFT) |
  259. (ACLK_BUS_PLL_SEL_GPLL << ACLK_BUS_PLL_SEL_SHIFT));
  260. return rv1108_aclk_bus_get_clk(cru);
  261. }
  262. static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru)
  263. {
  264. u32 div, val;
  265. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  266. val = readl(&cru->clksel_con[23]);
  267. div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT,
  268. PERI_DIV_CON_WIDTH);
  269. return DIV_TO_RATE(parent_rate, div);
  270. }
  271. static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru)
  272. {
  273. u32 div, val;
  274. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  275. val = readl(&cru->clksel_con[23]);
  276. div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT,
  277. PERI_DIV_CON_WIDTH);
  278. return DIV_TO_RATE(parent_rate, div);
  279. }
  280. static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru)
  281. {
  282. u32 div, val;
  283. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  284. val = readl(&cru->clksel_con[23]);
  285. div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT,
  286. PERI_DIV_CON_WIDTH);
  287. return DIV_TO_RATE(parent_rate, div);
  288. }
  289. static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
  290. {
  291. int src_clk_div;
  292. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  293. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  294. assert(src_clk_div < 32);
  295. rk_clrsetreg(&cru->clksel_con[23],
  296. ACLK_PERI_DIV_CON_MASK | ACLK_PERI_PLL_SEL_MASK,
  297. (src_clk_div << ACLK_PERI_DIV_CON_SHIFT) |
  298. (ACLK_PERI_PLL_SEL_GPLL << ACLK_PERI_PLL_SEL_SHIFT));
  299. return rv1108_aclk_peri_get_clk(cru);
  300. }
  301. static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
  302. {
  303. int src_clk_div;
  304. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  305. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  306. assert(src_clk_div < 32);
  307. rk_clrsetreg(&cru->clksel_con[23],
  308. HCLK_PERI_DIV_CON_MASK,
  309. (src_clk_div << HCLK_PERI_DIV_CON_SHIFT));
  310. return rv1108_hclk_peri_get_clk(cru);
  311. }
  312. static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
  313. {
  314. int src_clk_div;
  315. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  316. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  317. assert(src_clk_div < 32);
  318. rk_clrsetreg(&cru->clksel_con[23],
  319. PCLK_PERI_DIV_CON_MASK,
  320. (src_clk_div << PCLK_PERI_DIV_CON_SHIFT));
  321. return rv1108_pclk_peri_get_clk(cru);
  322. }
  323. static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id)
  324. {
  325. u32 div, con;
  326. switch (clk_id) {
  327. case SCLK_I2C0_PMU:
  328. con = readl(&cru->clksel_con[19]);
  329. div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT,
  330. I2C_DIV_CON_WIDTH);
  331. break;
  332. case SCLK_I2C1:
  333. con = readl(&cru->clksel_con[19]);
  334. div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT,
  335. I2C_DIV_CON_WIDTH);
  336. break;
  337. case SCLK_I2C2:
  338. con = readl(&cru->clksel_con[20]);
  339. div = bitfield_extract(con, CLK_I2C2_DIV_CON_SHIFT,
  340. I2C_DIV_CON_WIDTH);
  341. break;
  342. case SCLK_I2C3:
  343. con = readl(&cru->clksel_con[20]);
  344. div = bitfield_extract(con, CLK_I2C3_DIV_CON_SHIFT,
  345. I2C_DIV_CON_WIDTH);
  346. break;
  347. default:
  348. printf("do not support this i2c bus\n");
  349. return -EINVAL;
  350. }
  351. return DIV_TO_RATE(GPLL_HZ, div);
  352. }
  353. static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz)
  354. {
  355. int src_clk_div;
  356. /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
  357. src_clk_div = GPLL_HZ / hz;
  358. assert(src_clk_div - 1 <= 127);
  359. switch (clk_id) {
  360. case SCLK_I2C0_PMU:
  361. rk_clrsetreg(&cru->clksel_con[19],
  362. CLK_I2C0_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
  363. (src_clk_div << CLK_I2C0_DIV_CON_SHIFT) |
  364. (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
  365. break;
  366. case SCLK_I2C1:
  367. rk_clrsetreg(&cru->clksel_con[19],
  368. CLK_I2C1_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
  369. (src_clk_div << CLK_I2C1_DIV_CON_SHIFT) |
  370. (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
  371. break;
  372. case SCLK_I2C2:
  373. rk_clrsetreg(&cru->clksel_con[20],
  374. CLK_I2C2_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
  375. (src_clk_div << CLK_I2C2_DIV_CON_SHIFT) |
  376. (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
  377. break;
  378. case SCLK_I2C3:
  379. rk_clrsetreg(&cru->clksel_con[20],
  380. CLK_I2C3_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
  381. (src_clk_div << CLK_I2C3_DIV_CON_SHIFT) |
  382. (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
  383. break;
  384. default:
  385. printf("do not support this i2c bus\n");
  386. return -EINVAL;
  387. }
  388. return rv1108_i2c_get_clk(cru, clk_id);
  389. }
  390. static ulong rv1108_mmc_get_clk(struct rv1108_cru *cru)
  391. {
  392. u32 div, con;
  393. ulong mmc_clk;
  394. con = readl(&cru->clksel_con[26]);
  395. div = bitfield_extract(con, EMMC_CLK_DIV_SHIFT, 8);
  396. con = readl(&cru->clksel_con[25]);
  397. if ((con & EMMC_PLL_SEL_MASK) >> EMMC_PLL_SEL_SHIFT == EMMC_PLL_SEL_OSC)
  398. mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2;
  399. else
  400. mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2;
  401. debug("%s div %d get_clk %ld\n", __func__, div, mmc_clk);
  402. return mmc_clk;
  403. }
  404. static ulong rv1108_mmc_set_clk(struct rv1108_cru *cru, ulong rate)
  405. {
  406. int div;
  407. u32 pll_rate;
  408. div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate);
  409. if (div < 127) {
  410. debug("%s source gpll\n", __func__);
  411. rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
  412. (EMMC_PLL_SEL_GPLL << EMMC_PLL_SEL_SHIFT));
  413. pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  414. } else {
  415. debug("%s source 24m\n", __func__);
  416. rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
  417. (EMMC_PLL_SEL_OSC << EMMC_PLL_SEL_SHIFT));
  418. pll_rate = OSC_HZ;
  419. }
  420. div = DIV_ROUND_UP(pll_rate / 2, rate);
  421. rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK,
  422. ((div - 1) << EMMC_CLK_DIV_SHIFT));
  423. debug("%s set_rate %ld div %d\n", __func__, rate, div);
  424. return DIV_TO_RATE(pll_rate, div);
  425. }
  426. static ulong rv1108_clk_get_rate(struct clk *clk)
  427. {
  428. struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
  429. switch (clk->id) {
  430. case 0 ... 63:
  431. return rkclk_pll_get_rate(priv->cru, clk->id);
  432. case SCLK_SARADC:
  433. return rv1108_saradc_get_clk(priv->cru);
  434. case ACLK_VIO0:
  435. return rv1108_aclk_vio0_get_clk(priv->cru);
  436. case ACLK_VIO1:
  437. return rv1108_aclk_vio1_get_clk(priv->cru);
  438. case DCLK_VOP:
  439. return rv1108_dclk_vop_get_clk(priv->cru);
  440. case ACLK_PRE:
  441. return rv1108_aclk_bus_get_clk(priv->cru);
  442. case ACLK_PERI:
  443. return rv1108_aclk_peri_get_clk(priv->cru);
  444. case HCLK_PERI:
  445. return rv1108_hclk_peri_get_clk(priv->cru);
  446. case PCLK_PERI:
  447. return rv1108_pclk_peri_get_clk(priv->cru);
  448. case SCLK_I2C0_PMU:
  449. case SCLK_I2C1:
  450. case SCLK_I2C2:
  451. case SCLK_I2C3:
  452. return rv1108_i2c_get_clk(priv->cru, clk->id);
  453. case HCLK_EMMC:
  454. case SCLK_EMMC:
  455. case SCLK_EMMC_SAMPLE:
  456. return rv1108_mmc_get_clk(priv->cru);
  457. default:
  458. return -ENOENT;
  459. }
  460. }
  461. static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
  462. {
  463. struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
  464. ulong new_rate;
  465. switch (clk->id) {
  466. case SCLK_MAC:
  467. new_rate = rv1108_mac_set_clk(priv->cru, rate);
  468. break;
  469. case SCLK_SFC:
  470. new_rate = rv1108_sfc_set_clk(priv->cru, rate);
  471. break;
  472. case SCLK_SARADC:
  473. new_rate = rv1108_saradc_set_clk(priv->cru, rate);
  474. break;
  475. case ACLK_VIO0:
  476. new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate);
  477. break;
  478. case ACLK_VIO1:
  479. new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate);
  480. break;
  481. case DCLK_VOP:
  482. new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate);
  483. break;
  484. case ACLK_PRE:
  485. new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate);
  486. break;
  487. case ACLK_PERI:
  488. new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate);
  489. break;
  490. case HCLK_PERI:
  491. new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate);
  492. break;
  493. case PCLK_PERI:
  494. new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate);
  495. break;
  496. case SCLK_I2C0_PMU:
  497. case SCLK_I2C1:
  498. case SCLK_I2C2:
  499. case SCLK_I2C3:
  500. new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate);
  501. break;
  502. case HCLK_EMMC:
  503. case SCLK_EMMC:
  504. new_rate = rv1108_mmc_set_clk(priv->cru, rate);
  505. break;
  506. default:
  507. return -ENOENT;
  508. }
  509. return new_rate;
  510. }
  511. static const struct clk_ops rv1108_clk_ops = {
  512. .get_rate = rv1108_clk_get_rate,
  513. .set_rate = rv1108_clk_set_rate,
  514. };
  515. static void rkclk_init(struct rv1108_cru *cru)
  516. {
  517. unsigned int apll, dpll, gpll;
  518. unsigned int aclk_bus, aclk_peri, hclk_peri, pclk_peri;
  519. aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2);
  520. aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2);
  521. hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2);
  522. pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2);
  523. rv1108_aclk_vio0_set_clk(cru, 297000000);
  524. rv1108_aclk_vio1_set_clk(cru, 297000000);
  525. /* configure apll */
  526. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  527. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  528. aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ);
  529. aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ);
  530. hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ);
  531. pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ);
  532. apll = rkclk_pll_get_rate(cru, CLK_ARM);
  533. dpll = rkclk_pll_get_rate(cru, CLK_DDR);
  534. gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
  535. rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
  536. 0 << MAC_CLK_DIV_SHIFT);
  537. printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
  538. printf("ACLK_BUS: %d ACLK_PERI:%d HCLK_PERI:%d PCLK_PERI:%d\n",
  539. aclk_bus, aclk_peri, hclk_peri, pclk_peri);
  540. }
  541. static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
  542. {
  543. struct rv1108_clk_priv *priv = dev_get_priv(dev);
  544. priv->cru = dev_read_addr_ptr(dev);
  545. return 0;
  546. }
  547. static int rv1108_clk_probe(struct udevice *dev)
  548. {
  549. struct rv1108_clk_priv *priv = dev_get_priv(dev);
  550. rkclk_init(priv->cru);
  551. return 0;
  552. }
  553. static int rv1108_clk_bind(struct udevice *dev)
  554. {
  555. int ret;
  556. struct udevice *sys_child, *sf_child;
  557. struct sysreset_reg *priv;
  558. struct softreset_reg *sf_priv;
  559. /* The reset driver does not have a device node, so bind it here */
  560. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  561. &sys_child);
  562. if (ret) {
  563. debug("Warning: No sysreset driver: ret=%d\n", ret);
  564. } else {
  565. priv = malloc(sizeof(struct sysreset_reg));
  566. priv->glb_srst_fst_value = offsetof(struct rv1108_cru,
  567. glb_srst_fst_val);
  568. priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
  569. glb_srst_snd_val);
  570. sys_child->priv = priv;
  571. }
  572. #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
  573. ret = offsetof(struct rk3368_cru, softrst_con[0]);
  574. ret = rockchip_reset_bind(dev, ret, 13);
  575. if (ret)
  576. debug("Warning: software reset driver bind faile\n");
  577. #endif
  578. ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
  579. dev_ofnode(dev), &sf_child);
  580. if (ret) {
  581. debug("Warning: No rockchip reset driver: ret=%d\n", ret);
  582. } else {
  583. sf_priv = malloc(sizeof(struct softreset_reg));
  584. sf_priv->sf_reset_offset = offsetof(struct rv1108_cru,
  585. softrst_con[0]);
  586. sf_priv->sf_reset_num = 13;
  587. sf_child->priv = sf_priv;
  588. }
  589. return 0;
  590. }
  591. static const struct udevice_id rv1108_clk_ids[] = {
  592. { .compatible = "rockchip,rv1108-cru" },
  593. { }
  594. };
  595. U_BOOT_DRIVER(clk_rv1108) = {
  596. .name = "clk_rv1108",
  597. .id = UCLASS_CLK,
  598. .of_match = rv1108_clk_ids,
  599. .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
  600. .ops = &rv1108_clk_ops,
  601. .bind = rv1108_clk_bind,
  602. .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
  603. .probe = rv1108_clk_probe,
  604. };