clk_rk3368.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. * Author: Andy Yan <andy.yan@rock-chips.com>
  5. * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  6. */
  7. #include <common.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <dt-structs.h>
  11. #include <errno.h>
  12. #include <mapmem.h>
  13. #include <syscon.h>
  14. #include <bitfield.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/arch-rockchip/cru_rk3368.h>
  17. #include <asm/arch-rockchip/hardware.h>
  18. #include <asm/io.h>
  19. #include <dm/lists.h>
  20. #include <dt-bindings/clock/rk3368-cru.h>
  21. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  22. struct rk3368_clk_plat {
  23. struct dtd_rockchip_rk3368_cru dtd;
  24. };
  25. #endif
  26. struct pll_div {
  27. u32 nr;
  28. u32 nf;
  29. u32 no;
  30. };
  31. #define OSC_HZ (24 * 1000 * 1000)
  32. #define APLL_L_HZ (800 * 1000 * 1000)
  33. #define APLL_B_HZ (816 * 1000 * 1000)
  34. #define GPLL_HZ (576 * 1000 * 1000)
  35. #define CPLL_HZ (400 * 1000 * 1000)
  36. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  37. #define PLL_DIVISORS(hz, _nr, _no) { \
  38. .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
  39. _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  40. (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
  41. "divisors on line " __stringify(__LINE__));
  42. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  43. static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
  44. static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
  45. #if !defined(CONFIG_TPL_BUILD)
  46. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
  47. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
  48. #endif
  49. #endif
  50. static ulong rk3368_clk_get_rate(struct clk *clk);
  51. /* Get pll rate by id */
  52. static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
  53. enum rk3368_pll_id pll_id)
  54. {
  55. uint32_t nr, no, nf;
  56. uint32_t con;
  57. struct rk3368_pll *pll = &cru->pll[pll_id];
  58. con = readl(&pll->con3);
  59. switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
  60. case PLL_MODE_SLOW:
  61. return OSC_HZ;
  62. case PLL_MODE_NORMAL:
  63. con = readl(&pll->con0);
  64. no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
  65. nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
  66. con = readl(&pll->con1);
  67. nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
  68. return (24 * nf / (nr * no)) * 1000000;
  69. case PLL_MODE_DEEP_SLOW:
  70. default:
  71. return 32768;
  72. }
  73. }
  74. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  75. static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
  76. const struct pll_div *div)
  77. {
  78. struct rk3368_pll *pll = &cru->pll[pll_id];
  79. /* All PLLs have same VCO and output frequency range restrictions*/
  80. uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  81. uint output_hz = vco_hz / div->no;
  82. debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  83. pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  84. /* enter slow mode and reset pll */
  85. rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
  86. PLL_RESET << PLL_RESET_SHIFT);
  87. rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
  88. ((div->nr - 1) << PLL_NR_SHIFT) |
  89. ((div->no - 1) << PLL_OD_SHIFT));
  90. writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
  91. /*
  92. * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
  93. * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
  94. */
  95. clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
  96. udelay(10);
  97. /* return from reset */
  98. rk_clrreg(&pll->con3, PLL_RESET_MASK);
  99. /* waiting for pll lock */
  100. while (!(readl(&pll->con1) & PLL_LOCK_STA))
  101. udelay(1);
  102. rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
  103. PLL_MODE_NORMAL << PLL_MODE_SHIFT);
  104. return 0;
  105. }
  106. #endif
  107. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  108. static void rkclk_init(struct rk3368_cru *cru)
  109. {
  110. u32 apllb, aplll, dpll, cpll, gpll;
  111. rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
  112. rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
  113. #if !defined(CONFIG_TPL_BUILD)
  114. /*
  115. * If we plan to return to the boot ROM, we can't increase the
  116. * GPLL rate from the SPL stage.
  117. */
  118. rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
  119. rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
  120. #endif
  121. apllb = rkclk_pll_get_rate(cru, APLLB);
  122. aplll = rkclk_pll_get_rate(cru, APLLL);
  123. dpll = rkclk_pll_get_rate(cru, DPLL);
  124. cpll = rkclk_pll_get_rate(cru, CPLL);
  125. gpll = rkclk_pll_get_rate(cru, GPLL);
  126. debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
  127. __func__, apllb, aplll, dpll, cpll, gpll);
  128. }
  129. #endif
  130. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  131. static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
  132. {
  133. u32 div, con, con_id, rate;
  134. u32 pll_rate;
  135. switch (clk_id) {
  136. case HCLK_SDMMC:
  137. con_id = 50;
  138. break;
  139. case HCLK_EMMC:
  140. con_id = 51;
  141. break;
  142. case SCLK_SDIO0:
  143. con_id = 48;
  144. break;
  145. default:
  146. return -EINVAL;
  147. }
  148. con = readl(&cru->clksel_con[con_id]);
  149. switch (con & MMC_PLL_SEL_MASK) {
  150. case MMC_PLL_SEL_GPLL:
  151. pll_rate = rkclk_pll_get_rate(cru, GPLL);
  152. break;
  153. case MMC_PLL_SEL_24M:
  154. pll_rate = OSC_HZ;
  155. break;
  156. case MMC_PLL_SEL_CPLL:
  157. pll_rate = rkclk_pll_get_rate(cru, CPLL);
  158. break;
  159. case MMC_PLL_SEL_USBPHY_480M:
  160. default:
  161. return -EINVAL;
  162. }
  163. div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
  164. rate = DIV_TO_RATE(pll_rate, div);
  165. debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
  166. return rate >> 1;
  167. }
  168. static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
  169. ulong rate,
  170. u32 *best_mux,
  171. u32 *best_div)
  172. {
  173. int i;
  174. ulong best_rate = 0;
  175. const ulong MHz = 1000000;
  176. const struct {
  177. u32 mux;
  178. ulong rate;
  179. } parents[] = {
  180. { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
  181. { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
  182. { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
  183. };
  184. debug("%s: target rate %ld\n", __func__, rate);
  185. for (i = 0; i < ARRAY_SIZE(parents); ++i) {
  186. /*
  187. * Find the largest rate no larger than the target-rate for
  188. * the current parent.
  189. */
  190. ulong parent_rate = parents[i].rate;
  191. u32 div = DIV_ROUND_UP(parent_rate, rate);
  192. u32 adj_div = div;
  193. ulong new_rate = parent_rate / adj_div;
  194. debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
  195. __func__, rate, parents[i].mux, parents[i].rate, div);
  196. /* Skip, if not representable */
  197. if ((div - 1) > MMC_CLK_DIV_MASK)
  198. continue;
  199. /* Skip, if we already have a better (or equal) solution */
  200. if (new_rate <= best_rate)
  201. continue;
  202. /* This is our new best rate. */
  203. best_rate = new_rate;
  204. *best_mux = parents[i].mux;
  205. *best_div = div - 1;
  206. }
  207. debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
  208. __func__, *best_mux, *best_div, best_rate);
  209. return best_rate;
  210. }
  211. static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
  212. {
  213. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  214. struct rk3368_cru *cru = priv->cru;
  215. ulong clk_id = clk->id;
  216. u32 con_id, mux = 0, div = 0;
  217. /* Find the best parent and rate */
  218. rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
  219. switch (clk_id) {
  220. case HCLK_SDMMC:
  221. con_id = 50;
  222. break;
  223. case HCLK_EMMC:
  224. con_id = 51;
  225. break;
  226. case SCLK_SDIO0:
  227. con_id = 48;
  228. break;
  229. default:
  230. return -EINVAL;
  231. }
  232. rk_clrsetreg(&cru->clksel_con[con_id],
  233. MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
  234. mux | div);
  235. return rk3368_mmc_get_clk(cru, clk_id);
  236. }
  237. #endif
  238. #if IS_ENABLED(CONFIG_TPL_BUILD)
  239. static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
  240. {
  241. const struct pll_div *dpll_cfg = NULL;
  242. const ulong MHz = 1000000;
  243. /* Fout = ((Fin /NR) * NF )/ NO */
  244. static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
  245. static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
  246. static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
  247. switch (set_rate) {
  248. case 1200*MHz:
  249. dpll_cfg = &dpll_1200;
  250. break;
  251. case 1332*MHz:
  252. dpll_cfg = &dpll_1332;
  253. break;
  254. case 1600*MHz:
  255. dpll_cfg = &dpll_1600;
  256. break;
  257. default:
  258. pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
  259. }
  260. rkclk_set_pll(cru, DPLL, dpll_cfg);
  261. return set_rate;
  262. }
  263. #endif
  264. #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
  265. static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
  266. {
  267. ulong ret;
  268. /*
  269. * The gmac clock can be derived either from an external clock
  270. * or can be generated from internally by a divider from SCLK_MAC.
  271. */
  272. if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
  273. /* An external clock will always generate the right rate... */
  274. ret = set_rate;
  275. } else {
  276. u32 con = readl(&cru->clksel_con[43]);
  277. ulong pll_rate;
  278. u8 div;
  279. if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
  280. GMAC_PLL_SELECT_GENERAL)
  281. pll_rate = GPLL_HZ;
  282. else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
  283. GMAC_PLL_SELECT_CODEC)
  284. pll_rate = CPLL_HZ;
  285. else
  286. /* CPLL is not set */
  287. return -EPERM;
  288. div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
  289. if (div <= 0x1f)
  290. rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
  291. div << GMAC_DIV_CON_SHIFT);
  292. else
  293. debug("Unsupported div for gmac:%d\n", div);
  294. return DIV_TO_RATE(pll_rate, div);
  295. }
  296. return ret;
  297. }
  298. #endif
  299. /*
  300. * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
  301. * to select either CPLL or GPLL as the clock-parent. The location within
  302. * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
  303. */
  304. struct spi_clkreg {
  305. uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
  306. uint8_t div_shift;
  307. uint8_t sel_shift;
  308. };
  309. /*
  310. * The entries are numbered relative to their offset from SCLK_SPI0.
  311. */
  312. static const struct spi_clkreg spi_clkregs[] = {
  313. [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
  314. [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
  315. [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
  316. };
  317. static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
  318. {
  319. return (val >> shift) & ((1 << width) - 1);
  320. }
  321. static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
  322. {
  323. const struct spi_clkreg *spiclk = NULL;
  324. u32 div, val;
  325. switch (clk_id) {
  326. case SCLK_SPI0 ... SCLK_SPI2:
  327. spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
  328. break;
  329. default:
  330. pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
  331. return -EINVAL;
  332. }
  333. val = readl(&cru->clksel_con[spiclk->reg]);
  334. div = extract_bits(val, 7, spiclk->div_shift);
  335. debug("%s: div 0x%x\n", __func__, div);
  336. return DIV_TO_RATE(GPLL_HZ, div);
  337. }
  338. static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
  339. {
  340. const struct spi_clkreg *spiclk = NULL;
  341. int src_clk_div;
  342. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
  343. assert(src_clk_div < 127);
  344. switch (clk_id) {
  345. case SCLK_SPI0 ... SCLK_SPI2:
  346. spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
  347. break;
  348. default:
  349. pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
  350. return -EINVAL;
  351. }
  352. rk_clrsetreg(&cru->clksel_con[spiclk->reg],
  353. ((0x7f << spiclk->div_shift) |
  354. (0x1 << spiclk->sel_shift)),
  355. ((src_clk_div << spiclk->div_shift) |
  356. (1 << spiclk->sel_shift)));
  357. return rk3368_spi_get_clk(cru, clk_id);
  358. }
  359. static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
  360. {
  361. u32 div, val;
  362. val = readl(&cru->clksel_con[25]);
  363. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  364. CLK_SARADC_DIV_CON_WIDTH);
  365. return DIV_TO_RATE(OSC_HZ, div);
  366. }
  367. static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
  368. {
  369. int src_clk_div;
  370. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  371. assert(src_clk_div < 128);
  372. rk_clrsetreg(&cru->clksel_con[25],
  373. CLK_SARADC_DIV_CON_MASK,
  374. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  375. return rk3368_saradc_get_clk(cru);
  376. }
  377. static ulong rk3368_clk_get_rate(struct clk *clk)
  378. {
  379. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  380. ulong rate = 0;
  381. debug("%s: id %ld\n", __func__, clk->id);
  382. switch (clk->id) {
  383. case PLL_CPLL:
  384. rate = rkclk_pll_get_rate(priv->cru, CPLL);
  385. break;
  386. case PLL_GPLL:
  387. rate = rkclk_pll_get_rate(priv->cru, GPLL);
  388. break;
  389. case SCLK_SPI0 ... SCLK_SPI2:
  390. rate = rk3368_spi_get_clk(priv->cru, clk->id);
  391. break;
  392. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  393. case HCLK_SDMMC:
  394. case HCLK_EMMC:
  395. rate = rk3368_mmc_get_clk(priv->cru, clk->id);
  396. break;
  397. #endif
  398. case SCLK_SARADC:
  399. rate = rk3368_saradc_get_clk(priv->cru);
  400. break;
  401. default:
  402. return -ENOENT;
  403. }
  404. return rate;
  405. }
  406. static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
  407. {
  408. __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  409. ulong ret = 0;
  410. debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
  411. switch (clk->id) {
  412. case SCLK_SPI0 ... SCLK_SPI2:
  413. ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
  414. break;
  415. #if IS_ENABLED(CONFIG_TPL_BUILD)
  416. case CLK_DDR:
  417. ret = rk3368_ddr_set_clk(priv->cru, rate);
  418. break;
  419. #endif
  420. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  421. case HCLK_SDMMC:
  422. case HCLK_EMMC:
  423. ret = rk3368_mmc_set_clk(clk, rate);
  424. break;
  425. #endif
  426. #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
  427. case SCLK_MAC:
  428. /* select the external clock */
  429. ret = rk3368_gmac_set_clk(priv->cru, rate);
  430. break;
  431. #endif
  432. case SCLK_SARADC:
  433. ret = rk3368_saradc_set_clk(priv->cru, rate);
  434. break;
  435. default:
  436. return -ENOENT;
  437. }
  438. return ret;
  439. }
  440. static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
  441. {
  442. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  443. struct rk3368_cru *cru = priv->cru;
  444. const char *clock_output_name;
  445. int ret;
  446. /*
  447. * If the requested parent is in the same clock-controller and
  448. * the id is SCLK_MAC ("sclk_mac"), switch to the internal
  449. * clock.
  450. */
  451. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
  452. debug("%s: switching GAMC to SCLK_MAC\n", __func__);
  453. rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
  454. return 0;
  455. }
  456. /*
  457. * Otherwise, we need to check the clock-output-names of the
  458. * requested parent to see if the requested id is "ext_gmac".
  459. */
  460. ret = dev_read_string_index(parent->dev, "clock-output-names",
  461. parent->id, &clock_output_name);
  462. if (ret < 0)
  463. return -ENODATA;
  464. /* If this is "ext_gmac", switch to the external clock input */
  465. if (!strcmp(clock_output_name, "ext_gmac")) {
  466. debug("%s: switching GMAC to external clock\n", __func__);
  467. rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
  468. return 0;
  469. }
  470. return -EINVAL;
  471. }
  472. static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
  473. {
  474. switch (clk->id) {
  475. case SCLK_MAC:
  476. return rk3368_gmac_set_parent(clk, parent);
  477. }
  478. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  479. return -ENOENT;
  480. }
  481. static int rk3368_clk_enable(struct clk *clk)
  482. {
  483. switch (clk->id) {
  484. case SCLK_MAC:
  485. case SCLK_MAC_RX:
  486. case SCLK_MAC_TX:
  487. case SCLK_MACREF:
  488. case SCLK_MACREF_OUT:
  489. case ACLK_GMAC:
  490. case PCLK_GMAC:
  491. /* Required to successfully probe the Designware GMAC driver */
  492. return 0;
  493. }
  494. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  495. return -ENOENT;
  496. }
  497. static struct clk_ops rk3368_clk_ops = {
  498. .get_rate = rk3368_clk_get_rate,
  499. .set_rate = rk3368_clk_set_rate,
  500. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  501. .set_parent = rk3368_clk_set_parent,
  502. #endif
  503. .enable = rk3368_clk_enable,
  504. };
  505. static int rk3368_clk_probe(struct udevice *dev)
  506. {
  507. struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
  508. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  509. struct rk3368_clk_plat *plat = dev_get_platdata(dev);
  510. priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  511. #endif
  512. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  513. rkclk_init(priv->cru);
  514. #endif
  515. return 0;
  516. }
  517. static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
  518. {
  519. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  520. struct rk3368_clk_priv *priv = dev_get_priv(dev);
  521. priv->cru = dev_read_addr_ptr(dev);
  522. #endif
  523. return 0;
  524. }
  525. static int rk3368_clk_bind(struct udevice *dev)
  526. {
  527. int ret;
  528. struct udevice *sys_child;
  529. struct sysreset_reg *priv;
  530. /* The reset driver does not have a device node, so bind it here */
  531. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  532. &sys_child);
  533. if (ret) {
  534. debug("Warning: No sysreset driver: ret=%d\n", ret);
  535. } else {
  536. priv = malloc(sizeof(struct sysreset_reg));
  537. priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
  538. glb_srst_fst_val);
  539. priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
  540. glb_srst_snd_val);
  541. sys_child->priv = priv;
  542. }
  543. #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
  544. ret = offsetof(struct rk3368_cru, softrst_con[0]);
  545. ret = rockchip_reset_bind(dev, ret, 15);
  546. if (ret)
  547. debug("Warning: software reset driver bind faile\n");
  548. #endif
  549. return ret;
  550. }
  551. static const struct udevice_id rk3368_clk_ids[] = {
  552. { .compatible = "rockchip,rk3368-cru" },
  553. { }
  554. };
  555. U_BOOT_DRIVER(rockchip_rk3368_cru) = {
  556. .name = "rockchip_rk3368_cru",
  557. .id = UCLASS_CLK,
  558. .of_match = rk3368_clk_ids,
  559. .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
  560. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  561. .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
  562. #endif
  563. .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
  564. .ops = &rk3368_clk_ops,
  565. .bind = rk3368_clk_bind,
  566. .probe = rk3368_clk_probe,
  567. };