clk_rk3328.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <bitfield.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <syscon.h>
  11. #include <asm/arch-rockchip/clock.h>
  12. #include <asm/arch-rockchip/cru_rk3328.h>
  13. #include <asm/arch-rockchip/hardware.h>
  14. #include <asm/arch-rockchip/grf_rk3328.h>
  15. #include <asm/io.h>
  16. #include <dm/lists.h>
  17. #include <dt-bindings/clock/rk3328-cru.h>
  18. struct pll_div {
  19. u32 refdiv;
  20. u32 fbdiv;
  21. u32 postdiv1;
  22. u32 postdiv2;
  23. u32 frac;
  24. };
  25. #define RATE_TO_DIV(input_rate, output_rate) \
  26. ((input_rate) / (output_rate) - 1);
  27. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  28. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  29. .refdiv = _refdiv,\
  30. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  31. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  32. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
  33. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
  34. static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
  35. static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
  36. static const struct pll_div *apll_cfgs[] = {
  37. [APLL_816_MHZ] = &apll_816_cfg,
  38. [APLL_600_MHZ] = &apll_600_cfg,
  39. };
  40. enum {
  41. /* PLL_CON0 */
  42. PLL_POSTDIV1_SHIFT = 12,
  43. PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
  44. PLL_FBDIV_SHIFT = 0,
  45. PLL_FBDIV_MASK = 0xfff,
  46. /* PLL_CON1 */
  47. PLL_DSMPD_SHIFT = 12,
  48. PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
  49. PLL_INTEGER_MODE = 1,
  50. PLL_LOCK_STATUS_SHIFT = 10,
  51. PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
  52. PLL_POSTDIV2_SHIFT = 6,
  53. PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
  54. PLL_REFDIV_SHIFT = 0,
  55. PLL_REFDIV_MASK = 0x3f,
  56. /* PLL_CON2 */
  57. PLL_FRACDIV_SHIFT = 0,
  58. PLL_FRACDIV_MASK = 0xffffff,
  59. /* MODE_CON */
  60. APLL_MODE_SHIFT = 0,
  61. NPLL_MODE_SHIFT = 1,
  62. DPLL_MODE_SHIFT = 4,
  63. CPLL_MODE_SHIFT = 8,
  64. GPLL_MODE_SHIFT = 12,
  65. PLL_MODE_SLOW = 0,
  66. PLL_MODE_NORM,
  67. /* CLKSEL_CON0 */
  68. CLK_CORE_PLL_SEL_APLL = 0,
  69. CLK_CORE_PLL_SEL_GPLL,
  70. CLK_CORE_PLL_SEL_DPLL,
  71. CLK_CORE_PLL_SEL_NPLL,
  72. CLK_CORE_PLL_SEL_SHIFT = 6,
  73. CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
  74. CLK_CORE_DIV_SHIFT = 0,
  75. CLK_CORE_DIV_MASK = 0x1f,
  76. /* CLKSEL_CON1 */
  77. ACLKM_CORE_DIV_SHIFT = 4,
  78. ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
  79. PCLK_DBG_DIV_SHIFT = 0,
  80. PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
  81. /* CLKSEL_CON27 */
  82. GMAC2IO_PLL_SEL_SHIFT = 7,
  83. GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
  84. GMAC2IO_PLL_SEL_CPLL = 0,
  85. GMAC2IO_PLL_SEL_GPLL = 1,
  86. GMAC2IO_CLK_DIV_MASK = 0x1f,
  87. GMAC2IO_CLK_DIV_SHIFT = 0,
  88. /* CLKSEL_CON28 */
  89. ACLK_PERIHP_PLL_SEL_CPLL = 0,
  90. ACLK_PERIHP_PLL_SEL_GPLL,
  91. ACLK_PERIHP_PLL_SEL_HDMIPHY,
  92. ACLK_PERIHP_PLL_SEL_SHIFT = 6,
  93. ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
  94. ACLK_PERIHP_DIV_CON_SHIFT = 0,
  95. ACLK_PERIHP_DIV_CON_MASK = 0x1f,
  96. /* CLKSEL_CON29 */
  97. PCLK_PERIHP_DIV_CON_SHIFT = 4,
  98. PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
  99. HCLK_PERIHP_DIV_CON_SHIFT = 0,
  100. HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
  101. /* CLKSEL_CON22 */
  102. CLK_TSADC_DIV_CON_SHIFT = 0,
  103. CLK_TSADC_DIV_CON_MASK = 0x3ff,
  104. /* CLKSEL_CON23 */
  105. CLK_SARADC_DIV_CON_SHIFT = 0,
  106. CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
  107. CLK_SARADC_DIV_CON_WIDTH = 10,
  108. /* CLKSEL_CON24 */
  109. CLK_PWM_PLL_SEL_CPLL = 0,
  110. CLK_PWM_PLL_SEL_GPLL,
  111. CLK_PWM_PLL_SEL_SHIFT = 15,
  112. CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
  113. CLK_PWM_DIV_CON_SHIFT = 8,
  114. CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
  115. CLK_SPI_PLL_SEL_CPLL = 0,
  116. CLK_SPI_PLL_SEL_GPLL,
  117. CLK_SPI_PLL_SEL_SHIFT = 7,
  118. CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
  119. CLK_SPI_DIV_CON_SHIFT = 0,
  120. CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
  121. /* CLKSEL_CON30 */
  122. CLK_SDMMC_PLL_SEL_CPLL = 0,
  123. CLK_SDMMC_PLL_SEL_GPLL,
  124. CLK_SDMMC_PLL_SEL_24M,
  125. CLK_SDMMC_PLL_SEL_USBPHY,
  126. CLK_SDMMC_PLL_SHIFT = 8,
  127. CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
  128. CLK_SDMMC_DIV_CON_SHIFT = 0,
  129. CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
  130. /* CLKSEL_CON32 */
  131. CLK_EMMC_PLL_SEL_CPLL = 0,
  132. CLK_EMMC_PLL_SEL_GPLL,
  133. CLK_EMMC_PLL_SEL_24M,
  134. CLK_EMMC_PLL_SEL_USBPHY,
  135. CLK_EMMC_PLL_SHIFT = 8,
  136. CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
  137. CLK_EMMC_DIV_CON_SHIFT = 0,
  138. CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
  139. /* CLKSEL_CON34 */
  140. CLK_I2C_PLL_SEL_CPLL = 0,
  141. CLK_I2C_PLL_SEL_GPLL,
  142. CLK_I2C_DIV_CON_MASK = 0x7f,
  143. CLK_I2C_PLL_SEL_MASK = 1,
  144. CLK_I2C1_PLL_SEL_SHIFT = 15,
  145. CLK_I2C1_DIV_CON_SHIFT = 8,
  146. CLK_I2C0_PLL_SEL_SHIFT = 7,
  147. CLK_I2C0_DIV_CON_SHIFT = 0,
  148. /* CLKSEL_CON35 */
  149. CLK_I2C3_PLL_SEL_SHIFT = 15,
  150. CLK_I2C3_DIV_CON_SHIFT = 8,
  151. CLK_I2C2_PLL_SEL_SHIFT = 7,
  152. CLK_I2C2_DIV_CON_SHIFT = 0,
  153. };
  154. #define VCO_MAX_KHZ (3200 * (MHz / KHz))
  155. #define VCO_MIN_KHZ (800 * (MHz / KHz))
  156. #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
  157. #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
  158. /*
  159. * the div restructions of pll in integer mode, these are defined in
  160. * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
  161. */
  162. #define PLL_DIV_MIN 16
  163. #define PLL_DIV_MAX 3200
  164. /*
  165. * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
  166. * Formulas also embedded within the Fractional PLL Verilog model:
  167. * If DSMPD = 1 (DSM is disabled, "integer mode")
  168. * FOUTVCO = FREF / REFDIV * FBDIV
  169. * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
  170. * Where:
  171. * FOUTVCO = Fractional PLL non-divided output frequency
  172. * FOUTPOSTDIV = Fractional PLL divided output frequency
  173. * (output of second post divider)
  174. * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
  175. * REFDIV = Fractional PLL input reference clock divider
  176. * FBDIV = Integer value programmed into feedback divide
  177. *
  178. */
  179. static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
  180. const struct pll_div *div)
  181. {
  182. u32 *pll_con;
  183. u32 mode_shift, mode_mask;
  184. pll_con = NULL;
  185. mode_shift = 0;
  186. switch (clk_id) {
  187. case CLK_ARM:
  188. pll_con = cru->apll_con;
  189. mode_shift = APLL_MODE_SHIFT;
  190. break;
  191. case CLK_DDR:
  192. pll_con = cru->dpll_con;
  193. mode_shift = DPLL_MODE_SHIFT;
  194. break;
  195. case CLK_CODEC:
  196. pll_con = cru->cpll_con;
  197. mode_shift = CPLL_MODE_SHIFT;
  198. break;
  199. case CLK_GENERAL:
  200. pll_con = cru->gpll_con;
  201. mode_shift = GPLL_MODE_SHIFT;
  202. break;
  203. case CLK_NEW:
  204. pll_con = cru->npll_con;
  205. mode_shift = NPLL_MODE_SHIFT;
  206. break;
  207. default:
  208. break;
  209. }
  210. mode_mask = 1 << mode_shift;
  211. /* All 8 PLLs have same VCO and output frequency range restrictions. */
  212. u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
  213. u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
  214. debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
  215. postdiv2=%d, vco=%u khz, output=%u khz\n",
  216. pll_con, div->fbdiv, div->refdiv, div->postdiv1,
  217. div->postdiv2, vco_khz, output_khz);
  218. assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
  219. output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
  220. div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
  221. /*
  222. * When power on or changing PLL setting,
  223. * we must force PLL into slow mode to ensure output stable clock.
  224. */
  225. rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
  226. /* use integer mode */
  227. rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
  228. PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
  229. rk_clrsetreg(&pll_con[0],
  230. PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
  231. (div->fbdiv << PLL_FBDIV_SHIFT) |
  232. (div->postdiv1 << PLL_POSTDIV1_SHIFT));
  233. rk_clrsetreg(&pll_con[1],
  234. PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  235. (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
  236. (div->refdiv << PLL_REFDIV_SHIFT));
  237. /* waiting for pll lock */
  238. while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
  239. udelay(1);
  240. /* pll enter normal mode */
  241. rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
  242. }
  243. static void rkclk_init(struct rk3328_cru *cru)
  244. {
  245. u32 aclk_div;
  246. u32 hclk_div;
  247. u32 pclk_div;
  248. /* configure gpll cpll */
  249. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  250. rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
  251. /* configure perihp aclk, hclk, pclk */
  252. aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
  253. hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
  254. pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
  255. rk_clrsetreg(&cru->clksel_con[28],
  256. ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
  257. ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
  258. aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
  259. rk_clrsetreg(&cru->clksel_con[29],
  260. PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
  261. pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
  262. hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
  263. }
  264. void rk3328_configure_cpu(struct rk3328_cru *cru,
  265. enum apll_frequencies apll_freq)
  266. {
  267. u32 clk_core_div;
  268. u32 aclkm_div;
  269. u32 pclk_dbg_div;
  270. rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
  271. clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
  272. aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
  273. pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
  274. rk_clrsetreg(&cru->clksel_con[0],
  275. CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
  276. CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
  277. clk_core_div << CLK_CORE_DIV_SHIFT);
  278. rk_clrsetreg(&cru->clksel_con[1],
  279. PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
  280. pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
  281. aclkm_div << ACLKM_CORE_DIV_SHIFT);
  282. }
  283. static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
  284. {
  285. u32 div, con;
  286. switch (clk_id) {
  287. case SCLK_I2C0:
  288. con = readl(&cru->clksel_con[34]);
  289. div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  290. break;
  291. case SCLK_I2C1:
  292. con = readl(&cru->clksel_con[34]);
  293. div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  294. break;
  295. case SCLK_I2C2:
  296. con = readl(&cru->clksel_con[35]);
  297. div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  298. break;
  299. case SCLK_I2C3:
  300. con = readl(&cru->clksel_con[35]);
  301. div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  302. break;
  303. default:
  304. printf("do not support this i2c bus\n");
  305. return -EINVAL;
  306. }
  307. return DIV_TO_RATE(GPLL_HZ, div);
  308. }
  309. static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
  310. {
  311. int src_clk_div;
  312. src_clk_div = GPLL_HZ / hz;
  313. assert(src_clk_div - 1 < 127);
  314. switch (clk_id) {
  315. case SCLK_I2C0:
  316. rk_clrsetreg(&cru->clksel_con[34],
  317. CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
  318. CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
  319. (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
  320. CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
  321. break;
  322. case SCLK_I2C1:
  323. rk_clrsetreg(&cru->clksel_con[34],
  324. CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
  325. CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
  326. (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
  327. CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
  328. break;
  329. case SCLK_I2C2:
  330. rk_clrsetreg(&cru->clksel_con[35],
  331. CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
  332. CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
  333. (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
  334. CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
  335. break;
  336. case SCLK_I2C3:
  337. rk_clrsetreg(&cru->clksel_con[35],
  338. CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
  339. CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
  340. (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
  341. CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
  342. break;
  343. default:
  344. printf("do not support this i2c bus\n");
  345. return -EINVAL;
  346. }
  347. return DIV_TO_RATE(GPLL_HZ, src_clk_div);
  348. }
  349. static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
  350. {
  351. struct rk3328_grf_regs *grf;
  352. ulong ret;
  353. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  354. /*
  355. * The RGMII CLK can be derived either from an external "clkin"
  356. * or can be generated from internally by a divider from SCLK_MAC.
  357. */
  358. if (readl(&grf->mac_con[1]) & BIT(10) &&
  359. readl(&grf->soc_con[4]) & BIT(14)) {
  360. /* An external clock will always generate the right rate... */
  361. ret = rate;
  362. } else {
  363. u32 con = readl(&cru->clksel_con[27]);
  364. ulong pll_rate;
  365. u8 div;
  366. if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
  367. pll_rate = GPLL_HZ;
  368. else
  369. pll_rate = CPLL_HZ;
  370. div = DIV_ROUND_UP(pll_rate, rate) - 1;
  371. if (div <= 0x1f)
  372. rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
  373. div << GMAC2IO_CLK_DIV_SHIFT);
  374. else
  375. debug("Unsupported div for gmac:%d\n", div);
  376. return DIV_TO_RATE(pll_rate, div);
  377. }
  378. return ret;
  379. }
  380. static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
  381. {
  382. u32 div, con, con_id;
  383. switch (clk_id) {
  384. case HCLK_SDMMC:
  385. case SCLK_SDMMC:
  386. con_id = 30;
  387. break;
  388. case HCLK_EMMC:
  389. case SCLK_EMMC:
  390. con_id = 32;
  391. break;
  392. default:
  393. return -EINVAL;
  394. }
  395. con = readl(&cru->clksel_con[con_id]);
  396. div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
  397. if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
  398. == CLK_EMMC_PLL_SEL_24M)
  399. return DIV_TO_RATE(OSC_HZ, div) / 2;
  400. else
  401. return DIV_TO_RATE(GPLL_HZ, div) / 2;
  402. }
  403. static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
  404. ulong clk_id, ulong set_rate)
  405. {
  406. int src_clk_div;
  407. u32 con_id;
  408. switch (clk_id) {
  409. case HCLK_SDMMC:
  410. case SCLK_SDMMC:
  411. con_id = 30;
  412. break;
  413. case HCLK_EMMC:
  414. case SCLK_EMMC:
  415. con_id = 32;
  416. break;
  417. default:
  418. return -EINVAL;
  419. }
  420. /* Select clk_sdmmc/emmc source from GPLL by default */
  421. /* mmc clock defaulg div 2 internal, need provide double in cru */
  422. src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
  423. if (src_clk_div > 127) {
  424. /* use 24MHz source for 400KHz clock */
  425. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
  426. rk_clrsetreg(&cru->clksel_con[con_id],
  427. CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
  428. CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
  429. (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
  430. } else {
  431. rk_clrsetreg(&cru->clksel_con[con_id],
  432. CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
  433. CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
  434. (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
  435. }
  436. return rk3328_mmc_get_clk(cru, clk_id);
  437. }
  438. static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
  439. {
  440. u32 div, con;
  441. con = readl(&cru->clksel_con[24]);
  442. div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
  443. return DIV_TO_RATE(GPLL_HZ, div);
  444. }
  445. static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
  446. {
  447. u32 div = GPLL_HZ / hz;
  448. rk_clrsetreg(&cru->clksel_con[24],
  449. CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
  450. CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
  451. (div - 1) << CLK_PWM_DIV_CON_SHIFT);
  452. return DIV_TO_RATE(GPLL_HZ, div);
  453. }
  454. static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
  455. {
  456. u32 div, val;
  457. val = readl(&cru->clksel_con[23]);
  458. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  459. CLK_SARADC_DIV_CON_WIDTH);
  460. return DIV_TO_RATE(OSC_HZ, div);
  461. }
  462. static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
  463. {
  464. int src_clk_div;
  465. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  466. assert(src_clk_div < 128);
  467. rk_clrsetreg(&cru->clksel_con[23],
  468. CLK_SARADC_DIV_CON_MASK,
  469. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  470. return rk3328_saradc_get_clk(cru);
  471. }
  472. static ulong rk3328_clk_get_rate(struct clk *clk)
  473. {
  474. struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
  475. ulong rate = 0;
  476. switch (clk->id) {
  477. case 0 ... 29:
  478. return 0;
  479. case HCLK_SDMMC:
  480. case HCLK_EMMC:
  481. case SCLK_SDMMC:
  482. case SCLK_EMMC:
  483. rate = rk3328_mmc_get_clk(priv->cru, clk->id);
  484. break;
  485. case SCLK_I2C0:
  486. case SCLK_I2C1:
  487. case SCLK_I2C2:
  488. case SCLK_I2C3:
  489. rate = rk3328_i2c_get_clk(priv->cru, clk->id);
  490. break;
  491. case SCLK_PWM:
  492. rate = rk3328_pwm_get_clk(priv->cru);
  493. break;
  494. case SCLK_SARADC:
  495. rate = rk3328_saradc_get_clk(priv->cru);
  496. break;
  497. default:
  498. return -ENOENT;
  499. }
  500. return rate;
  501. }
  502. static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
  503. {
  504. struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
  505. ulong ret = 0;
  506. switch (clk->id) {
  507. case 0 ... 29:
  508. return 0;
  509. case HCLK_SDMMC:
  510. case HCLK_EMMC:
  511. case SCLK_SDMMC:
  512. case SCLK_EMMC:
  513. ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
  514. break;
  515. case SCLK_I2C0:
  516. case SCLK_I2C1:
  517. case SCLK_I2C2:
  518. case SCLK_I2C3:
  519. ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
  520. break;
  521. case SCLK_MAC2IO:
  522. ret = rk3328_gmac2io_set_clk(priv->cru, rate);
  523. break;
  524. case SCLK_PWM:
  525. ret = rk3328_pwm_set_clk(priv->cru, rate);
  526. break;
  527. case SCLK_SARADC:
  528. ret = rk3328_saradc_set_clk(priv->cru, rate);
  529. break;
  530. case DCLK_LCDC:
  531. case SCLK_PDM:
  532. case SCLK_RTC32K:
  533. case SCLK_UART0:
  534. case SCLK_UART1:
  535. case SCLK_UART2:
  536. case SCLK_SDIO:
  537. case SCLK_TSP:
  538. case SCLK_WIFI:
  539. case ACLK_BUS_PRE:
  540. case HCLK_BUS_PRE:
  541. case PCLK_BUS_PRE:
  542. case ACLK_PERI_PRE:
  543. case HCLK_PERI:
  544. case PCLK_PERI:
  545. case ACLK_VIO_PRE:
  546. case HCLK_VIO_PRE:
  547. case ACLK_RGA_PRE:
  548. case SCLK_RGA:
  549. case ACLK_VOP_PRE:
  550. case ACLK_RKVDEC_PRE:
  551. case ACLK_RKVENC:
  552. case ACLK_VPU_PRE:
  553. case SCLK_VDEC_CABAC:
  554. case SCLK_VDEC_CORE:
  555. case SCLK_VENC_CORE:
  556. case SCLK_VENC_DSP:
  557. case SCLK_EFUSE:
  558. case PCLK_DDR:
  559. case ACLK_GMAC:
  560. case PCLK_GMAC:
  561. case SCLK_USB3OTG_SUSPEND:
  562. return 0;
  563. default:
  564. return -ENOENT;
  565. }
  566. return ret;
  567. }
  568. static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
  569. {
  570. struct rk3328_grf_regs *grf;
  571. const char *clock_output_name;
  572. int ret;
  573. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  574. /*
  575. * If the requested parent is in the same clock-controller and the id
  576. * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
  577. */
  578. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
  579. debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
  580. rk_clrreg(&grf->mac_con[1], BIT(10));
  581. return 0;
  582. }
  583. /*
  584. * Otherwise, we need to check the clock-output-names of the
  585. * requested parent to see if the requested id is "gmac_clkin".
  586. */
  587. ret = dev_read_string_index(parent->dev, "clock-output-names",
  588. parent->id, &clock_output_name);
  589. if (ret < 0)
  590. return -ENODATA;
  591. /* If this is "gmac_clkin", switch to the external clock input */
  592. if (!strcmp(clock_output_name, "gmac_clkin")) {
  593. debug("%s: switching RGMII to CLKIN\n", __func__);
  594. rk_setreg(&grf->mac_con[1], BIT(10));
  595. return 0;
  596. }
  597. return -EINVAL;
  598. }
  599. static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
  600. {
  601. struct rk3328_grf_regs *grf;
  602. const char *clock_output_name;
  603. int ret;
  604. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  605. /*
  606. * If the requested parent is in the same clock-controller and the id
  607. * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
  608. */
  609. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
  610. debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
  611. rk_clrreg(&grf->soc_con[4], BIT(14));
  612. return 0;
  613. }
  614. /*
  615. * Otherwise, we need to check the clock-output-names of the
  616. * requested parent to see if the requested id is "gmac_clkin".
  617. */
  618. ret = dev_read_string_index(parent->dev, "clock-output-names",
  619. parent->id, &clock_output_name);
  620. if (ret < 0)
  621. return -ENODATA;
  622. /* If this is "gmac_clkin", switch to the external clock input */
  623. if (!strcmp(clock_output_name, "gmac_clkin")) {
  624. debug("%s: switching RGMII to CLKIN\n", __func__);
  625. rk_setreg(&grf->soc_con[4], BIT(14));
  626. return 0;
  627. }
  628. return -EINVAL;
  629. }
  630. static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
  631. {
  632. switch (clk->id) {
  633. case SCLK_MAC2IO:
  634. return rk3328_gmac2io_set_parent(clk, parent);
  635. case SCLK_MAC2IO_EXT:
  636. return rk3328_gmac2io_ext_set_parent(clk, parent);
  637. case DCLK_LCDC:
  638. case SCLK_PDM:
  639. case SCLK_RTC32K:
  640. case SCLK_UART0:
  641. case SCLK_UART1:
  642. case SCLK_UART2:
  643. return 0;
  644. }
  645. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  646. return -ENOENT;
  647. }
  648. static struct clk_ops rk3328_clk_ops = {
  649. .get_rate = rk3328_clk_get_rate,
  650. .set_rate = rk3328_clk_set_rate,
  651. .set_parent = rk3328_clk_set_parent,
  652. };
  653. static int rk3328_clk_probe(struct udevice *dev)
  654. {
  655. struct rk3328_clk_priv *priv = dev_get_priv(dev);
  656. rkclk_init(priv->cru);
  657. return 0;
  658. }
  659. static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
  660. {
  661. struct rk3328_clk_priv *priv = dev_get_priv(dev);
  662. priv->cru = dev_read_addr_ptr(dev);
  663. return 0;
  664. }
  665. static int rk3328_clk_bind(struct udevice *dev)
  666. {
  667. int ret;
  668. struct udevice *sys_child;
  669. struct sysreset_reg *priv;
  670. /* The reset driver does not have a device node, so bind it here */
  671. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  672. &sys_child);
  673. if (ret) {
  674. debug("Warning: No sysreset driver: ret=%d\n", ret);
  675. } else {
  676. priv = malloc(sizeof(struct sysreset_reg));
  677. priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
  678. glb_srst_fst_value);
  679. priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
  680. glb_srst_snd_value);
  681. sys_child->priv = priv;
  682. }
  683. #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
  684. ret = offsetof(struct rk3328_cru, softrst_con[0]);
  685. ret = rockchip_reset_bind(dev, ret, 12);
  686. if (ret)
  687. debug("Warning: software reset driver bind faile\n");
  688. #endif
  689. return ret;
  690. }
  691. static const struct udevice_id rk3328_clk_ids[] = {
  692. { .compatible = "rockchip,rk3328-cru" },
  693. { }
  694. };
  695. U_BOOT_DRIVER(rockchip_rk3328_cru) = {
  696. .name = "rockchip_rk3328_cru",
  697. .id = UCLASS_CLK,
  698. .of_match = rk3328_clk_ids,
  699. .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
  700. .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
  701. .ops = &rk3328_clk_ops,
  702. .bind = rk3328_clk_bind,
  703. .probe = rk3328_clk_probe,
  704. };