clk_rk3188.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <dt-structs.h>
  10. #include <errno.h>
  11. #include <mapmem.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/clock.h>
  15. #include <asm/arch-rockchip/cru_rk3188.h>
  16. #include <asm/arch-rockchip/grf_rk3188.h>
  17. #include <asm/arch-rockchip/hardware.h>
  18. #include <dt-bindings/clock/rk3188-cru.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/lists.h>
  21. #include <dm/uclass-internal.h>
  22. #include <linux/log2.h>
  23. enum rk3188_clk_type {
  24. RK3188_CRU,
  25. RK3188A_CRU,
  26. };
  27. struct rk3188_clk_plat {
  28. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  29. struct dtd_rockchip_rk3188_cru dtd;
  30. #endif
  31. };
  32. struct pll_div {
  33. u32 nr;
  34. u32 nf;
  35. u32 no;
  36. };
  37. enum {
  38. VCO_MAX_HZ = 2200U * 1000000,
  39. VCO_MIN_HZ = 440 * 1000000,
  40. OUTPUT_MAX_HZ = 2200U * 1000000,
  41. OUTPUT_MIN_HZ = 30 * 1000000,
  42. FREF_MAX_HZ = 2200U * 1000000,
  43. FREF_MIN_HZ = 30 * 1000,
  44. };
  45. enum {
  46. /* PLL CON0 */
  47. PLL_OD_MASK = 0x0f,
  48. /* PLL CON1 */
  49. PLL_NF_MASK = 0x1fff,
  50. /* PLL CON2 */
  51. PLL_BWADJ_MASK = 0x0fff,
  52. /* PLL CON3 */
  53. PLL_RESET_SHIFT = 5,
  54. /* GRF_SOC_STATUS0 */
  55. SOCSTS_DPLL_LOCK = 1 << 5,
  56. SOCSTS_APLL_LOCK = 1 << 6,
  57. SOCSTS_CPLL_LOCK = 1 << 7,
  58. SOCSTS_GPLL_LOCK = 1 << 8,
  59. };
  60. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  61. #define PLL_DIVISORS(hz, _nr, _no) {\
  62. .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
  63. _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  64. (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
  65. "divisors on line " __stringify(__LINE__));
  66. /* Keep divisors as low as possible to reduce jitter and power usage */
  67. #ifdef CONFIG_SPL_BUILD
  68. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
  69. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
  70. #endif
  71. static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
  72. const struct pll_div *div, bool has_bwadj)
  73. {
  74. int pll_id = rk_pll_id(clk_id);
  75. struct rk3188_pll *pll = &cru->pll[pll_id];
  76. /* All PLLs have same VCO and output frequency range restrictions. */
  77. uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  78. uint output_hz = vco_hz / div->no;
  79. debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  80. (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  81. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  82. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
  83. (div->no == 1 || !(div->no % 2)));
  84. /* enter reset */
  85. rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  86. rk_clrsetreg(&pll->con0,
  87. CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
  88. ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
  89. rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
  90. if (has_bwadj)
  91. rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
  92. udelay(10);
  93. /* return from reset */
  94. rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  95. return 0;
  96. }
  97. static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
  98. unsigned int hz, bool has_bwadj)
  99. {
  100. static const struct pll_div dpll_cfg[] = {
  101. {.nf = 75, .nr = 1, .no = 6},
  102. {.nf = 400, .nr = 9, .no = 2},
  103. {.nf = 500, .nr = 9, .no = 2},
  104. {.nf = 100, .nr = 3, .no = 1},
  105. };
  106. int cfg;
  107. switch (hz) {
  108. case 300000000:
  109. cfg = 0;
  110. break;
  111. case 533000000: /* actually 533.3P MHz */
  112. cfg = 1;
  113. break;
  114. case 666000000: /* actually 666.6P MHz */
  115. cfg = 2;
  116. break;
  117. case 800000000:
  118. cfg = 3;
  119. break;
  120. default:
  121. debug("Unsupported SDRAM frequency");
  122. return -EINVAL;
  123. }
  124. /* pll enter slow-mode */
  125. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
  126. DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
  127. rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
  128. /* wait for pll lock */
  129. while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
  130. udelay(1);
  131. /* PLL enter normal-mode */
  132. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
  133. DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
  134. return 0;
  135. }
  136. static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
  137. unsigned int hz, bool has_bwadj)
  138. {
  139. static const struct pll_div apll_cfg[] = {
  140. {.nf = 50, .nr = 1, .no = 2},
  141. {.nf = 67, .nr = 1, .no = 1},
  142. };
  143. int div_core_peri, div_aclk_core, cfg;
  144. /*
  145. * We support two possible frequencies, the safe 600MHz
  146. * which will work with default pmic settings and will
  147. * be set in SPL to get away from the 24MHz default and
  148. * the maximum of 1.6Ghz, which boards can set if they
  149. * were able to get pmic support for it.
  150. */
  151. switch (hz) {
  152. case APLL_SAFE_HZ:
  153. cfg = 0;
  154. div_core_peri = 1;
  155. div_aclk_core = 3;
  156. break;
  157. case APLL_HZ:
  158. cfg = 1;
  159. div_core_peri = 2;
  160. div_aclk_core = 3;
  161. break;
  162. default:
  163. debug("Unsupported ARMCLK frequency");
  164. return -EINVAL;
  165. }
  166. /* pll enter slow-mode */
  167. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
  168. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  169. rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
  170. /* waiting for pll lock */
  171. while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
  172. udelay(1);
  173. /* Set divider for peripherals attached to the cpu core. */
  174. rk_clrsetreg(&cru->cru_clksel_con[0],
  175. CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
  176. div_core_peri << CORE_PERI_DIV_SHIFT);
  177. /* set up dependent divisor for aclk_core */
  178. rk_clrsetreg(&cru->cru_clksel_con[1],
  179. CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
  180. div_aclk_core << CORE_ACLK_DIV_SHIFT);
  181. /* PLL enter normal-mode */
  182. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
  183. APLL_MODE_NORMAL << APLL_MODE_SHIFT);
  184. return hz;
  185. }
  186. /* Get pll rate by id */
  187. static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
  188. enum rk_clk_id clk_id)
  189. {
  190. uint32_t nr, no, nf;
  191. uint32_t con;
  192. int pll_id = rk_pll_id(clk_id);
  193. struct rk3188_pll *pll = &cru->pll[pll_id];
  194. static u8 clk_shift[CLK_COUNT] = {
  195. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
  196. GPLL_MODE_SHIFT
  197. };
  198. uint shift;
  199. con = readl(&cru->cru_mode_con);
  200. shift = clk_shift[clk_id];
  201. switch ((con >> shift) & APLL_MODE_MASK) {
  202. case APLL_MODE_SLOW:
  203. return OSC_HZ;
  204. case APLL_MODE_NORMAL:
  205. /* normal mode */
  206. con = readl(&pll->con0);
  207. no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
  208. nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
  209. con = readl(&pll->con1);
  210. nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
  211. return (24 * nf / (nr * no)) * 1000000;
  212. case APLL_MODE_DEEP:
  213. default:
  214. return 32768;
  215. }
  216. }
  217. static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
  218. int periph)
  219. {
  220. uint div;
  221. u32 con;
  222. switch (periph) {
  223. case HCLK_EMMC:
  224. case SCLK_EMMC:
  225. con = readl(&cru->cru_clksel_con[12]);
  226. div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
  227. break;
  228. case HCLK_SDMMC:
  229. case SCLK_SDMMC:
  230. con = readl(&cru->cru_clksel_con[11]);
  231. div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
  232. break;
  233. case HCLK_SDIO:
  234. case SCLK_SDIO:
  235. con = readl(&cru->cru_clksel_con[12]);
  236. div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
  237. break;
  238. default:
  239. return -EINVAL;
  240. }
  241. return DIV_TO_RATE(gclk_rate, div) / 2;
  242. }
  243. static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
  244. int periph, uint freq)
  245. {
  246. int src_clk_div;
  247. debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
  248. /* mmc clock defaulg div 2 internal, need provide double in cru */
  249. src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
  250. assert(src_clk_div <= 0x3f);
  251. switch (periph) {
  252. case HCLK_EMMC:
  253. case SCLK_EMMC:
  254. rk_clrsetreg(&cru->cru_clksel_con[12],
  255. EMMC_DIV_MASK << EMMC_DIV_SHIFT,
  256. src_clk_div << EMMC_DIV_SHIFT);
  257. break;
  258. case HCLK_SDMMC:
  259. case SCLK_SDMMC:
  260. rk_clrsetreg(&cru->cru_clksel_con[11],
  261. MMC0_DIV_MASK << MMC0_DIV_SHIFT,
  262. src_clk_div << MMC0_DIV_SHIFT);
  263. break;
  264. case HCLK_SDIO:
  265. case SCLK_SDIO:
  266. rk_clrsetreg(&cru->cru_clksel_con[12],
  267. SDIO_DIV_MASK << SDIO_DIV_SHIFT,
  268. src_clk_div << SDIO_DIV_SHIFT);
  269. break;
  270. default:
  271. return -EINVAL;
  272. }
  273. return rockchip_mmc_get_clk(cru, gclk_rate, periph);
  274. }
  275. static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
  276. int periph)
  277. {
  278. uint div;
  279. u32 con;
  280. switch (periph) {
  281. case SCLK_SPI0:
  282. con = readl(&cru->cru_clksel_con[25]);
  283. div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
  284. break;
  285. case SCLK_SPI1:
  286. con = readl(&cru->cru_clksel_con[25]);
  287. div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
  288. break;
  289. default:
  290. return -EINVAL;
  291. }
  292. return DIV_TO_RATE(gclk_rate, div);
  293. }
  294. static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
  295. int periph, uint freq)
  296. {
  297. int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
  298. assert(src_clk_div < 128);
  299. switch (periph) {
  300. case SCLK_SPI0:
  301. assert(src_clk_div <= SPI0_DIV_MASK);
  302. rk_clrsetreg(&cru->cru_clksel_con[25],
  303. SPI0_DIV_MASK << SPI0_DIV_SHIFT,
  304. src_clk_div << SPI0_DIV_SHIFT);
  305. break;
  306. case SCLK_SPI1:
  307. assert(src_clk_div <= SPI1_DIV_MASK);
  308. rk_clrsetreg(&cru->cru_clksel_con[25],
  309. SPI1_DIV_MASK << SPI1_DIV_SHIFT,
  310. src_clk_div << SPI1_DIV_SHIFT);
  311. break;
  312. default:
  313. return -EINVAL;
  314. }
  315. return rockchip_spi_get_clk(cru, gclk_rate, periph);
  316. }
  317. #ifdef CONFIG_SPL_BUILD
  318. static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
  319. bool has_bwadj)
  320. {
  321. u32 aclk_div, hclk_div, pclk_div, h2p_div;
  322. /* pll enter slow-mode */
  323. rk_clrsetreg(&cru->cru_mode_con,
  324. GPLL_MODE_MASK << GPLL_MODE_SHIFT |
  325. CPLL_MODE_MASK << CPLL_MODE_SHIFT,
  326. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  327. CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
  328. /* init pll */
  329. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
  330. rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
  331. /* waiting for pll lock */
  332. while ((readl(&grf->soc_status0) &
  333. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
  334. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
  335. udelay(1);
  336. /*
  337. * cpu clock pll source selection and
  338. * reparent aclk_cpu_pre from apll to gpll
  339. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  340. */
  341. aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
  342. assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  343. rk_clrsetreg(&cru->cru_clksel_con[0],
  344. CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
  345. A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
  346. CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
  347. aclk_div << A9_CPU_DIV_SHIFT);
  348. hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
  349. assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
  350. pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
  351. assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
  352. h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
  353. assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
  354. rk_clrsetreg(&cru->cru_clksel_con[1],
  355. AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
  356. CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
  357. CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
  358. h2p_div << AHB2APB_DIV_SHIFT |
  359. pclk_div << CPU_PCLK_DIV_SHIFT |
  360. hclk_div << CPU_HCLK_DIV_SHIFT);
  361. /*
  362. * peri clock pll source selection and
  363. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  364. */
  365. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  366. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  367. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  368. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  369. PERI_ACLK_HZ && (hclk_div < 0x4));
  370. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  371. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  372. PERI_ACLK_HZ && (pclk_div < 0x4));
  373. rk_clrsetreg(&cru->cru_clksel_con[10],
  374. PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
  375. PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
  376. PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
  377. PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
  378. pclk_div << PERI_PCLK_DIV_SHIFT |
  379. hclk_div << PERI_HCLK_DIV_SHIFT |
  380. aclk_div << PERI_ACLK_DIV_SHIFT);
  381. /* PLL enter normal-mode */
  382. rk_clrsetreg(&cru->cru_mode_con,
  383. GPLL_MODE_MASK << GPLL_MODE_SHIFT |
  384. CPLL_MODE_MASK << CPLL_MODE_SHIFT,
  385. GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
  386. CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
  387. rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
  388. }
  389. #endif
  390. static ulong rk3188_clk_get_rate(struct clk *clk)
  391. {
  392. struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
  393. ulong new_rate, gclk_rate;
  394. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  395. switch (clk->id) {
  396. case 1 ... 4:
  397. new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
  398. break;
  399. case HCLK_EMMC:
  400. case HCLK_SDMMC:
  401. case HCLK_SDIO:
  402. case SCLK_EMMC:
  403. case SCLK_SDMMC:
  404. case SCLK_SDIO:
  405. new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
  406. clk->id);
  407. break;
  408. case SCLK_SPI0:
  409. case SCLK_SPI1:
  410. new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
  411. clk->id);
  412. break;
  413. case PCLK_I2C0:
  414. case PCLK_I2C1:
  415. case PCLK_I2C2:
  416. case PCLK_I2C3:
  417. case PCLK_I2C4:
  418. return gclk_rate;
  419. default:
  420. return -ENOENT;
  421. }
  422. return new_rate;
  423. }
  424. static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
  425. {
  426. struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
  427. struct rk3188_cru *cru = priv->cru;
  428. ulong new_rate;
  429. switch (clk->id) {
  430. case PLL_APLL:
  431. new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
  432. priv->has_bwadj);
  433. break;
  434. case CLK_DDR:
  435. new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
  436. priv->has_bwadj);
  437. break;
  438. case HCLK_EMMC:
  439. case HCLK_SDMMC:
  440. case HCLK_SDIO:
  441. case SCLK_EMMC:
  442. case SCLK_SDMMC:
  443. case SCLK_SDIO:
  444. new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
  445. clk->id, rate);
  446. break;
  447. case SCLK_SPI0:
  448. case SCLK_SPI1:
  449. new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
  450. clk->id, rate);
  451. break;
  452. default:
  453. return -ENOENT;
  454. }
  455. return new_rate;
  456. }
  457. static struct clk_ops rk3188_clk_ops = {
  458. .get_rate = rk3188_clk_get_rate,
  459. .set_rate = rk3188_clk_set_rate,
  460. };
  461. static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
  462. {
  463. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  464. struct rk3188_clk_priv *priv = dev_get_priv(dev);
  465. priv->cru = dev_read_addr_ptr(dev);
  466. #endif
  467. return 0;
  468. }
  469. static int rk3188_clk_probe(struct udevice *dev)
  470. {
  471. struct rk3188_clk_priv *priv = dev_get_priv(dev);
  472. enum rk3188_clk_type type = dev_get_driver_data(dev);
  473. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  474. if (IS_ERR(priv->grf))
  475. return PTR_ERR(priv->grf);
  476. priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
  477. #ifdef CONFIG_SPL_BUILD
  478. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  479. struct rk3188_clk_plat *plat = dev_get_platdata(dev);
  480. priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  481. #endif
  482. rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
  483. #endif
  484. return 0;
  485. }
  486. static int rk3188_clk_bind(struct udevice *dev)
  487. {
  488. int ret;
  489. struct udevice *sys_child;
  490. struct sysreset_reg *priv;
  491. /* The reset driver does not have a device node, so bind it here */
  492. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  493. &sys_child);
  494. if (ret) {
  495. debug("Warning: No sysreset driver: ret=%d\n", ret);
  496. } else {
  497. priv = malloc(sizeof(struct sysreset_reg));
  498. priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
  499. cru_glb_srst_fst_value);
  500. priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
  501. cru_glb_srst_snd_value);
  502. sys_child->priv = priv;
  503. }
  504. #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
  505. ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
  506. ret = rockchip_reset_bind(dev, ret, 9);
  507. if (ret)
  508. debug("Warning: software reset driver bind faile\n");
  509. #endif
  510. return 0;
  511. }
  512. static const struct udevice_id rk3188_clk_ids[] = {
  513. { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
  514. { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
  515. { }
  516. };
  517. U_BOOT_DRIVER(rockchip_rk3188_cru) = {
  518. .name = "rockchip_rk3188_cru",
  519. .id = UCLASS_CLK,
  520. .of_match = rk3188_clk_ids,
  521. .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
  522. .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
  523. .ops = &rk3188_clk_ops,
  524. .bind = rk3188_clk_bind,
  525. .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata,
  526. .probe = rk3188_clk_probe,
  527. };