clk_rk3128.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <syscon.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/clock.h>
  12. #include <asm/arch-rockchip/cru_rk3128.h>
  13. #include <asm/arch-rockchip/hardware.h>
  14. #include <bitfield.h>
  15. #include <dm/lists.h>
  16. #include <dt-bindings/clock/rk3128-cru.h>
  17. #include <linux/log2.h>
  18. enum {
  19. VCO_MAX_HZ = 2400U * 1000000,
  20. VCO_MIN_HZ = 600 * 1000000,
  21. OUTPUT_MAX_HZ = 2400U * 1000000,
  22. OUTPUT_MIN_HZ = 24 * 1000000,
  23. };
  24. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  25. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  26. .refdiv = _refdiv,\
  27. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  28. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  29. /* use integer mode*/
  30. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  31. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  32. static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
  33. const struct pll_div *div)
  34. {
  35. int pll_id = rk_pll_id(clk_id);
  36. struct rk3128_pll *pll = &cru->pll[pll_id];
  37. /* All PLLs have same VCO and output frequency range restrictions. */
  38. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  39. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  40. debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
  41. pll, div->fbdiv, div->refdiv, div->postdiv1,
  42. div->postdiv2, vco_hz, output_hz);
  43. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  44. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  45. /* use integer mode */
  46. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  47. /* Power down */
  48. rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
  49. rk_clrsetreg(&pll->con0,
  50. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  51. (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  52. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  53. (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  54. div->refdiv << PLL_REFDIV_SHIFT));
  55. /* Power Up */
  56. rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
  57. /* waiting for pll lock */
  58. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  59. udelay(1);
  60. return 0;
  61. }
  62. static int pll_para_config(u32 freq_hz, struct pll_div *div)
  63. {
  64. u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0;
  65. u32 postdiv1, postdiv2 = 1;
  66. u32 fref_khz;
  67. u32 diff_khz, best_diff_khz;
  68. const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
  69. const u32 max_postdiv1 = 7, max_postdiv2 = 7;
  70. u32 vco_khz;
  71. u32 freq_khz = freq_hz / 1000;
  72. if (!freq_hz) {
  73. printf("%s: the frequency can't be 0 Hz\n", __func__);
  74. return -1;
  75. }
  76. postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz);
  77. if (postdiv1 > max_postdiv1) {
  78. postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
  79. postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
  80. }
  81. vco_khz = freq_khz * postdiv1 * postdiv2;
  82. if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) ||
  83. postdiv2 > max_postdiv2) {
  84. printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
  85. __func__, freq_hz);
  86. return -1;
  87. }
  88. div->postdiv1 = postdiv1;
  89. div->postdiv2 = postdiv2;
  90. best_diff_khz = vco_khz;
  91. for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
  92. fref_khz = ref_khz / refdiv;
  93. fbdiv = vco_khz / fref_khz;
  94. if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
  95. continue;
  96. diff_khz = vco_khz - fbdiv * fref_khz;
  97. if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
  98. fbdiv++;
  99. diff_khz = fref_khz - diff_khz;
  100. }
  101. if (diff_khz >= best_diff_khz)
  102. continue;
  103. best_diff_khz = diff_khz;
  104. div->refdiv = refdiv;
  105. div->fbdiv = fbdiv;
  106. }
  107. if (best_diff_khz > 4 * (1000)) {
  108. printf("%s: Failed to match output frequency %u bestis %u Hz\n",
  109. __func__, freq_hz,
  110. best_diff_khz * 1000);
  111. return -1;
  112. }
  113. return 0;
  114. }
  115. static void rkclk_init(struct rk3128_cru *cru)
  116. {
  117. u32 aclk_div;
  118. u32 hclk_div;
  119. u32 pclk_div;
  120. /* pll enter slow-mode */
  121. rk_clrsetreg(&cru->cru_mode_con,
  122. GPLL_MODE_MASK | APLL_MODE_MASK,
  123. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  124. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  125. /* init pll */
  126. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  127. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  128. /*
  129. * select apll as cpu/core clock pll source and
  130. * set up dependent divisors for PERI and ACLK clocks.
  131. * core hz : apll = 1:1
  132. */
  133. aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
  134. assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
  135. pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
  136. assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
  137. rk_clrsetreg(&cru->cru_clksel_con[0],
  138. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  139. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  140. 0 << CORE_DIV_CON_SHIFT);
  141. rk_clrsetreg(&cru->cru_clksel_con[1],
  142. CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  143. aclk_div << CORE_ACLK_DIV_SHIFT |
  144. pclk_div << CORE_PERI_DIV_SHIFT);
  145. /*
  146. * select gpll as pd_bus bus clock source and
  147. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  148. */
  149. aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
  150. assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  151. pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
  152. assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
  153. hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
  154. assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
  155. rk_clrsetreg(&cru->cru_clksel_con[0],
  156. BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  157. BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  158. aclk_div << BUS_ACLK_DIV_SHIFT);
  159. rk_clrsetreg(&cru->cru_clksel_con[1],
  160. BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  161. pclk_div << BUS_PCLK_DIV_SHIFT |
  162. hclk_div << BUS_HCLK_DIV_SHIFT);
  163. /*
  164. * select gpll as pd_peri bus clock source and
  165. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  166. */
  167. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  168. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  169. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  170. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  171. PERI_ACLK_HZ && (hclk_div < 0x4));
  172. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  173. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  174. PERI_ACLK_HZ && pclk_div < 0x8);
  175. rk_clrsetreg(&cru->cru_clksel_con[10],
  176. PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  177. PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  178. PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  179. pclk_div << PERI_PCLK_DIV_SHIFT |
  180. hclk_div << PERI_HCLK_DIV_SHIFT |
  181. aclk_div << PERI_ACLK_DIV_SHIFT);
  182. /* PLL enter normal-mode */
  183. rk_clrsetreg(&cru->cru_mode_con,
  184. GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK,
  185. GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  186. APLL_MODE_NORM << APLL_MODE_SHIFT |
  187. CPLL_MODE_NORM << CPLL_MODE_SHIFT);
  188. /*fix NAND controller working clock max to 150Mhz */
  189. rk_clrsetreg(&cru->cru_clksel_con[2],
  190. NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
  191. NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
  192. 3 << NANDC_CLK_DIV_SHIFT);
  193. }
  194. /* Get pll rate by id */
  195. static u32 rkclk_pll_get_rate(struct rk3128_cru *cru,
  196. enum rk_clk_id clk_id)
  197. {
  198. u32 refdiv, fbdiv, postdiv1, postdiv2;
  199. u32 con;
  200. int pll_id = rk_pll_id(clk_id);
  201. struct rk3128_pll *pll = &cru->pll[pll_id];
  202. static u8 clk_shift[CLK_COUNT] = {
  203. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
  204. GPLL_MODE_SHIFT, 0xff
  205. };
  206. static u32 clk_mask[CLK_COUNT] = {
  207. 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
  208. GPLL_MODE_MASK, 0xff
  209. };
  210. uint shift;
  211. uint mask;
  212. con = readl(&cru->cru_mode_con);
  213. shift = clk_shift[clk_id];
  214. mask = clk_mask[clk_id];
  215. switch ((con & mask) >> shift) {
  216. case GPLL_MODE_SLOW:
  217. return OSC_HZ;
  218. case GPLL_MODE_NORM:
  219. /* normal mode */
  220. con = readl(&pll->con0);
  221. postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  222. fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  223. con = readl(&pll->con1);
  224. postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  225. refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  226. return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  227. case GPLL_MODE_DEEP:
  228. default:
  229. return 32768;
  230. }
  231. }
  232. static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
  233. int periph)
  234. {
  235. uint src_rate;
  236. uint div, mux;
  237. u32 con;
  238. switch (periph) {
  239. case HCLK_EMMC:
  240. case SCLK_EMMC:
  241. case SCLK_EMMC_SAMPLE:
  242. con = readl(&cru->cru_clksel_con[12]);
  243. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  244. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  245. break;
  246. case HCLK_SDMMC:
  247. case SCLK_SDMMC:
  248. con = readl(&cru->cru_clksel_con[11]);
  249. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  250. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  251. break;
  252. default:
  253. return -EINVAL;
  254. }
  255. src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
  256. return DIV_TO_RATE(src_rate, div);
  257. }
  258. static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
  259. int periph, uint freq)
  260. {
  261. int src_clk_div;
  262. int mux;
  263. debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
  264. /* mmc clock defaulg div 2 internal, need provide double in cru */
  265. src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
  266. if (src_clk_div > 128) {
  267. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  268. mux = EMMC_SEL_24M;
  269. } else {
  270. mux = EMMC_SEL_GPLL;
  271. }
  272. switch (periph) {
  273. case HCLK_EMMC:
  274. rk_clrsetreg(&cru->cru_clksel_con[12],
  275. EMMC_PLL_MASK | EMMC_DIV_MASK,
  276. mux << EMMC_PLL_SHIFT |
  277. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  278. break;
  279. case HCLK_SDMMC:
  280. case SCLK_SDMMC:
  281. rk_clrsetreg(&cru->cru_clksel_con[11],
  282. MMC0_PLL_MASK | MMC0_DIV_MASK,
  283. mux << MMC0_PLL_SHIFT |
  284. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  285. break;
  286. default:
  287. return -EINVAL;
  288. }
  289. return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
  290. }
  291. static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
  292. {
  293. u32 div, con;
  294. switch (clk_id) {
  295. case PCLK_I2C0:
  296. case PCLK_I2C1:
  297. case PCLK_I2C2:
  298. case PCLK_I2C3:
  299. case PCLK_PWM:
  300. con = readl(&cru->cru_clksel_con[10]);
  301. div = con >> 12 & 0x3;
  302. break;
  303. default:
  304. printf("do not support this peripheral bus\n");
  305. return -EINVAL;
  306. }
  307. return DIV_TO_RATE(PERI_ACLK_HZ, div);
  308. }
  309. static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz)
  310. {
  311. int src_clk_div;
  312. src_clk_div = PERI_ACLK_HZ / hz;
  313. assert(src_clk_div - 1 < 4);
  314. switch (clk_id) {
  315. case PCLK_I2C0:
  316. case PCLK_I2C1:
  317. case PCLK_I2C2:
  318. case PCLK_I2C3:
  319. case PCLK_PWM:
  320. rk_setreg(&cru->cru_clksel_con[10],
  321. ((src_clk_div - 1) << 12));
  322. break;
  323. default:
  324. printf("do not support this peripheral bus\n");
  325. return -EINVAL;
  326. }
  327. return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div);
  328. }
  329. static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru)
  330. {
  331. u32 div, val;
  332. val = readl(&cru->cru_clksel_con[24]);
  333. div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
  334. SARADC_DIV_CON_WIDTH);
  335. return DIV_TO_RATE(OSC_HZ, div);
  336. }
  337. static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz)
  338. {
  339. int src_clk_div;
  340. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  341. assert(src_clk_div < 128);
  342. rk_clrsetreg(&cru->cru_clksel_con[24],
  343. SARADC_DIV_CON_MASK,
  344. src_clk_div << SARADC_DIV_CON_SHIFT);
  345. return rk3128_saradc_get_clk(cru);
  346. }
  347. static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
  348. {
  349. int src_clk_div;
  350. struct pll_div cpll_config = {0};
  351. src_clk_div = GPLL_HZ / hz;
  352. assert(src_clk_div - 1 < 31);
  353. switch (clk_id) {
  354. case ACLK_VIO0:
  355. rk_clrsetreg(&cru->cru_clksel_con[31],
  356. VIO0_PLL_MASK | VIO0_DIV_MASK,
  357. VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
  358. (src_clk_div - 1) << VIO0_DIV_SHIFT);
  359. break;
  360. case ACLK_VIO1:
  361. rk_clrsetreg(&cru->cru_clksel_con[31],
  362. VIO1_PLL_MASK | VIO1_DIV_MASK,
  363. VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
  364. (src_clk_div - 1) << VIO1_DIV_SHIFT);
  365. break;
  366. case DCLK_LCDC:
  367. if (pll_para_config(hz, &cpll_config))
  368. return -1;
  369. rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
  370. rk_clrsetreg(&cru->cru_clksel_con[27],
  371. DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
  372. DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
  373. (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
  374. break;
  375. default:
  376. printf("do not support this vop freq\n");
  377. return -EINVAL;
  378. }
  379. return hz;
  380. }
  381. static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
  382. {
  383. u32 div, con, parent;
  384. switch (clk_id) {
  385. case ACLK_VIO0:
  386. con = readl(&cru->cru_clksel_con[31]);
  387. div = con & 0x1f;
  388. parent = GPLL_HZ;
  389. break;
  390. case ACLK_VIO1:
  391. con = readl(&cru->cru_clksel_con[31]);
  392. div = (con >> 8) & 0x1f;
  393. parent = GPLL_HZ;
  394. break;
  395. case DCLK_LCDC:
  396. con = readl(&cru->cru_clksel_con[27]);
  397. div = (con >> 8) & 0xfff;
  398. parent = rkclk_pll_get_rate(cru, CLK_CODEC);
  399. break;
  400. default:
  401. return -ENOENT;
  402. }
  403. return DIV_TO_RATE(parent, div);
  404. }
  405. static ulong rk3128_clk_get_rate(struct clk *clk)
  406. {
  407. struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
  408. switch (clk->id) {
  409. case 0 ... 63:
  410. return rkclk_pll_get_rate(priv->cru, clk->id);
  411. case PCLK_I2C0:
  412. case PCLK_I2C1:
  413. case PCLK_I2C2:
  414. case PCLK_I2C3:
  415. case PCLK_PWM:
  416. return rk3128_peri_get_pclk(priv->cru, clk->id);
  417. case SCLK_SARADC:
  418. return rk3128_saradc_get_clk(priv->cru);
  419. case DCLK_LCDC:
  420. case ACLK_VIO0:
  421. case ACLK_VIO1:
  422. return rk3128_vop_get_rate(priv->cru, clk->id);
  423. default:
  424. return -ENOENT;
  425. }
  426. }
  427. static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
  428. {
  429. struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
  430. ulong new_rate, gclk_rate;
  431. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  432. switch (clk->id) {
  433. case 0 ... 63:
  434. return 0;
  435. case DCLK_LCDC:
  436. case ACLK_VIO0:
  437. case ACLK_VIO1:
  438. new_rate = rk3128_vop_set_clk(priv->cru,
  439. clk->id, rate);
  440. break;
  441. case HCLK_EMMC:
  442. new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  443. clk->id, rate);
  444. break;
  445. case PCLK_I2C0:
  446. case PCLK_I2C1:
  447. case PCLK_I2C2:
  448. case PCLK_I2C3:
  449. case PCLK_PWM:
  450. new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate);
  451. break;
  452. case SCLK_SARADC:
  453. new_rate = rk3128_saradc_set_clk(priv->cru, rate);
  454. break;
  455. default:
  456. return -ENOENT;
  457. }
  458. return new_rate;
  459. }
  460. static struct clk_ops rk3128_clk_ops = {
  461. .get_rate = rk3128_clk_get_rate,
  462. .set_rate = rk3128_clk_set_rate,
  463. };
  464. static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
  465. {
  466. struct rk3128_clk_priv *priv = dev_get_priv(dev);
  467. priv->cru = dev_read_addr_ptr(dev);
  468. return 0;
  469. }
  470. static int rk3128_clk_probe(struct udevice *dev)
  471. {
  472. struct rk3128_clk_priv *priv = dev_get_priv(dev);
  473. rkclk_init(priv->cru);
  474. return 0;
  475. }
  476. static int rk3128_clk_bind(struct udevice *dev)
  477. {
  478. int ret;
  479. struct udevice *sys_child;
  480. struct sysreset_reg *priv;
  481. /* The reset driver does not have a device node, so bind it here */
  482. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  483. &sys_child);
  484. if (ret) {
  485. debug("Warning: No sysreset driver: ret=%d\n", ret);
  486. } else {
  487. priv = malloc(sizeof(struct sysreset_reg));
  488. priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
  489. cru_glb_srst_fst_value);
  490. priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
  491. cru_glb_srst_snd_value);
  492. sys_child->priv = priv;
  493. }
  494. return 0;
  495. }
  496. static const struct udevice_id rk3128_clk_ids[] = {
  497. { .compatible = "rockchip,rk3128-cru" },
  498. { .compatible = "rockchip,rk3126-cru" },
  499. { }
  500. };
  501. U_BOOT_DRIVER(rockchip_rk3128_cru) = {
  502. .name = "clk_rk3128",
  503. .id = UCLASS_CLK,
  504. .of_match = rk3128_clk_ids,
  505. .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
  506. .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
  507. .ops = &rk3128_clk_ops,
  508. .bind = rk3128_clk_bind,
  509. .probe = rk3128_clk_probe,
  510. };