clk_rk3036.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <syscon.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/clock.h>
  12. #include <asm/arch-rockchip/cru_rk3036.h>
  13. #include <asm/arch-rockchip/hardware.h>
  14. #include <dm/lists.h>
  15. #include <dt-bindings/clock/rk3036-cru.h>
  16. #include <linux/log2.h>
  17. enum {
  18. VCO_MAX_HZ = 2400U * 1000000,
  19. VCO_MIN_HZ = 600 * 1000000,
  20. OUTPUT_MAX_HZ = 2400U * 1000000,
  21. OUTPUT_MIN_HZ = 24 * 1000000,
  22. };
  23. #define RATE_TO_DIV(input_rate, output_rate) \
  24. ((input_rate) / (output_rate) - 1);
  25. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  26. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  27. .refdiv = _refdiv,\
  28. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  29. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  30. _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
  31. OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
  32. #hz "Hz cannot be hit with PLL "\
  33. "divisors on line " __stringify(__LINE__));
  34. /* use integer mode*/
  35. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  36. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  37. static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
  38. const struct pll_div *div)
  39. {
  40. int pll_id = rk_pll_id(clk_id);
  41. struct rk3036_pll *pll = &cru->pll[pll_id];
  42. /* All PLLs have same VCO and output frequency range restrictions. */
  43. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  44. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  45. debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
  46. vco=%u Hz, output=%u Hz\n",
  47. pll, div->fbdiv, div->refdiv, div->postdiv1,
  48. div->postdiv2, vco_hz, output_hz);
  49. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  50. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  51. /* use integer mode */
  52. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  53. rk_clrsetreg(&pll->con0,
  54. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  55. (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  56. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  57. (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  58. div->refdiv << PLL_REFDIV_SHIFT));
  59. /* waiting for pll lock */
  60. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  61. udelay(1);
  62. return 0;
  63. }
  64. static void rkclk_init(struct rk3036_cru *cru)
  65. {
  66. u32 aclk_div;
  67. u32 hclk_div;
  68. u32 pclk_div;
  69. /* pll enter slow-mode */
  70. rk_clrsetreg(&cru->cru_mode_con,
  71. GPLL_MODE_MASK | APLL_MODE_MASK,
  72. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  73. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  74. /* init pll */
  75. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  76. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  77. /*
  78. * select apll as cpu/core clock pll source and
  79. * set up dependent divisors for PERI and ACLK clocks.
  80. * core hz : apll = 1:1
  81. */
  82. aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
  83. assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
  84. pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
  85. assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
  86. rk_clrsetreg(&cru->cru_clksel_con[0],
  87. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  88. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  89. 0 << CORE_DIV_CON_SHIFT);
  90. rk_clrsetreg(&cru->cru_clksel_con[1],
  91. CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  92. aclk_div << CORE_ACLK_DIV_SHIFT |
  93. pclk_div << CORE_PERI_DIV_SHIFT);
  94. /*
  95. * select apll as pd_bus bus clock source and
  96. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  97. */
  98. aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
  99. assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  100. pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
  101. assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
  102. hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
  103. assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
  104. rk_clrsetreg(&cru->cru_clksel_con[0],
  105. BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  106. BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  107. aclk_div << BUS_ACLK_DIV_SHIFT);
  108. rk_clrsetreg(&cru->cru_clksel_con[1],
  109. BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  110. pclk_div << BUS_PCLK_DIV_SHIFT |
  111. hclk_div << BUS_HCLK_DIV_SHIFT);
  112. /*
  113. * select gpll as pd_peri bus clock source and
  114. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  115. */
  116. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  117. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  118. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  119. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  120. PERI_ACLK_HZ && (hclk_div < 0x4));
  121. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  122. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  123. PERI_ACLK_HZ && pclk_div < 0x8);
  124. rk_clrsetreg(&cru->cru_clksel_con[10],
  125. PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  126. PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  127. PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  128. pclk_div << PERI_PCLK_DIV_SHIFT |
  129. hclk_div << PERI_HCLK_DIV_SHIFT |
  130. aclk_div << PERI_ACLK_DIV_SHIFT);
  131. /* PLL enter normal-mode */
  132. rk_clrsetreg(&cru->cru_mode_con,
  133. GPLL_MODE_MASK | APLL_MODE_MASK,
  134. GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  135. APLL_MODE_NORM << APLL_MODE_SHIFT);
  136. }
  137. /* Get pll rate by id */
  138. static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
  139. enum rk_clk_id clk_id)
  140. {
  141. uint32_t refdiv, fbdiv, postdiv1, postdiv2;
  142. uint32_t con;
  143. int pll_id = rk_pll_id(clk_id);
  144. struct rk3036_pll *pll = &cru->pll[pll_id];
  145. static u8 clk_shift[CLK_COUNT] = {
  146. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
  147. GPLL_MODE_SHIFT, 0xff
  148. };
  149. static u32 clk_mask[CLK_COUNT] = {
  150. 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
  151. GPLL_MODE_MASK, 0xffffffff
  152. };
  153. uint shift;
  154. uint mask;
  155. con = readl(&cru->cru_mode_con);
  156. shift = clk_shift[clk_id];
  157. mask = clk_mask[clk_id];
  158. switch ((con & mask) >> shift) {
  159. case GPLL_MODE_SLOW:
  160. return OSC_HZ;
  161. case GPLL_MODE_NORM:
  162. /* normal mode */
  163. con = readl(&pll->con0);
  164. postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  165. fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  166. con = readl(&pll->con1);
  167. postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  168. refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  169. return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  170. case GPLL_MODE_DEEP:
  171. default:
  172. return 32768;
  173. }
  174. }
  175. static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
  176. int periph)
  177. {
  178. uint src_rate;
  179. uint div, mux;
  180. u32 con;
  181. switch (periph) {
  182. case HCLK_EMMC:
  183. case SCLK_EMMC:
  184. con = readl(&cru->cru_clksel_con[12]);
  185. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  186. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  187. break;
  188. case HCLK_SDIO:
  189. case SCLK_SDIO:
  190. con = readl(&cru->cru_clksel_con[12]);
  191. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  192. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  193. break;
  194. default:
  195. return -EINVAL;
  196. }
  197. src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
  198. return DIV_TO_RATE(src_rate, div) / 2;
  199. }
  200. static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
  201. int periph, uint freq)
  202. {
  203. int src_clk_div;
  204. int mux;
  205. debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
  206. /* mmc clock auto divide 2 in internal */
  207. src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
  208. if (src_clk_div > 128) {
  209. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  210. assert(src_clk_div - 1 < 128);
  211. mux = EMMC_SEL_24M;
  212. } else {
  213. mux = EMMC_SEL_GPLL;
  214. }
  215. switch (periph) {
  216. case HCLK_EMMC:
  217. case SCLK_EMMC:
  218. rk_clrsetreg(&cru->cru_clksel_con[12],
  219. EMMC_PLL_MASK | EMMC_DIV_MASK,
  220. mux << EMMC_PLL_SHIFT |
  221. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  222. break;
  223. case HCLK_SDIO:
  224. case SCLK_SDIO:
  225. rk_clrsetreg(&cru->cru_clksel_con[11],
  226. MMC0_PLL_MASK | MMC0_DIV_MASK,
  227. mux << MMC0_PLL_SHIFT |
  228. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  229. break;
  230. default:
  231. return -EINVAL;
  232. }
  233. return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
  234. }
  235. static ulong rk3036_clk_get_rate(struct clk *clk)
  236. {
  237. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  238. switch (clk->id) {
  239. case 0 ... 63:
  240. return rkclk_pll_get_rate(priv->cru, clk->id);
  241. default:
  242. return -ENOENT;
  243. }
  244. }
  245. static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
  246. {
  247. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  248. ulong new_rate, gclk_rate;
  249. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  250. switch (clk->id) {
  251. case 0 ... 63:
  252. return 0;
  253. case HCLK_EMMC:
  254. case SCLK_EMMC:
  255. new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  256. clk->id, rate);
  257. break;
  258. default:
  259. return -ENOENT;
  260. }
  261. return new_rate;
  262. }
  263. static struct clk_ops rk3036_clk_ops = {
  264. .get_rate = rk3036_clk_get_rate,
  265. .set_rate = rk3036_clk_set_rate,
  266. };
  267. static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
  268. {
  269. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  270. priv->cru = dev_read_addr_ptr(dev);
  271. return 0;
  272. }
  273. static int rk3036_clk_probe(struct udevice *dev)
  274. {
  275. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  276. rkclk_init(priv->cru);
  277. return 0;
  278. }
  279. static int rk3036_clk_bind(struct udevice *dev)
  280. {
  281. int ret;
  282. struct udevice *sys_child;
  283. struct sysreset_reg *priv;
  284. /* The reset driver does not have a device node, so bind it here */
  285. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  286. &sys_child);
  287. if (ret) {
  288. debug("Warning: No sysreset driver: ret=%d\n", ret);
  289. } else {
  290. priv = malloc(sizeof(struct sysreset_reg));
  291. priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
  292. cru_glb_srst_fst_value);
  293. priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
  294. cru_glb_srst_snd_value);
  295. sys_child->priv = priv;
  296. }
  297. #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
  298. ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
  299. ret = rockchip_reset_bind(dev, ret, 9);
  300. if (ret)
  301. debug("Warning: software reset driver bind faile\n");
  302. #endif
  303. return 0;
  304. }
  305. static const struct udevice_id rk3036_clk_ids[] = {
  306. { .compatible = "rockchip,rk3036-cru" },
  307. { }
  308. };
  309. U_BOOT_DRIVER(rockchip_rk3036_cru) = {
  310. .name = "clk_rk3036",
  311. .id = UCLASS_CLK,
  312. .of_match = rk3036_clk_ids,
  313. .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
  314. .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
  315. .ops = &rk3036_clk_ops,
  316. .bind = rk3036_clk_bind,
  317. .probe = rk3036_clk_probe,
  318. };