123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261 |
- // SPDX-License-Identifier: GPL-2.0+
- /*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
- #include <common.h>
- #include <debug_uart.h>
- #include <dm.h>
- #include <ram.h>
- #include <spl.h>
- #include <spl_gpio.h>
- #include <syscon.h>
- #include <asm/io.h>
- #include <asm/arch-rockchip/bootrom.h>
- #include <asm/arch-rockchip/clock.h>
- #include <asm/arch-rockchip/grf_rk3399.h>
- #include <asm/arch-rockchip/hardware.h>
- #include <asm/arch-rockchip/periph.h>
- #include <asm/arch-rockchip/sys_proto.h>
- #include <dm/pinctrl.h>
- void board_return_to_bootrom(void)
- {
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
- }
- static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
- [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
- [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
- };
- const char *board_spl_was_booted_from(void)
- {
- u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
- const char *bootdevice_ofpath = NULL;
- if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
- bootdevice_ofpath = boot_devices[bootdevice_brom_id];
- if (bootdevice_ofpath)
- debug("%s: brom_bootdevice_id %x maps to '%s'\n",
- __func__, bootdevice_brom_id, bootdevice_ofpath);
- else
- debug("%s: failed to resolve brom_bootdevice_id %x\n",
- __func__, bootdevice_brom_id);
- return bootdevice_ofpath;
- }
- u32 spl_boot_device(void)
- {
- u32 boot_device = BOOT_DEVICE_MMC1;
- if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
- return BOOT_DEVICE_BOOTROM;
- return boot_device;
- }
- const char *spl_decode_boot_device(u32 boot_device)
- {
- int i;
- static const struct {
- u32 boot_device;
- const char *ofpath;
- } spl_boot_devices_tbl[] = {
- { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
- { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
- { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
- };
- for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
- if (spl_boot_devices_tbl[i].boot_device == boot_device)
- return spl_boot_devices_tbl[i].ofpath;
- return NULL;
- }
- void spl_perform_fixups(struct spl_image_info *spl_image)
- {
- void *blob = spl_image->fdt_addr;
- const char *boot_ofpath;
- int chosen;
- /*
- * Inject the ofpath of the device the full U-Boot (or Linux in
- * Falcon-mode) was booted from into the FDT, if a FDT has been
- * loaded at the same time.
- */
- if (!blob)
- return;
- boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
- if (!boot_ofpath) {
- pr_err("%s: could not map boot_device to ofpath\n", __func__);
- return;
- }
- chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
- if (chosen < 0) {
- pr_err("%s: could not find/create '/chosen'\n", __func__);
- return;
- }
- fdt_setprop_string(blob, chosen,
- "u-boot,spl-boot-device", boot_ofpath);
- }
- #define TIMER_CHN10_BASE 0xff8680a0
- #define TIMER_END_COUNT_L 0x00
- #define TIMER_END_COUNT_H 0x04
- #define TIMER_INIT_COUNT_L 0x10
- #define TIMER_INIT_COUNT_H 0x14
- #define TIMER_CONTROL_REG 0x1c
- #define TIMER_EN 0x1
- #define TIMER_FMODE (0 << 1)
- #define TIMER_RMODE (1 << 1)
- void secure_timer_init(void)
- {
- writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
- writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
- writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
- writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
- writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
- }
- void board_debug_uart_init(void)
- {
- #define GRF_BASE 0xff770000
- #define GPIO0_BASE 0xff720000
- #define PMUGRF_BASE 0xff320000
- struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
- #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
- struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
- #endif
- #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
- /* Enable early UART0 on the RK3399 */
- rk_clrsetreg(&grf->gpio2c_iomux,
- GRF_GPIO2C0_SEL_MASK,
- GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio2c_iomux,
- GRF_GPIO2C1_SEL_MASK,
- GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
- #else
- # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- rk_setreg(&grf->io_vsel, 1 << 0);
- /*
- * Let's enable these power rails here, we are already running the SPI
- * Flash based code.
- */
- spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
- spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
- spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
- spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
- #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
- /* Enable early UART2 channel C on the RK3399 */
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C3_SEL_MASK,
- GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C4_SEL_MASK,
- GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
- /* Set channel C as UART2 input */
- rk_clrsetreg(&grf->soc_con7,
- GRF_UART_DBG_SEL_MASK,
- GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
- #endif
- }
- void board_init_f(ulong dummy)
- {
- struct udevice *pinctrl;
- struct udevice *dev;
- struct rk3399_pmusgrf_regs *sgrf;
- struct rk3399_grf_regs *grf;
- int ret;
- #define EARLY_UART
- #ifdef EARLY_UART
- debug_uart_init();
- # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- int sum, i;
- /*
- * Add a delay and ensure that the compiler does not optimise this out.
- * This is needed since the power rails tail a while to turn on, and
- * we get garbage serial output otherwise.
- */
- sum = 0;
- for (i = 0; i < 150000; i++)
- sum += i;
- gru_dummy_function(sum);
- #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- printascii("U-Boot SPL board init\n");
- #endif
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
- /*
- * Disable DDR and SRAM security regions.
- *
- * As we are entered from the BootROM, the region from
- * 0x0 through 0xfffff (i.e. the first MB of memory) will
- * be protected. This will cause issues with the DW_MMC
- * driver, which tries to DMA from/to the stack (likely)
- * located in this range.
- */
- sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
- rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
- rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
- /* eMMC clock generator: disable the clock multipilier */
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- rk_clrreg(&grf->emmccore_con[11], 0x0ff);
- secure_timer_init();
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- pr_err("Pinctrl init failed: %d\n", ret);
- return;
- }
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- pr_err("DRAM init failed: %d\n", ret);
- return;
- }
- }
- #ifdef CONFIG_SPL_LOAD_FIT
- int board_fit_config_name_match(const char *name)
- {
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
- return 0;
- }
- #endif
|