rk3399-board-spl.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  4. * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  5. */
  6. #include <common.h>
  7. #include <debug_uart.h>
  8. #include <dm.h>
  9. #include <ram.h>
  10. #include <spl.h>
  11. #include <spl_gpio.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/bootrom.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/arch-rockchip/grf_rk3399.h>
  17. #include <asm/arch-rockchip/hardware.h>
  18. #include <asm/arch-rockchip/periph.h>
  19. #include <asm/arch-rockchip/sys_proto.h>
  20. #include <dm/pinctrl.h>
  21. void board_return_to_bootrom(void)
  22. {
  23. back_to_bootrom(BROM_BOOT_NEXTSTAGE);
  24. }
  25. static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  26. [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
  27. [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
  28. [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
  29. };
  30. const char *board_spl_was_booted_from(void)
  31. {
  32. u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
  33. const char *bootdevice_ofpath = NULL;
  34. if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
  35. bootdevice_ofpath = boot_devices[bootdevice_brom_id];
  36. if (bootdevice_ofpath)
  37. debug("%s: brom_bootdevice_id %x maps to '%s'\n",
  38. __func__, bootdevice_brom_id, bootdevice_ofpath);
  39. else
  40. debug("%s: failed to resolve brom_bootdevice_id %x\n",
  41. __func__, bootdevice_brom_id);
  42. return bootdevice_ofpath;
  43. }
  44. u32 spl_boot_device(void)
  45. {
  46. u32 boot_device = BOOT_DEVICE_MMC1;
  47. if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
  48. return BOOT_DEVICE_BOOTROM;
  49. return boot_device;
  50. }
  51. const char *spl_decode_boot_device(u32 boot_device)
  52. {
  53. int i;
  54. static const struct {
  55. u32 boot_device;
  56. const char *ofpath;
  57. } spl_boot_devices_tbl[] = {
  58. { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
  59. { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
  60. { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
  61. };
  62. for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
  63. if (spl_boot_devices_tbl[i].boot_device == boot_device)
  64. return spl_boot_devices_tbl[i].ofpath;
  65. return NULL;
  66. }
  67. void spl_perform_fixups(struct spl_image_info *spl_image)
  68. {
  69. void *blob = spl_image->fdt_addr;
  70. const char *boot_ofpath;
  71. int chosen;
  72. /*
  73. * Inject the ofpath of the device the full U-Boot (or Linux in
  74. * Falcon-mode) was booted from into the FDT, if a FDT has been
  75. * loaded at the same time.
  76. */
  77. if (!blob)
  78. return;
  79. boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
  80. if (!boot_ofpath) {
  81. pr_err("%s: could not map boot_device to ofpath\n", __func__);
  82. return;
  83. }
  84. chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
  85. if (chosen < 0) {
  86. pr_err("%s: could not find/create '/chosen'\n", __func__);
  87. return;
  88. }
  89. fdt_setprop_string(blob, chosen,
  90. "u-boot,spl-boot-device", boot_ofpath);
  91. }
  92. #define TIMER_CHN10_BASE 0xff8680a0
  93. #define TIMER_END_COUNT_L 0x00
  94. #define TIMER_END_COUNT_H 0x04
  95. #define TIMER_INIT_COUNT_L 0x10
  96. #define TIMER_INIT_COUNT_H 0x14
  97. #define TIMER_CONTROL_REG 0x1c
  98. #define TIMER_EN 0x1
  99. #define TIMER_FMODE (0 << 1)
  100. #define TIMER_RMODE (1 << 1)
  101. void secure_timer_init(void)
  102. {
  103. writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
  104. writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
  105. writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
  106. writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
  107. writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
  108. }
  109. void board_debug_uart_init(void)
  110. {
  111. #define GRF_BASE 0xff770000
  112. #define GPIO0_BASE 0xff720000
  113. #define PMUGRF_BASE 0xff320000
  114. struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  115. #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  116. struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
  117. struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
  118. #endif
  119. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  120. /* Enable early UART0 on the RK3399 */
  121. rk_clrsetreg(&grf->gpio2c_iomux,
  122. GRF_GPIO2C0_SEL_MASK,
  123. GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  124. rk_clrsetreg(&grf->gpio2c_iomux,
  125. GRF_GPIO2C1_SEL_MASK,
  126. GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  127. #else
  128. # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  129. rk_setreg(&grf->io_vsel, 1 << 0);
  130. /*
  131. * Let's enable these power rails here, we are already running the SPI
  132. * Flash based code.
  133. */
  134. spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
  135. spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  136. spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
  137. spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
  138. #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
  139. /* Enable early UART2 channel C on the RK3399 */
  140. rk_clrsetreg(&grf->gpio4c_iomux,
  141. GRF_GPIO4C3_SEL_MASK,
  142. GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
  143. rk_clrsetreg(&grf->gpio4c_iomux,
  144. GRF_GPIO4C4_SEL_MASK,
  145. GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
  146. /* Set channel C as UART2 input */
  147. rk_clrsetreg(&grf->soc_con7,
  148. GRF_UART_DBG_SEL_MASK,
  149. GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
  150. #endif
  151. }
  152. void board_init_f(ulong dummy)
  153. {
  154. struct udevice *pinctrl;
  155. struct udevice *dev;
  156. struct rk3399_pmusgrf_regs *sgrf;
  157. struct rk3399_grf_regs *grf;
  158. int ret;
  159. #define EARLY_UART
  160. #ifdef EARLY_UART
  161. debug_uart_init();
  162. # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  163. int sum, i;
  164. /*
  165. * Add a delay and ensure that the compiler does not optimise this out.
  166. * This is needed since the power rails tail a while to turn on, and
  167. * we get garbage serial output otherwise.
  168. */
  169. sum = 0;
  170. for (i = 0; i < 150000; i++)
  171. sum += i;
  172. gru_dummy_function(sum);
  173. #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
  174. /*
  175. * Debug UART can be used from here if required:
  176. *
  177. * debug_uart_init();
  178. * printch('a');
  179. * printhex8(0x1234);
  180. * printascii("string");
  181. */
  182. printascii("U-Boot SPL board init\n");
  183. #endif
  184. ret = spl_early_init();
  185. if (ret) {
  186. debug("spl_early_init() failed: %d\n", ret);
  187. hang();
  188. }
  189. /*
  190. * Disable DDR and SRAM security regions.
  191. *
  192. * As we are entered from the BootROM, the region from
  193. * 0x0 through 0xfffff (i.e. the first MB of memory) will
  194. * be protected. This will cause issues with the DW_MMC
  195. * driver, which tries to DMA from/to the stack (likely)
  196. * located in this range.
  197. */
  198. sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  199. rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
  200. rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
  201. /* eMMC clock generator: disable the clock multipilier */
  202. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  203. rk_clrreg(&grf->emmccore_con[11], 0x0ff);
  204. secure_timer_init();
  205. ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
  206. if (ret) {
  207. pr_err("Pinctrl init failed: %d\n", ret);
  208. return;
  209. }
  210. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  211. if (ret) {
  212. pr_err("DRAM init failed: %d\n", ret);
  213. return;
  214. }
  215. }
  216. #ifdef CONFIG_SPL_LOAD_FIT
  217. int board_fit_config_name_match(const char *name)
  218. {
  219. /* Just empty function now - can't decide what to choose */
  220. debug("%s: %s\n", __func__, name);
  221. return 0;
  222. }
  223. #endif