rk322x-board.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <ram.h>
  9. #include <syscon.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/boot_mode.h>
  12. #include <asm/arch-rockchip/clock.h>
  13. #include <asm/arch-rockchip/periph.h>
  14. #include <asm/arch-rockchip/grf_rk322x.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. __weak int rk_board_late_init(void)
  17. {
  18. return 0;
  19. }
  20. int board_late_init(void)
  21. {
  22. setup_boot_mode();
  23. return rk_board_late_init();
  24. }
  25. int board_init(void)
  26. {
  27. #include <asm/arch-rockchip/grf_rk322x.h>
  28. /* Enable early UART2 channel 1 on the RK322x */
  29. #define GRF_BASE 0x11000000
  30. struct rk322x_grf * const grf = (void *)GRF_BASE;
  31. enum {
  32. GPIO1B2_SHIFT = 4,
  33. GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
  34. GPIO1B2_GPIO = 0,
  35. GPIO1B2_UART21_SIN,
  36. GPIO1B1_SHIFT = 2,
  37. GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
  38. GPIO1B1_GPIO = 0,
  39. GPIO1B1_UART1_SOUT,
  40. GPIO1B1_UART21_SOUT,
  41. };
  42. enum {
  43. CON_IOMUX_UART2SEL_SHIFT= 8,
  44. CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
  45. CON_IOMUX_UART2SEL_2 = 0,
  46. CON_IOMUX_UART2SEL_21,
  47. };
  48. rk_clrsetreg(&grf->gpio1b_iomux,
  49. GPIO1B1_MASK | GPIO1B2_MASK,
  50. GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
  51. GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
  52. /* Set channel C as UART2 input */
  53. rk_clrsetreg(&grf->con_iomux,
  54. CON_IOMUX_UART2SEL_MASK,
  55. CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
  56. /*
  57. * The integrated macphy is enabled by default, disable it
  58. * for saving power consuming.
  59. */
  60. rk_clrsetreg(&grf->macphy_con[0],
  61. MACPHY_CFG_ENABLE_MASK,
  62. 0 << MACPHY_CFG_ENABLE_SHIFT);
  63. return 0;
  64. }
  65. int dram_init_banksize(void)
  66. {
  67. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  68. gd->bd->bi_dram[0].size = 0x8400000;
  69. /* Reserve 0x200000 for OPTEE */
  70. gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
  71. + gd->bd->bi_dram[0].size + 0x200000;
  72. gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  73. + gd->ram_size - gd->bd->bi_dram[1].start;
  74. return 0;
  75. }
  76. #ifndef CONFIG_SYS_DCACHE_OFF
  77. void enable_caches(void)
  78. {
  79. /* Enable D-cache. I-cache is already enabled in start.S */
  80. dcache_enable();
  81. }
  82. #endif
  83. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  84. #include <usb.h>
  85. #include <usb/dwc2_udc.h>
  86. static struct dwc2_plat_otg_data rk322x_otg_data = {
  87. .rx_fifo_sz = 512,
  88. .np_tx_fifo_sz = 16,
  89. .tx_fifo_sz = 128,
  90. };
  91. int board_usb_init(int index, enum usb_init_type init)
  92. {
  93. int node;
  94. const char *mode;
  95. bool matched = false;
  96. const void *blob = gd->fdt_blob;
  97. /* find the usb_otg node */
  98. node = fdt_node_offset_by_compatible(blob, -1,
  99. "rockchip,rk3288-usb");
  100. while (node > 0) {
  101. mode = fdt_getprop(blob, node, "dr_mode", NULL);
  102. if (mode && strcmp(mode, "otg") == 0) {
  103. matched = true;
  104. break;
  105. }
  106. node = fdt_node_offset_by_compatible(blob, node,
  107. "rockchip,rk3288-usb");
  108. }
  109. if (!matched) {
  110. debug("Not found usb_otg device\n");
  111. return -ENODEV;
  112. }
  113. rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
  114. return dwc2_udc_probe(&rk322x_otg_data);
  115. }
  116. int board_usb_cleanup(int index, enum usb_init_type init)
  117. {
  118. return 0;
  119. }
  120. #endif
  121. #if CONFIG_IS_ENABLED(FASTBOOT)
  122. int fastboot_set_reboot_flag(void)
  123. {
  124. struct rk322x_grf *grf;
  125. printf("Setting reboot to fastboot flag ...\n");
  126. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  127. /* Set boot mode to fastboot */
  128. writel(BOOT_FASTBOOT, &grf->os_reg[0]);
  129. return 0;
  130. }
  131. #endif