Kconfig 7.9 KB

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  1. if ARCH_ROCKCHIP
  2. config ROCKCHIP_RK3036
  3. bool "Support Rockchip RK3036"
  4. select CPU_V7A
  5. select SUPPORT_SPL
  6. select SPL
  7. imply USB_FUNCTION_ROCKUSB
  8. imply CMD_ROCKUSB
  9. help
  10. The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
  11. including NEON and GPU, Mali-400 graphics, several DDR3 options
  12. and video codec support. Peripherals include Gigabit Ethernet,
  13. USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
  14. config ROCKCHIP_RK3128
  15. bool "Support Rockchip RK3128"
  16. select CPU_V7A
  17. help
  18. The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
  19. including NEON and GPU, Mali-400 graphics, several DDR3 options
  20. and video codec support. Peripherals include Gigabit Ethernet,
  21. USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
  22. config ROCKCHIP_RK3188
  23. bool "Support Rockchip RK3188"
  24. select CPU_V7A
  25. select SPL_BOARD_INIT if SPL
  26. select SUPPORT_SPL
  27. select SPL
  28. select SPL_CLK
  29. select SPL_REGMAP
  30. select SPL_SYSCON
  31. select SPL_RAM
  32. select SPL_DRIVERS_MISC_SUPPORT
  33. select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
  34. select DEBUG_UART_BOARD_INIT
  35. select BOARD_LATE_INIT
  36. select ROCKCHIP_BROM_HELPER
  37. help
  38. The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
  39. including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
  40. video interfaces, several memory options and video codec support.
  41. Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
  42. UART, SPI, I2C and PWMs.
  43. config ROCKCHIP_RK322X
  44. bool "Support Rockchip RK3228/RK3229"
  45. select CPU_V7A
  46. select SUPPORT_SPL
  47. select SPL
  48. select ROCKCHIP_BROM_HELPER
  49. select DEBUG_UART_BOARD_INIT
  50. help
  51. The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
  52. including NEON and GPU, Mali-400 graphics, several DDR3 options
  53. and video codec support. Peripherals include Gigabit Ethernet,
  54. USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
  55. config ROCKCHIP_RK3288
  56. bool "Support Rockchip RK3288"
  57. select CPU_V7A
  58. select SPL_BOARD_INIT if SPL
  59. select SUPPORT_SPL
  60. select SPL
  61. imply USB_FUNCTION_ROCKUSB
  62. imply CMD_ROCKUSB
  63. help
  64. The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
  65. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
  66. video interfaces supporting HDMI and eDP, several DDR3 options
  67. and video codec support. Peripherals include Gigabit Ethernet,
  68. USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
  69. if ROCKCHIP_RK3288
  70. config TPL_TEXT_BASE
  71. default 0xff704000
  72. config TPL_MAX_SIZE
  73. default 32768
  74. endif
  75. config ROCKCHIP_RK3328
  76. bool "Support Rockchip RK3328"
  77. select ARM64
  78. help
  79. The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
  80. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
  81. video interfaces supporting HDMI and eDP, several DDR3 options
  82. and video codec support. Peripherals include Gigabit Ethernet,
  83. USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
  84. config ROCKCHIP_RK3368
  85. bool "Support Rockchip RK3368"
  86. select ARM64
  87. select SUPPORT_SPL
  88. select SUPPORT_TPL
  89. select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
  90. select TPL_NEEDS_SEPARATE_STACK if TPL
  91. imply SPL_SEPARATE_BSS
  92. imply SPL_SERIAL_SUPPORT
  93. imply TPL_SERIAL_SUPPORT
  94. select DEBUG_UART_BOARD_INIT
  95. help
  96. The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
  97. into a big and little cluster with 4 cores each) Cortex-A53 including
  98. AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
  99. (for the little cluster), PowerVR G6110 based graphics, one video
  100. output processor supporting LVDS/HDMI/eDP, several DDR3 options and
  101. video codec support.
  102. On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
  103. I2S, UARTs, SPI, I2C and PWMs.
  104. if ROCKCHIP_RK3368
  105. config TPL_TEXT_BASE
  106. default 0xff8c1000
  107. config TPL_MAX_SIZE
  108. default 28672
  109. config TPL_STACK
  110. default 0xff8cffff
  111. endif
  112. config ROCKCHIP_RK3399
  113. bool "Support Rockchip RK3399"
  114. select ARM64
  115. select SUPPORT_SPL
  116. select SPL
  117. select SPL_SEPARATE_BSS
  118. select SPL_SERIAL_SUPPORT
  119. select SPL_DRIVERS_MISC_SUPPORT
  120. select DEBUG_UART_BOARD_INIT
  121. select BOARD_LATE_INIT
  122. select ROCKCHIP_BROM_HELPER
  123. help
  124. The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
  125. and quad-core Cortex-A53.
  126. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
  127. video interfaces supporting HDMI and eDP, several DDR3 options
  128. and video codec support. Peripherals include Gigabit Ethernet,
  129. USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
  130. config ROCKCHIP_RV1108
  131. bool "Support Rockchip RV1108"
  132. select CPU_V7A
  133. help
  134. The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
  135. and a DSP.
  136. config ROCKCHIP_USB_UART
  137. bool "Route uart output to usb pins"
  138. help
  139. Rockchip SoCs have the ability to route the signals of the debug
  140. uart through the d+ and d- pins of a specific usb phy to enable
  141. some form of closed-case debugging. With this option supported
  142. SoCs will enable this routing as a debug measure.
  143. config SPL_ROCKCHIP_BACK_TO_BROM
  144. bool "SPL returns to bootrom"
  145. default y if ROCKCHIP_RK3036
  146. select ROCKCHIP_BROM_HELPER
  147. depends on SPL
  148. help
  149. Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
  150. SPL will return to the boot rom, which will then load the U-Boot
  151. binary to keep going on.
  152. config TPL_ROCKCHIP_BACK_TO_BROM
  153. bool "TPL returns to bootrom"
  154. default y if ROCKCHIP_RK3368
  155. select ROCKCHIP_BROM_HELPER
  156. depends on TPL
  157. help
  158. Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
  159. SPL will return to the boot rom, which will then load the U-Boot
  160. binary to keep going on.
  161. config ROCKCHIP_BOOT_MODE_REG
  162. hex "Rockchip boot mode flag register address"
  163. default 0x200081c8 if ROCKCHIP_RK3036
  164. default 0x20004040 if ROCKCHIP_RK3188
  165. default 0x110005c8 if ROCKCHIP_RK322X
  166. default 0xff730094 if ROCKCHIP_RK3288
  167. default 0xff738200 if ROCKCHIP_RK3368
  168. default 0xff320300 if ROCKCHIP_RK3399
  169. default 0x10300580 if ROCKCHIP_RV1108
  170. default 0
  171. help
  172. The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
  173. according to the value from this register.
  174. config ROCKCHIP_SPL_RESERVE_IRAM
  175. hex "Size of IRAM reserved in SPL"
  176. default 0
  177. help
  178. SPL may need reserve memory for firmware loaded by SPL, whose load
  179. address is in IRAM and may overlay with SPL text area if not
  180. reserved.
  181. config ROCKCHIP_BROM_HELPER
  182. bool
  183. config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
  184. bool "SPL requires early-return (for RK3188-style BROM) to BROM"
  185. depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
  186. help
  187. Some Rockchip BROM variants (e.g. on the RK3188) load the
  188. first stage in segments and enter multiple times. E.g. on
  189. the RK3188, the first 1KB of the first stage are loaded
  190. first and entered; after returning to the BROM, the
  191. remainder of the first stage is loaded, but the BROM
  192. re-enters at the same address/to the same code as previously.
  193. This enables support code in the BOOT0 hook for the SPL stage
  194. to allow multiple entries.
  195. config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
  196. bool "TPL requires early-return (for RK3188-style BROM) to BROM"
  197. depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
  198. help
  199. Some Rockchip BROM variants (e.g. on the RK3188) load the
  200. first stage in segments and enter multiple times. E.g. on
  201. the RK3188, the first 1KB of the first stage are loaded
  202. first and entered; after returning to the BROM, the
  203. remainder of the first stage is loaded, but the BROM
  204. re-enters at the same address/to the same code as previously.
  205. This enables support code in the BOOT0 hook for the TPL stage
  206. to allow multiple entries.
  207. config SPL_MMC_SUPPORT
  208. default y if !SPL_ROCKCHIP_BACK_TO_BROM
  209. source "arch/arm/mach-rockchip/rk3036/Kconfig"
  210. source "arch/arm/mach-rockchip/rk3128/Kconfig"
  211. source "arch/arm/mach-rockchip/rk3188/Kconfig"
  212. source "arch/arm/mach-rockchip/rk322x/Kconfig"
  213. source "arch/arm/mach-rockchip/rk3288/Kconfig"
  214. source "arch/arm/mach-rockchip/rk3328/Kconfig"
  215. source "arch/arm/mach-rockchip/rk3368/Kconfig"
  216. source "arch/arm/mach-rockchip/rk3399/Kconfig"
  217. source "arch/arm/mach-rockchip/rv1108/Kconfig"
  218. endif