phy.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Generic PHY Management code
  4. *
  5. * Copyright 2011 Freescale Semiconductor, Inc.
  6. * author Andy Fleming
  7. *
  8. * Based loosely off of Linux's PHY Lib
  9. */
  10. #include <common.h>
  11. #include <console.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <net.h>
  16. #include <command.h>
  17. #include <miiphy.h>
  18. #include <phy.h>
  19. #include <errno.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/compiler.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. /* Generic PHY support and helper functions */
  26. /**
  27. * genphy_config_advert - sanitize and advertise auto-negotiation parameters
  28. * @phydev: target phy_device struct
  29. *
  30. * Description: Writes MII_ADVERTISE with the appropriate values,
  31. * after sanitizing the values to make sure we only advertise
  32. * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
  33. * hasn't changed, and > 0 if it has changed.
  34. */
  35. static int genphy_config_advert(struct phy_device *phydev)
  36. {
  37. u32 advertise;
  38. int oldadv, adv, bmsr;
  39. int err, changed = 0;
  40. /* Only allow advertising what this PHY supports */
  41. phydev->advertising &= phydev->supported;
  42. advertise = phydev->advertising;
  43. /* Setup standard advertisement */
  44. adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
  45. oldadv = adv;
  46. if (adv < 0)
  47. return adv;
  48. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
  49. ADVERTISE_PAUSE_ASYM);
  50. if (advertise & ADVERTISED_10baseT_Half)
  51. adv |= ADVERTISE_10HALF;
  52. if (advertise & ADVERTISED_10baseT_Full)
  53. adv |= ADVERTISE_10FULL;
  54. if (advertise & ADVERTISED_100baseT_Half)
  55. adv |= ADVERTISE_100HALF;
  56. if (advertise & ADVERTISED_100baseT_Full)
  57. adv |= ADVERTISE_100FULL;
  58. if (advertise & ADVERTISED_Pause)
  59. adv |= ADVERTISE_PAUSE_CAP;
  60. if (advertise & ADVERTISED_Asym_Pause)
  61. adv |= ADVERTISE_PAUSE_ASYM;
  62. if (advertise & ADVERTISED_1000baseX_Half)
  63. adv |= ADVERTISE_1000XHALF;
  64. if (advertise & ADVERTISED_1000baseX_Full)
  65. adv |= ADVERTISE_1000XFULL;
  66. if (adv != oldadv) {
  67. err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv);
  68. if (err < 0)
  69. return err;
  70. changed = 1;
  71. }
  72. bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  73. if (bmsr < 0)
  74. return bmsr;
  75. /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
  76. * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
  77. * logical 1.
  78. */
  79. if (!(bmsr & BMSR_ESTATEN))
  80. return changed;
  81. /* Configure gigabit if it's supported */
  82. adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
  83. oldadv = adv;
  84. if (adv < 0)
  85. return adv;
  86. adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  87. if (phydev->supported & (SUPPORTED_1000baseT_Half |
  88. SUPPORTED_1000baseT_Full)) {
  89. if (advertise & SUPPORTED_1000baseT_Half)
  90. adv |= ADVERTISE_1000HALF;
  91. if (advertise & SUPPORTED_1000baseT_Full)
  92. adv |= ADVERTISE_1000FULL;
  93. }
  94. if (adv != oldadv)
  95. changed = 1;
  96. err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv);
  97. if (err < 0)
  98. return err;
  99. return changed;
  100. }
  101. /**
  102. * genphy_setup_forced - configures/forces speed/duplex from @phydev
  103. * @phydev: target phy_device struct
  104. *
  105. * Description: Configures MII_BMCR to force speed/duplex
  106. * to the values in phydev. Assumes that the values are valid.
  107. */
  108. static int genphy_setup_forced(struct phy_device *phydev)
  109. {
  110. int err;
  111. int ctl = BMCR_ANRESTART;
  112. phydev->pause = 0;
  113. phydev->asym_pause = 0;
  114. if (phydev->speed == SPEED_1000)
  115. ctl |= BMCR_SPEED1000;
  116. else if (phydev->speed == SPEED_100)
  117. ctl |= BMCR_SPEED100;
  118. if (phydev->duplex == DUPLEX_FULL)
  119. ctl |= BMCR_FULLDPLX;
  120. err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
  121. return err;
  122. }
  123. /**
  124. * genphy_restart_aneg - Enable and Restart Autonegotiation
  125. * @phydev: target phy_device struct
  126. */
  127. int genphy_restart_aneg(struct phy_device *phydev)
  128. {
  129. int ctl;
  130. ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  131. if (ctl < 0)
  132. return ctl;
  133. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  134. /* Don't isolate the PHY if we're negotiating */
  135. ctl &= ~(BMCR_ISOLATE);
  136. ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
  137. return ctl;
  138. }
  139. /**
  140. * genphy_config_aneg - restart auto-negotiation or write BMCR
  141. * @phydev: target phy_device struct
  142. *
  143. * Description: If auto-negotiation is enabled, we configure the
  144. * advertising, and then restart auto-negotiation. If it is not
  145. * enabled, then we write the BMCR.
  146. */
  147. int genphy_config_aneg(struct phy_device *phydev)
  148. {
  149. int result;
  150. if (phydev->autoneg != AUTONEG_ENABLE)
  151. return genphy_setup_forced(phydev);
  152. result = genphy_config_advert(phydev);
  153. if (result < 0) /* error */
  154. return result;
  155. if (result == 0) {
  156. /*
  157. * Advertisment hasn't changed, but maybe aneg was never on to
  158. * begin with? Or maybe phy was isolated?
  159. */
  160. int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  161. if (ctl < 0)
  162. return ctl;
  163. if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
  164. result = 1; /* do restart aneg */
  165. }
  166. /*
  167. * Only restart aneg if we are advertising something different
  168. * than we were before.
  169. */
  170. if (result > 0)
  171. result = genphy_restart_aneg(phydev);
  172. return result;
  173. }
  174. /**
  175. * genphy_update_link - update link status in @phydev
  176. * @phydev: target phy_device struct
  177. *
  178. * Description: Update the value in phydev->link to reflect the
  179. * current link value. In order to do this, we need to read
  180. * the status register twice, keeping the second value.
  181. */
  182. int genphy_update_link(struct phy_device *phydev)
  183. {
  184. unsigned int mii_reg;
  185. /*
  186. * Wait if the link is up, and autonegotiation is in progress
  187. * (ie - we're capable and it's not done)
  188. */
  189. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  190. /*
  191. * If we already saw the link up, and it hasn't gone down, then
  192. * we don't need to wait for autoneg again
  193. */
  194. if (phydev->link && mii_reg & BMSR_LSTATUS)
  195. return 0;
  196. if ((phydev->autoneg == AUTONEG_ENABLE) &&
  197. !(mii_reg & BMSR_ANEGCOMPLETE)) {
  198. int i = 0;
  199. printf("%s Waiting for PHY auto negotiation to complete",
  200. phydev->dev->name);
  201. while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
  202. /*
  203. * Timeout reached ?
  204. */
  205. if (i > (PHY_ANEG_TIMEOUT / 50)) {
  206. printf(" TIMEOUT !\n");
  207. phydev->link = 0;
  208. return -ETIMEDOUT;
  209. }
  210. if (ctrlc()) {
  211. puts("user interrupt!\n");
  212. phydev->link = 0;
  213. return -EINTR;
  214. }
  215. if ((i++ % 10) == 0)
  216. printf(".");
  217. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  218. mdelay(50); /* 50 ms */
  219. }
  220. printf(" done\n");
  221. phydev->link = 1;
  222. } else {
  223. /* Read the link a second time to clear the latched state */
  224. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  225. if (mii_reg & BMSR_LSTATUS)
  226. phydev->link = 1;
  227. else
  228. phydev->link = 0;
  229. }
  230. return 0;
  231. }
  232. /*
  233. * Generic function which updates the speed and duplex. If
  234. * autonegotiation is enabled, it uses the AND of the link
  235. * partner's advertised capabilities and our advertised
  236. * capabilities. If autonegotiation is disabled, we use the
  237. * appropriate bits in the control register.
  238. *
  239. * Stolen from Linux's mii.c and phy_device.c
  240. */
  241. int genphy_parse_link(struct phy_device *phydev)
  242. {
  243. int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  244. /* We're using autonegotiation */
  245. if (phydev->autoneg == AUTONEG_ENABLE) {
  246. u32 lpa = 0;
  247. int gblpa = 0;
  248. u32 estatus = 0;
  249. /* Check for gigabit capability */
  250. if (phydev->supported & (SUPPORTED_1000baseT_Full |
  251. SUPPORTED_1000baseT_Half)) {
  252. /* We want a list of states supported by
  253. * both PHYs in the link
  254. */
  255. gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
  256. if (gblpa < 0) {
  257. debug("Could not read MII_STAT1000. ");
  258. debug("Ignoring gigabit capability\n");
  259. gblpa = 0;
  260. }
  261. gblpa &= phy_read(phydev,
  262. MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
  263. }
  264. /* Set the baseline so we only have to set them
  265. * if they're different
  266. */
  267. phydev->speed = SPEED_10;
  268. phydev->duplex = DUPLEX_HALF;
  269. /* Check the gigabit fields */
  270. if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
  271. phydev->speed = SPEED_1000;
  272. if (gblpa & PHY_1000BTSR_1000FD)
  273. phydev->duplex = DUPLEX_FULL;
  274. /* We're done! */
  275. return 0;
  276. }
  277. lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
  278. lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
  279. if (lpa & (LPA_100FULL | LPA_100HALF)) {
  280. phydev->speed = SPEED_100;
  281. if (lpa & LPA_100FULL)
  282. phydev->duplex = DUPLEX_FULL;
  283. } else if (lpa & LPA_10FULL) {
  284. phydev->duplex = DUPLEX_FULL;
  285. }
  286. /*
  287. * Extended status may indicate that the PHY supports
  288. * 1000BASE-T/X even though the 1000BASE-T registers
  289. * are missing. In this case we can't tell whether the
  290. * peer also supports it, so we only check extended
  291. * status if the 1000BASE-T registers are actually
  292. * missing.
  293. */
  294. if ((mii_reg & BMSR_ESTATEN) && !(mii_reg & BMSR_ERCAP))
  295. estatus = phy_read(phydev, MDIO_DEVAD_NONE,
  296. MII_ESTATUS);
  297. if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_XHALF |
  298. ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
  299. phydev->speed = SPEED_1000;
  300. if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_TFULL))
  301. phydev->duplex = DUPLEX_FULL;
  302. }
  303. } else {
  304. u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  305. phydev->speed = SPEED_10;
  306. phydev->duplex = DUPLEX_HALF;
  307. if (bmcr & BMCR_FULLDPLX)
  308. phydev->duplex = DUPLEX_FULL;
  309. if (bmcr & BMCR_SPEED1000)
  310. phydev->speed = SPEED_1000;
  311. else if (bmcr & BMCR_SPEED100)
  312. phydev->speed = SPEED_100;
  313. }
  314. return 0;
  315. }
  316. int genphy_config(struct phy_device *phydev)
  317. {
  318. int val;
  319. u32 features;
  320. features = (SUPPORTED_TP | SUPPORTED_MII
  321. | SUPPORTED_AUI | SUPPORTED_FIBRE |
  322. SUPPORTED_BNC);
  323. /* Do we support autonegotiation? */
  324. val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  325. if (val < 0)
  326. return val;
  327. if (val & BMSR_ANEGCAPABLE)
  328. features |= SUPPORTED_Autoneg;
  329. if (val & BMSR_100FULL)
  330. features |= SUPPORTED_100baseT_Full;
  331. if (val & BMSR_100HALF)
  332. features |= SUPPORTED_100baseT_Half;
  333. if (val & BMSR_10FULL)
  334. features |= SUPPORTED_10baseT_Full;
  335. if (val & BMSR_10HALF)
  336. features |= SUPPORTED_10baseT_Half;
  337. if (val & BMSR_ESTATEN) {
  338. val = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS);
  339. if (val < 0)
  340. return val;
  341. if (val & ESTATUS_1000_TFULL)
  342. features |= SUPPORTED_1000baseT_Full;
  343. if (val & ESTATUS_1000_THALF)
  344. features |= SUPPORTED_1000baseT_Half;
  345. if (val & ESTATUS_1000_XFULL)
  346. features |= SUPPORTED_1000baseX_Full;
  347. if (val & ESTATUS_1000_XHALF)
  348. features |= SUPPORTED_1000baseX_Half;
  349. }
  350. phydev->supported &= features;
  351. phydev->advertising &= features;
  352. genphy_config_aneg(phydev);
  353. return 0;
  354. }
  355. int genphy_startup(struct phy_device *phydev)
  356. {
  357. int ret;
  358. ret = genphy_update_link(phydev);
  359. if (ret)
  360. return ret;
  361. return genphy_parse_link(phydev);
  362. }
  363. int genphy_shutdown(struct phy_device *phydev)
  364. {
  365. return 0;
  366. }
  367. static struct phy_driver genphy_driver = {
  368. .uid = 0xffffffff,
  369. .mask = 0xffffffff,
  370. .name = "Generic PHY",
  371. .features = PHY_GBIT_FEATURES | SUPPORTED_MII |
  372. SUPPORTED_AUI | SUPPORTED_FIBRE |
  373. SUPPORTED_BNC,
  374. .config = genphy_config,
  375. .startup = genphy_startup,
  376. .shutdown = genphy_shutdown,
  377. };
  378. int genphy_init(void)
  379. {
  380. return phy_register(&genphy_driver);
  381. }
  382. static LIST_HEAD(phy_drivers);
  383. int phy_init(void)
  384. {
  385. #ifdef CONFIG_NEEDS_MANUAL_RELOC
  386. /*
  387. * The pointers inside phy_drivers also needs to be updated incase of
  388. * manual reloc, without which these points to some invalid
  389. * pre reloc address and leads to invalid accesses, hangs.
  390. */
  391. struct list_head *head = &phy_drivers;
  392. head->next = (void *)head->next + gd->reloc_off;
  393. head->prev = (void *)head->prev + gd->reloc_off;
  394. #endif
  395. #ifdef CONFIG_B53_SWITCH
  396. phy_b53_init();
  397. #endif
  398. #ifdef CONFIG_MV88E61XX_SWITCH
  399. phy_mv88e61xx_init();
  400. #endif
  401. #ifdef CONFIG_PHY_AQUANTIA
  402. phy_aquantia_init();
  403. #endif
  404. #ifdef CONFIG_PHY_ATHEROS
  405. phy_atheros_init();
  406. #endif
  407. #ifdef CONFIG_PHY_BROADCOM
  408. phy_broadcom_init();
  409. #endif
  410. #ifdef CONFIG_PHY_CORTINA
  411. phy_cortina_init();
  412. #endif
  413. #ifdef CONFIG_PHY_DAVICOM
  414. phy_davicom_init();
  415. #endif
  416. #ifdef CONFIG_PHY_ET1011C
  417. phy_et1011c_init();
  418. #endif
  419. #ifdef CONFIG_PHY_LXT
  420. phy_lxt_init();
  421. #endif
  422. #ifdef CONFIG_PHY_MARVELL
  423. phy_marvell_init();
  424. #endif
  425. #ifdef CONFIG_PHY_MICREL_KSZ8XXX
  426. phy_micrel_ksz8xxx_init();
  427. #endif
  428. #ifdef CONFIG_PHY_MICREL_KSZ90X1
  429. phy_micrel_ksz90x1_init();
  430. #endif
  431. #ifdef CONFIG_PHY_MESON_GXL
  432. phy_meson_gxl_init();
  433. #endif
  434. #ifdef CONFIG_PHY_NATSEMI
  435. phy_natsemi_init();
  436. #endif
  437. #ifdef CONFIG_PHY_REALTEK
  438. phy_realtek_init();
  439. #endif
  440. #ifdef CONFIG_PHY_SMSC
  441. phy_smsc_init();
  442. #endif
  443. #ifdef CONFIG_PHY_TERANETICS
  444. phy_teranetics_init();
  445. #endif
  446. #ifdef CONFIG_PHY_TI
  447. phy_ti_init();
  448. #endif
  449. #ifdef CONFIG_PHY_VITESSE
  450. phy_vitesse_init();
  451. #endif
  452. #ifdef CONFIG_PHY_XILINX
  453. phy_xilinx_init();
  454. #endif
  455. #ifdef CONFIG_PHY_MSCC
  456. phy_mscc_init();
  457. #endif
  458. #ifdef CONFIG_PHY_FIXED
  459. phy_fixed_init();
  460. #endif
  461. #ifdef CONFIG_PHY_NCSI
  462. phy_ncsi_init();
  463. #endif
  464. #ifdef CONFIG_PHY_XILINX_GMII2RGMII
  465. phy_xilinx_gmii2rgmii_init();
  466. #endif
  467. genphy_init();
  468. return 0;
  469. }
  470. int phy_register(struct phy_driver *drv)
  471. {
  472. INIT_LIST_HEAD(&drv->list);
  473. list_add_tail(&drv->list, &phy_drivers);
  474. #ifdef CONFIG_NEEDS_MANUAL_RELOC
  475. if (drv->probe)
  476. drv->probe += gd->reloc_off;
  477. if (drv->config)
  478. drv->config += gd->reloc_off;
  479. if (drv->startup)
  480. drv->startup += gd->reloc_off;
  481. if (drv->shutdown)
  482. drv->shutdown += gd->reloc_off;
  483. if (drv->readext)
  484. drv->readext += gd->reloc_off;
  485. if (drv->writeext)
  486. drv->writeext += gd->reloc_off;
  487. if (drv->read_mmd)
  488. drv->read_mmd += gd->reloc_off;
  489. if (drv->write_mmd)
  490. drv->write_mmd += gd->reloc_off;
  491. #endif
  492. return 0;
  493. }
  494. int phy_set_supported(struct phy_device *phydev, u32 max_speed)
  495. {
  496. /* The default values for phydev->supported are provided by the PHY
  497. * driver "features" member, we want to reset to sane defaults first
  498. * before supporting higher speeds.
  499. */
  500. phydev->supported &= PHY_DEFAULT_FEATURES;
  501. switch (max_speed) {
  502. default:
  503. return -ENOTSUPP;
  504. case SPEED_1000:
  505. phydev->supported |= PHY_1000BT_FEATURES;
  506. /* fall through */
  507. case SPEED_100:
  508. phydev->supported |= PHY_100BT_FEATURES;
  509. /* fall through */
  510. case SPEED_10:
  511. phydev->supported |= PHY_10BT_FEATURES;
  512. }
  513. return 0;
  514. }
  515. static int phy_probe(struct phy_device *phydev)
  516. {
  517. int err = 0;
  518. phydev->advertising = phydev->drv->features;
  519. phydev->supported = phydev->drv->features;
  520. phydev->mmds = phydev->drv->mmds;
  521. if (phydev->drv->probe)
  522. err = phydev->drv->probe(phydev);
  523. return err;
  524. }
  525. static struct phy_driver *generic_for_interface(phy_interface_t interface)
  526. {
  527. #ifdef CONFIG_PHYLIB_10G
  528. if (is_10g_interface(interface))
  529. return &gen10g_driver;
  530. #endif
  531. return &genphy_driver;
  532. }
  533. static struct phy_driver *get_phy_driver(struct phy_device *phydev,
  534. phy_interface_t interface)
  535. {
  536. struct list_head *entry;
  537. int phy_id = phydev->phy_id;
  538. struct phy_driver *drv = NULL;
  539. list_for_each(entry, &phy_drivers) {
  540. drv = list_entry(entry, struct phy_driver, list);
  541. if ((drv->uid & drv->mask) == (phy_id & drv->mask))
  542. return drv;
  543. }
  544. /* If we made it here, there's no driver for this PHY */
  545. return generic_for_interface(interface);
  546. }
  547. static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
  548. u32 phy_id, bool is_c45,
  549. phy_interface_t interface)
  550. {
  551. struct phy_device *dev;
  552. /*
  553. * We allocate the device, and initialize the
  554. * default values
  555. */
  556. dev = malloc(sizeof(*dev));
  557. if (!dev) {
  558. printf("Failed to allocate PHY device for %s:%d\n",
  559. bus ? bus->name : "(null bus)", addr);
  560. return NULL;
  561. }
  562. memset(dev, 0, sizeof(*dev));
  563. dev->duplex = -1;
  564. dev->link = 0;
  565. dev->interface = interface;
  566. #ifdef CONFIG_DM_ETH
  567. dev->node = ofnode_null();
  568. #endif
  569. dev->autoneg = AUTONEG_ENABLE;
  570. dev->addr = addr;
  571. dev->phy_id = phy_id;
  572. dev->is_c45 = is_c45;
  573. dev->bus = bus;
  574. dev->drv = get_phy_driver(dev, interface);
  575. if (phy_probe(dev)) {
  576. printf("%s, PHY probe failed\n", __func__);
  577. return NULL;
  578. }
  579. if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
  580. bus->phymap[addr] = dev;
  581. return dev;
  582. }
  583. /**
  584. * get_phy_id - reads the specified addr for its ID.
  585. * @bus: the target MII bus
  586. * @addr: PHY address on the MII bus
  587. * @phy_id: where to store the ID retrieved.
  588. *
  589. * Description: Reads the ID registers of the PHY at @addr on the
  590. * @bus, stores it in @phy_id and returns zero on success.
  591. */
  592. int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
  593. {
  594. int phy_reg;
  595. /*
  596. * Grab the bits from PHYIR1, and put them
  597. * in the upper half
  598. */
  599. phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  600. if (phy_reg < 0)
  601. return -EIO;
  602. *phy_id = (phy_reg & 0xffff) << 16;
  603. /* Grab the bits from PHYIR2, and put them in the lower half */
  604. phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  605. if (phy_reg < 0)
  606. return -EIO;
  607. *phy_id |= (phy_reg & 0xffff);
  608. return 0;
  609. }
  610. static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
  611. uint phy_mask, int devad,
  612. phy_interface_t interface)
  613. {
  614. u32 phy_id = 0xffffffff;
  615. bool is_c45;
  616. while (phy_mask) {
  617. int addr = ffs(phy_mask) - 1;
  618. int r = get_phy_id(bus, addr, devad, &phy_id);
  619. /*
  620. * If the PHY ID is flat 0 we ignore it. There are C45 PHYs
  621. * that return all 0s for C22 reads (like Aquantia AQR112) and
  622. * there are C22 PHYs that return all 0s for C45 reads (like
  623. * Atheros AR8035).
  624. */
  625. if (r == 0 && phy_id == 0)
  626. goto next;
  627. /* If the PHY ID is mostly f's, we didn't find anything */
  628. if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) {
  629. is_c45 = (devad == MDIO_DEVAD_NONE) ? false : true;
  630. return phy_device_create(bus, addr, phy_id, is_c45,
  631. interface);
  632. }
  633. next:
  634. phy_mask &= ~(1 << addr);
  635. }
  636. return NULL;
  637. }
  638. static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
  639. uint phy_mask,
  640. phy_interface_t interface)
  641. {
  642. /* If we have one, return the existing device, with new interface */
  643. while (phy_mask) {
  644. int addr = ffs(phy_mask) - 1;
  645. if (bus->phymap[addr]) {
  646. bus->phymap[addr]->interface = interface;
  647. return bus->phymap[addr];
  648. }
  649. phy_mask &= ~(1 << addr);
  650. }
  651. return NULL;
  652. }
  653. static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
  654. uint phy_mask,
  655. phy_interface_t interface)
  656. {
  657. struct phy_device *phydev;
  658. int devad[] = {
  659. /* Clause-22 */
  660. MDIO_DEVAD_NONE,
  661. /* Clause-45 */
  662. MDIO_MMD_PMAPMD,
  663. MDIO_MMD_WIS,
  664. MDIO_MMD_PCS,
  665. MDIO_MMD_PHYXS,
  666. MDIO_MMD_VEND1,
  667. };
  668. int i, devad_cnt;
  669. devad_cnt = sizeof(devad)/sizeof(int);
  670. phydev = search_for_existing_phy(bus, phy_mask, interface);
  671. if (phydev)
  672. return phydev;
  673. /* try different access clauses */
  674. for (i = 0; i < devad_cnt; i++) {
  675. phydev = create_phy_by_mask(bus, phy_mask,
  676. devad[i], interface);
  677. if (IS_ERR(phydev))
  678. return NULL;
  679. if (phydev)
  680. return phydev;
  681. }
  682. debug("\n%s PHY: ", bus->name);
  683. while (phy_mask) {
  684. int addr = ffs(phy_mask) - 1;
  685. debug("%d ", addr);
  686. phy_mask &= ~(1 << addr);
  687. }
  688. debug("not found\n");
  689. return NULL;
  690. }
  691. /**
  692. * get_phy_device - reads the specified PHY device and returns its
  693. * @phy_device struct
  694. * @bus: the target MII bus
  695. * @addr: PHY address on the MII bus
  696. *
  697. * Description: Reads the ID registers of the PHY at @addr on the
  698. * @bus, then allocates and returns the phy_device to represent it.
  699. */
  700. static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
  701. phy_interface_t interface)
  702. {
  703. return get_phy_device_by_mask(bus, 1 << addr, interface);
  704. }
  705. int phy_reset(struct phy_device *phydev)
  706. {
  707. int reg;
  708. int timeout = 500;
  709. int devad = MDIO_DEVAD_NONE;
  710. if (phydev->flags & PHY_FLAG_BROKEN_RESET)
  711. return 0;
  712. #ifdef CONFIG_PHYLIB_10G
  713. /* If it's 10G, we need to issue reset through one of the MMDs */
  714. if (is_10g_interface(phydev->interface)) {
  715. if (!phydev->mmds)
  716. gen10g_discover_mmds(phydev);
  717. devad = ffs(phydev->mmds) - 1;
  718. }
  719. #endif
  720. if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) {
  721. debug("PHY reset failed\n");
  722. return -1;
  723. }
  724. #ifdef CONFIG_PHY_RESET_DELAY
  725. udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
  726. #endif
  727. /*
  728. * Poll the control register for the reset bit to go to 0 (it is
  729. * auto-clearing). This should happen within 0.5 seconds per the
  730. * IEEE spec.
  731. */
  732. reg = phy_read(phydev, devad, MII_BMCR);
  733. while ((reg & BMCR_RESET) && timeout--) {
  734. reg = phy_read(phydev, devad, MII_BMCR);
  735. if (reg < 0) {
  736. debug("PHY status read failed\n");
  737. return -1;
  738. }
  739. udelay(1000);
  740. }
  741. if (reg & BMCR_RESET) {
  742. puts("PHY reset timed out\n");
  743. return -1;
  744. }
  745. return 0;
  746. }
  747. int miiphy_reset(const char *devname, unsigned char addr)
  748. {
  749. struct mii_dev *bus = miiphy_get_dev_by_name(devname);
  750. struct phy_device *phydev;
  751. /*
  752. * miiphy_reset was only used on standard PHYs, so we'll fake it here.
  753. * If later code tries to connect with the right interface, this will
  754. * be corrected by get_phy_device in phy_connect()
  755. */
  756. phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII);
  757. return phy_reset(phydev);
  758. }
  759. struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask,
  760. phy_interface_t interface)
  761. {
  762. /* Reset the bus */
  763. if (bus->reset) {
  764. bus->reset(bus);
  765. /* Wait 15ms to make sure the PHY has come out of hard reset */
  766. mdelay(15);
  767. }
  768. return get_phy_device_by_mask(bus, phy_mask, interface);
  769. }
  770. #ifdef CONFIG_DM_ETH
  771. void phy_connect_dev(struct phy_device *phydev, struct udevice *dev)
  772. #else
  773. void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
  774. #endif
  775. {
  776. /* Soft Reset the PHY */
  777. phy_reset(phydev);
  778. if (phydev->dev && phydev->dev != dev) {
  779. printf("%s:%d is connected to %s. Reconnecting to %s\n",
  780. phydev->bus->name, phydev->addr,
  781. phydev->dev->name, dev->name);
  782. }
  783. phydev->dev = dev;
  784. debug("%s connected to %s\n", dev->name, phydev->drv->name);
  785. }
  786. #ifdef CONFIG_PHY_XILINX_GMII2RGMII
  787. #ifdef CONFIG_DM_ETH
  788. static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
  789. struct udevice *dev,
  790. phy_interface_t interface)
  791. #else
  792. static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
  793. struct eth_device *dev,
  794. phy_interface_t interface)
  795. #endif
  796. {
  797. struct phy_device *phydev = NULL;
  798. int sn = dev_of_offset(dev);
  799. int off;
  800. while (sn > 0) {
  801. off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
  802. "xlnx,gmii-to-rgmii-1.0");
  803. if (off > 0) {
  804. phydev = phy_device_create(bus, off,
  805. PHY_GMII2RGMII_ID, false,
  806. interface);
  807. break;
  808. }
  809. if (off == -FDT_ERR_NOTFOUND)
  810. sn = fdt_first_subnode(gd->fdt_blob, sn);
  811. else
  812. printf("%s: Error finding compat string:%d\n",
  813. __func__, off);
  814. }
  815. return phydev;
  816. }
  817. #endif
  818. #ifdef CONFIG_PHY_FIXED
  819. #ifdef CONFIG_DM_ETH
  820. static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
  821. struct udevice *dev,
  822. phy_interface_t interface)
  823. #else
  824. static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
  825. struct eth_device *dev,
  826. phy_interface_t interface)
  827. #endif
  828. {
  829. struct phy_device *phydev = NULL;
  830. int sn;
  831. const char *name;
  832. sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
  833. while (sn > 0) {
  834. name = fdt_get_name(gd->fdt_blob, sn, NULL);
  835. if (name && strcmp(name, "fixed-link") == 0) {
  836. phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false,
  837. interface);
  838. break;
  839. }
  840. sn = fdt_next_subnode(gd->fdt_blob, sn);
  841. }
  842. return phydev;
  843. }
  844. #endif
  845. #ifdef CONFIG_DM_ETH
  846. struct phy_device *phy_connect(struct mii_dev *bus, int addr,
  847. struct udevice *dev,
  848. phy_interface_t interface)
  849. #else
  850. struct phy_device *phy_connect(struct mii_dev *bus, int addr,
  851. struct eth_device *dev,
  852. phy_interface_t interface)
  853. #endif
  854. {
  855. struct phy_device *phydev = NULL;
  856. uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff;
  857. #ifdef CONFIG_PHY_FIXED
  858. phydev = phy_connect_fixed(bus, dev, interface);
  859. #endif
  860. #ifdef CONFIG_PHY_NCSI
  861. if (!phydev)
  862. phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false, interface);
  863. #endif
  864. #ifdef CONFIG_PHY_XILINX_GMII2RGMII
  865. if (!phydev)
  866. phydev = phy_connect_gmii2rgmii(bus, dev, interface);
  867. #endif
  868. if (!phydev)
  869. phydev = phy_find_by_mask(bus, mask, interface);
  870. if (phydev)
  871. phy_connect_dev(phydev, dev);
  872. else
  873. printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
  874. return phydev;
  875. }
  876. /*
  877. * Start the PHY. Returns 0 on success, or a negative error code.
  878. */
  879. int phy_startup(struct phy_device *phydev)
  880. {
  881. if (phydev->drv->startup)
  882. return phydev->drv->startup(phydev);
  883. return 0;
  884. }
  885. __weak int board_phy_config(struct phy_device *phydev)
  886. {
  887. if (phydev->drv->config)
  888. return phydev->drv->config(phydev);
  889. return 0;
  890. }
  891. int phy_config(struct phy_device *phydev)
  892. {
  893. /* Invoke an optional board-specific helper */
  894. return board_phy_config(phydev);
  895. }
  896. int phy_shutdown(struct phy_device *phydev)
  897. {
  898. if (phydev->drv->shutdown)
  899. phydev->drv->shutdown(phydev);
  900. return 0;
  901. }
  902. int phy_get_interface_by_name(const char *str)
  903. {
  904. int i;
  905. for (i = 0; i < PHY_INTERFACE_MODE_COUNT; i++) {
  906. if (!strcmp(str, phy_interface_strings[i]))
  907. return i;
  908. }
  909. return -1;
  910. }