xhci.h 43 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * USB HOST XHCI Controller
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. #ifndef HOST_XHCI_H_
  16. #define HOST_XHCI_H_
  17. #include <asm/types.h>
  18. #include <asm/cache.h>
  19. #include <asm/io.h>
  20. #include <linux/list.h>
  21. #include <linux/compat.h>
  22. #define MAX_EP_CTX_NUM 31
  23. #define XHCI_ALIGNMENT 64
  24. /* Generic timeout for XHCI events */
  25. #define XHCI_TIMEOUT 5000
  26. /* Max number of USB devices for any host controller - limit in section 6.1 */
  27. #define MAX_HC_SLOTS 256
  28. /* Section 5.3.3 - MaxPorts */
  29. #define MAX_HC_PORTS 255
  30. /* Up to 16 ms to halt an HC */
  31. #define XHCI_MAX_HALT_USEC (16*1000)
  32. #define XHCI_MAX_RESET_USEC (250*1000)
  33. /*
  34. * These bits are Read Only (RO) and should be saved and written to the
  35. * registers: 0, 3, 10:13, 30
  36. * connect status, over-current status, port speed, and device removable.
  37. * connect status and port speed are also sticky - meaning they're in
  38. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  39. */
  40. #define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30))
  41. /*
  42. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  43. * bits 5:8, 9, 14:15, 25:27
  44. * link state, port power, port indicator state, "wake on" enable state
  45. */
  46. #define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25))
  47. /*
  48. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  49. * bit 4 (port reset)
  50. */
  51. #define XHCI_PORT_RW1S ((1 << 4))
  52. /*
  53. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  54. * bits 1, 17, 18, 19, 20, 21, 22, 23
  55. * port enable/disable, and
  56. * change bits: connect, PED,
  57. * warm port reset changed (reserved zero for USB 2.0 ports),
  58. * over-current, reset, link state, and L1 change
  59. */
  60. #define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17))
  61. /*
  62. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  63. * latched in
  64. */
  65. #define XHCI_PORT_RW ((1 << 16))
  66. /*
  67. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  68. * bits 2, 24, 28:31
  69. */
  70. #define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28))
  71. /*
  72. * XHCI Register Space.
  73. */
  74. struct xhci_hccr {
  75. uint32_t cr_capbase;
  76. uint32_t cr_hcsparams1;
  77. uint32_t cr_hcsparams2;
  78. uint32_t cr_hcsparams3;
  79. uint32_t cr_hccparams;
  80. uint32_t cr_dboff;
  81. uint32_t cr_rtsoff;
  82. /* hc_capbase bitmasks */
  83. /* bits 7:0 - how long is the Capabilities register */
  84. #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
  85. /* bits 31:16 */
  86. #define HC_VERSION(p) (((p) >> 16) & 0xffff)
  87. /* HCSPARAMS1 - hcs_params1 - bitmasks */
  88. /* bits 0:7, Max Device Slots */
  89. #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
  90. #define HCS_SLOTS_MASK 0xff
  91. /* bits 8:18, Max Interrupters */
  92. #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
  93. /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
  94. #define HCS_MAX_PORTS_SHIFT 24
  95. #define HCS_MAX_PORTS_MASK (0xff << HCS_MAX_PORTS_SHIFT)
  96. #define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff)
  97. /* HCSPARAMS2 - hcs_params2 - bitmasks */
  98. /* bits 0:3, frames or uframes that SW needs to queue transactions
  99. * ahead of the HW to meet periodic deadlines */
  100. #define HCS_IST(p) (((p) >> 0) & 0xf)
  101. /* bits 4:7, max number of Event Ring segments */
  102. #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
  103. /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
  104. /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
  105. /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
  106. #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
  107. /* HCSPARAMS3 - hcs_params3 - bitmasks */
  108. /* bits 0:7, Max U1 to U0 latency for the roothub ports */
  109. #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
  110. /* bits 16:31, Max U2 to U0 latency for the roothub ports */
  111. #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
  112. /* HCCPARAMS - hcc_params - bitmasks */
  113. /* true: HC can use 64-bit address pointers */
  114. #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
  115. /* true: HC can do bandwidth negotiation */
  116. #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
  117. /* true: HC uses 64-byte Device Context structures
  118. * FIXME 64-byte context structures aren't supported yet.
  119. */
  120. #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
  121. /* true: HC has port power switches */
  122. #define HCC_PPC(p) ((p) & (1 << 3))
  123. /* true: HC has port indicators */
  124. #define HCS_INDICATOR(p) ((p) & (1 << 4))
  125. /* true: HC has Light HC Reset Capability */
  126. #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
  127. /* true: HC supports latency tolerance messaging */
  128. #define HCC_LTC(p) ((p) & (1 << 6))
  129. /* true: no secondary Stream ID Support */
  130. #define HCC_NSS(p) ((p) & (1 << 7))
  131. /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
  132. #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
  133. /* Extended Capabilities pointer from PCI base - section 5.3.6 */
  134. #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
  135. /* db_off bitmask - bits 0:1 reserved */
  136. #define DBOFF_MASK (~0x3)
  137. /* run_regs_off bitmask - bits 0:4 reserved */
  138. #define RTSOFF_MASK (~0x1f)
  139. };
  140. struct xhci_hcor_port_regs {
  141. volatile uint32_t or_portsc;
  142. volatile uint32_t or_portpmsc;
  143. volatile uint32_t or_portli;
  144. volatile uint32_t reserved_3;
  145. };
  146. struct xhci_hcor {
  147. volatile uint32_t or_usbcmd;
  148. volatile uint32_t or_usbsts;
  149. volatile uint32_t or_pagesize;
  150. volatile uint32_t reserved_0[2];
  151. volatile uint32_t or_dnctrl;
  152. volatile uint64_t or_crcr;
  153. volatile uint32_t reserved_1[4];
  154. volatile uint64_t or_dcbaap;
  155. volatile uint32_t or_config;
  156. volatile uint32_t reserved_2[241];
  157. struct xhci_hcor_port_regs portregs[MAX_HC_PORTS];
  158. };
  159. /* USBCMD - USB command - command bitmasks */
  160. /* start/stop HC execution - do not write unless HC is halted*/
  161. #define CMD_RUN XHCI_CMD_RUN
  162. /* Reset HC - resets internal HC state machine and all registers (except
  163. * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
  164. * The xHCI driver must reinitialize the xHC after setting this bit.
  165. */
  166. #define CMD_RESET (1 << 1)
  167. /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
  168. #define CMD_EIE XHCI_CMD_EIE
  169. /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
  170. #define CMD_HSEIE XHCI_CMD_HSEIE
  171. /* bits 4:6 are reserved (and should be preserved on writes). */
  172. /* light reset (port status stays unchanged) - reset completed when this is 0 */
  173. #define CMD_LRESET (1 << 7)
  174. /* host controller save/restore state. */
  175. #define CMD_CSS (1 << 8)
  176. #define CMD_CRS (1 << 9)
  177. /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
  178. #define CMD_EWE XHCI_CMD_EWE
  179. /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
  180. * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
  181. * '0' means the xHC can power it off if all ports are in the disconnect,
  182. * disabled, or powered-off state.
  183. */
  184. #define CMD_PM_INDEX (1 << 11)
  185. /* bits 12:31 are reserved (and should be preserved on writes). */
  186. /* USBSTS - USB status - status bitmasks */
  187. /* HC not running - set to 1 when run/stop bit is cleared. */
  188. #define STS_HALT XHCI_STS_HALT
  189. /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
  190. #define STS_FATAL (1 << 2)
  191. /* event interrupt - clear this prior to clearing any IP flags in IR set*/
  192. #define STS_EINT (1 << 3)
  193. /* port change detect */
  194. #define STS_PORT (1 << 4)
  195. /* bits 5:7 reserved and zeroed */
  196. /* save state status - '1' means xHC is saving state */
  197. #define STS_SAVE (1 << 8)
  198. /* restore state status - '1' means xHC is restoring state */
  199. #define STS_RESTORE (1 << 9)
  200. /* true: save or restore error */
  201. #define STS_SRE (1 << 10)
  202. /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
  203. #define STS_CNR XHCI_STS_CNR
  204. /* true: internal Host Controller Error - SW needs to reset and reinitialize */
  205. #define STS_HCE (1 << 12)
  206. /* bits 13:31 reserved and should be preserved */
  207. /*
  208. * DNCTRL - Device Notification Control Register - dev_notification bitmasks
  209. * Generate a device notification event when the HC sees a transaction with a
  210. * notification type that matches a bit set in this bit field.
  211. */
  212. #define DEV_NOTE_MASK (0xffff)
  213. #define ENABLE_DEV_NOTE(x) (1 << (x))
  214. /* Most of the device notification types should only be used for debug.
  215. * SW does need to pay attention to function wake notifications.
  216. */
  217. #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
  218. /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
  219. /* bit 0 is the command ring cycle state */
  220. /* stop ring operation after completion of the currently executing command */
  221. #define CMD_RING_PAUSE (1 << 1)
  222. /* stop ring immediately - abort the currently executing command */
  223. #define CMD_RING_ABORT (1 << 2)
  224. /* true: command ring is running */
  225. #define CMD_RING_RUNNING (1 << 3)
  226. /* bits 4:5 reserved and should be preserved */
  227. /* Command Ring pointer - bit mask for the lower 32 bits. */
  228. #define CMD_RING_RSVD_BITS (0x3f)
  229. /* CONFIG - Configure Register - config_reg bitmasks */
  230. /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
  231. #define MAX_DEVS(p) ((p) & 0xff)
  232. /* bits 8:31 - reserved and should be preserved */
  233. /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
  234. /* true: device connected */
  235. #define PORT_CONNECT (1 << 0)
  236. /* true: port enabled */
  237. #define PORT_PE (1 << 1)
  238. /* bit 2 reserved and zeroed */
  239. /* true: port has an over-current condition */
  240. #define PORT_OC (1 << 3)
  241. /* true: port reset signaling asserted */
  242. #define PORT_RESET (1 << 4)
  243. /* Port Link State - bits 5:8
  244. * A read gives the current link PM state of the port,
  245. * a write with Link State Write Strobe set sets the link state.
  246. */
  247. #define PORT_PLS_MASK (0xf << 5)
  248. #define XDEV_U0 (0x0 << 5)
  249. #define XDEV_U2 (0x2 << 5)
  250. #define XDEV_U3 (0x3 << 5)
  251. #define XDEV_RESUME (0xf << 5)
  252. /* true: port has power (see HCC_PPC) */
  253. #define PORT_POWER (1 << 9)
  254. /* bits 10:13 indicate device speed:
  255. * 0 - undefined speed - port hasn't be initialized by a reset yet
  256. * 1 - full speed
  257. * 2 - low speed
  258. * 3 - high speed
  259. * 4 - super speed
  260. * 5-15 reserved
  261. */
  262. #define DEV_SPEED_MASK (0xf << 10)
  263. #define XDEV_FS (0x1 << 10)
  264. #define XDEV_LS (0x2 << 10)
  265. #define XDEV_HS (0x3 << 10)
  266. #define XDEV_SS (0x4 << 10)
  267. #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
  268. #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
  269. #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
  270. #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
  271. #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
  272. /* Bits 20:23 in the Slot Context are the speed for the device */
  273. #define SLOT_SPEED_FS (XDEV_FS << 10)
  274. #define SLOT_SPEED_LS (XDEV_LS << 10)
  275. #define SLOT_SPEED_HS (XDEV_HS << 10)
  276. #define SLOT_SPEED_SS (XDEV_SS << 10)
  277. /* Port Indicator Control */
  278. #define PORT_LED_OFF (0 << 14)
  279. #define PORT_LED_AMBER (1 << 14)
  280. #define PORT_LED_GREEN (2 << 14)
  281. #define PORT_LED_MASK (3 << 14)
  282. /* Port Link State Write Strobe - set this when changing link state */
  283. #define PORT_LINK_STROBE (1 << 16)
  284. /* true: connect status change */
  285. #define PORT_CSC (1 << 17)
  286. /* true: port enable change */
  287. #define PORT_PEC (1 << 18)
  288. /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
  289. * into an enabled state, and the device into the default state. A "warm" reset
  290. * also resets the link, forcing the device through the link training sequence.
  291. * SW can also look at the Port Reset register to see when warm reset is done.
  292. */
  293. #define PORT_WRC (1 << 19)
  294. /* true: over-current change */
  295. #define PORT_OCC (1 << 20)
  296. /* true: reset change - 1 to 0 transition of PORT_RESET */
  297. #define PORT_RC (1 << 21)
  298. /* port link status change - set on some port link state transitions:
  299. * Transition Reason
  300. * --------------------------------------------------------------------------
  301. * - U3 to Resume Wakeup signaling from a device
  302. * - Resume to Recovery to U0 USB 3.0 device resume
  303. * - Resume to U0 USB 2.0 device resume
  304. * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
  305. * - U3 to U0 Software resume of USB 2.0 device complete
  306. * - U2 to U0 L1 resume of USB 2.1 device complete
  307. * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
  308. * - U0 to disabled L1 entry error with USB 2.1 device
  309. * - Any state to inactive Error on USB 3.0 port
  310. */
  311. #define PORT_PLC (1 << 22)
  312. /* port configure error change - port failed to configure its link partner */
  313. #define PORT_CEC (1 << 23)
  314. /* bit 24 reserved */
  315. /* wake on connect (enable) */
  316. #define PORT_WKCONN_E (1 << 25)
  317. /* wake on disconnect (enable) */
  318. #define PORT_WKDISC_E (1 << 26)
  319. /* wake on over-current (enable) */
  320. #define PORT_WKOC_E (1 << 27)
  321. /* bits 28:29 reserved */
  322. /* true: device is removable - for USB 3.0 roothub emulation */
  323. #define PORT_DEV_REMOVE (1 << 30)
  324. /* Initiate a warm port reset - complete when PORT_WRC is '1' */
  325. #define PORT_WR (1 << 31)
  326. /* We mark duplicate entries with -1 */
  327. #define DUPLICATE_ENTRY ((u8)(-1))
  328. /* Port Power Management Status and Control - port_power_base bitmasks */
  329. /* Inactivity timer value for transitions into U1, in microseconds.
  330. * Timeout can be up to 127us. 0xFF means an infinite timeout.
  331. */
  332. #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
  333. /* Inactivity timer value for transitions into U2 */
  334. #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
  335. /* Bits 24:31 for port testing */
  336. /* USB2 Protocol PORTSPMSC */
  337. #define PORT_L1S_MASK 7
  338. #define PORT_L1S_SUCCESS 1
  339. #define PORT_RWE (1 << 3)
  340. #define PORT_HIRD(p) (((p) & 0xf) << 4)
  341. #define PORT_HIRD_MASK (0xf << 4)
  342. #define PORT_L1DS(p) (((p) & 0xff) << 8)
  343. #define PORT_HLE (1 << 16)
  344. /**
  345. * struct xhci_intr_reg - Interrupt Register Set
  346. * @irq_pending: IMAN - Interrupt Management Register. Used to enable
  347. * interrupts and check for pending interrupts.
  348. * @irq_control: IMOD - Interrupt Moderation Register.
  349. * Used to throttle interrupts.
  350. * @erst_size: Number of segments in the
  351. Event Ring Segment Table (ERST).
  352. * @erst_base: ERST base address.
  353. * @erst_dequeue: Event ring dequeue pointer.
  354. *
  355. * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
  356. * Ring Segment Table (ERST) associated with it.
  357. * The event ring is comprised of multiple segments of the same size.
  358. * The HC places events on the ring and "updates the Cycle bit in the TRBs to
  359. * indicate to software the current position of the Enqueue Pointer."
  360. * The HCD (Linux) processes those events and updates the dequeue pointer.
  361. */
  362. struct xhci_intr_reg {
  363. volatile __le32 irq_pending;
  364. volatile __le32 irq_control;
  365. volatile __le32 erst_size;
  366. volatile __le32 rsvd;
  367. volatile __le64 erst_base;
  368. volatile __le64 erst_dequeue;
  369. };
  370. /* irq_pending bitmasks */
  371. #define ER_IRQ_PENDING(p) ((p) & 0x1)
  372. /* bits 2:31 need to be preserved */
  373. /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
  374. #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
  375. #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
  376. #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
  377. /* irq_control bitmasks */
  378. /* Minimum interval between interrupts (in 250ns intervals). The interval
  379. * between interrupts will be longer if there are no events on the event ring.
  380. * Default is 4000 (1 ms).
  381. */
  382. #define ER_IRQ_INTERVAL_MASK (0xffff)
  383. /* Counter used to count down the time to the next interrupt - HW use only */
  384. #define ER_IRQ_COUNTER_MASK (0xffff << 16)
  385. /* erst_size bitmasks */
  386. /* Preserve bits 16:31 of erst_size */
  387. #define ERST_SIZE_MASK (0xffff << 16)
  388. /* erst_dequeue bitmasks */
  389. /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
  390. * where the current dequeue pointer lies. This is an optional HW hint.
  391. */
  392. #define ERST_DESI_MASK (0x7)
  393. /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
  394. * a work queue (or delayed service routine)?
  395. */
  396. #define ERST_EHB (1 << 3)
  397. #define ERST_PTR_MASK (0xf)
  398. /**
  399. * struct xhci_run_regs
  400. * @microframe_index: MFINDEX - current microframe number
  401. *
  402. * Section 5.5 Host Controller Runtime Registers:
  403. * "Software should read and write these registers using only Dword (32 bit)
  404. * or larger accesses"
  405. */
  406. struct xhci_run_regs {
  407. __le32 microframe_index;
  408. __le32 rsvd[7];
  409. struct xhci_intr_reg ir_set[128];
  410. };
  411. /**
  412. * struct doorbell_array
  413. *
  414. * Bits 0 - 7: Endpoint target
  415. * Bits 8 - 15: RsvdZ
  416. * Bits 16 - 31: Stream ID
  417. *
  418. * Section 5.6
  419. */
  420. struct xhci_doorbell_array {
  421. volatile __le32 doorbell[256];
  422. };
  423. #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
  424. #define DB_VALUE_HOST 0x00000000
  425. /**
  426. * struct xhci_protocol_caps
  427. * @revision: major revision, minor revision, capability ID,
  428. * and next capability pointer.
  429. * @name_string: Four ASCII characters to say which spec this xHC
  430. * follows, typically "USB ".
  431. * @port_info: Port offset, count, and protocol-defined information.
  432. */
  433. struct xhci_protocol_caps {
  434. u32 revision;
  435. u32 name_string;
  436. u32 port_info;
  437. };
  438. #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
  439. #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
  440. #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
  441. /**
  442. * struct xhci_container_ctx
  443. * @type: Type of context. Used to calculated offsets to contained contexts.
  444. * @size: Size of the context data
  445. * @bytes: The raw context data given to HW
  446. *
  447. * Represents either a Device or Input context. Holds a pointer to the raw
  448. * memory used for the context (bytes).
  449. */
  450. struct xhci_container_ctx {
  451. unsigned type;
  452. #define XHCI_CTX_TYPE_DEVICE 0x1
  453. #define XHCI_CTX_TYPE_INPUT 0x2
  454. int size;
  455. u8 *bytes;
  456. };
  457. /**
  458. * struct xhci_slot_ctx
  459. * @dev_info: Route string, device speed, hub info, and last valid endpoint
  460. * @dev_info2: Max exit latency for device number, root hub port number
  461. * @tt_info: tt_info is used to construct split transaction tokens
  462. * @dev_state: slot state and device address
  463. *
  464. * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
  465. * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
  466. * reserved at the end of the slot context for HC internal use.
  467. */
  468. struct xhci_slot_ctx {
  469. __le32 dev_info;
  470. __le32 dev_info2;
  471. __le32 tt_info;
  472. __le32 dev_state;
  473. /* offset 0x10 to 0x1f reserved for HC internal use */
  474. __le32 reserved[4];
  475. };
  476. /* dev_info bitmasks */
  477. /* Route String - 0:19 */
  478. #define ROUTE_STRING_MASK (0xfffff)
  479. /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
  480. #define DEV_SPEED (0xf << 20)
  481. /* bit 24 reserved */
  482. /* Is this LS/FS device connected through a HS hub? - bit 25 */
  483. #define DEV_MTT (0x1 << 25)
  484. /* Set if the device is a hub - bit 26 */
  485. #define DEV_HUB (0x1 << 26)
  486. /* Index of the last valid endpoint context in this device context - 27:31 */
  487. #define LAST_CTX_MASK (0x1f << 27)
  488. #define LAST_CTX(p) ((p) << 27)
  489. #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
  490. #define SLOT_FLAG (1 << 0)
  491. #define EP0_FLAG (1 << 1)
  492. /* dev_info2 bitmasks */
  493. /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
  494. #define MAX_EXIT (0xffff)
  495. /* Root hub port number that is needed to access the USB device */
  496. #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
  497. #define ROOT_HUB_PORT_MASK (0xff)
  498. #define ROOT_HUB_PORT_SHIFT (16)
  499. #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
  500. /* Maximum number of ports under a hub device */
  501. #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
  502. /* tt_info bitmasks */
  503. /*
  504. * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
  505. * The Slot ID of the hub that isolates the high speed signaling from
  506. * this low or full-speed device. '0' if attached to root hub port.
  507. */
  508. #define TT_SLOT(p) (((p) & 0xff) << 0)
  509. /*
  510. * The number of the downstream facing port of the high-speed hub
  511. * '0' if the device is not low or full speed.
  512. */
  513. #define TT_PORT(p) (((p) & 0xff) << 8)
  514. #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
  515. /* dev_state bitmasks */
  516. /* USB device address - assigned by the HC */
  517. #define DEV_ADDR_MASK (0xff)
  518. /* bits 8:26 reserved */
  519. /* Slot state */
  520. #define SLOT_STATE (0x1f << 27)
  521. #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
  522. #define SLOT_STATE_DISABLED 0
  523. #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
  524. #define SLOT_STATE_DEFAULT 1
  525. #define SLOT_STATE_ADDRESSED 2
  526. #define SLOT_STATE_CONFIGURED 3
  527. /**
  528. * struct xhci_ep_ctx
  529. * @ep_info: endpoint state, streams, mult, and interval information.
  530. * @ep_info2: information on endpoint type, max packet size, max burst size,
  531. * error count, and whether the HC will force an event for all
  532. * transactions.
  533. * @deq: 64-bit ring dequeue pointer address. If the endpoint only
  534. * defines one stream, this points to the endpoint transfer ring.
  535. * Otherwise, it points to a stream context array, which has a
  536. * ring pointer for each flow.
  537. * @tx_info:
  538. * Average TRB lengths for the endpoint ring and
  539. * max payload within an Endpoint Service Interval Time (ESIT).
  540. *
  541. * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context
  542. * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes
  543. * reserved at the end of the endpoint context for HC internal use.
  544. */
  545. struct xhci_ep_ctx {
  546. __le32 ep_info;
  547. __le32 ep_info2;
  548. __le64 deq;
  549. __le32 tx_info;
  550. /* offset 0x14 - 0x1f reserved for HC internal use */
  551. __le32 reserved[3];
  552. };
  553. /* ep_info bitmasks */
  554. /*
  555. * Endpoint State - bits 0:2
  556. * 0 - disabled
  557. * 1 - running
  558. * 2 - halted due to halt condition - ok to manipulate endpoint ring
  559. * 3 - stopped
  560. * 4 - TRB error
  561. * 5-7 - reserved
  562. */
  563. #define EP_STATE_MASK (0xf)
  564. #define EP_STATE_DISABLED 0
  565. #define EP_STATE_RUNNING 1
  566. #define EP_STATE_HALTED 2
  567. #define EP_STATE_STOPPED 3
  568. #define EP_STATE_ERROR 4
  569. /* Mult - Max number of burtst within an interval, in EP companion desc. */
  570. #define EP_MULT(p) (((p) & 0x3) << 8)
  571. #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
  572. /* bits 10:14 are Max Primary Streams */
  573. /* bit 15 is Linear Stream Array */
  574. /* Interval - period between requests to an endpoint - 125u increments. */
  575. #define EP_INTERVAL(p) (((p) & 0xff) << 16)
  576. #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
  577. #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
  578. #define EP_MAXPSTREAMS_MASK (0x1f << 10)
  579. #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
  580. /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
  581. #define EP_HAS_LSA (1 << 15)
  582. /* ep_info2 bitmasks */
  583. /*
  584. * Force Event - generate transfer events for all TRBs for this endpoint
  585. * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
  586. */
  587. #define FORCE_EVENT (0x1)
  588. #define ERROR_COUNT(p) (((p) & 0x3) << 1)
  589. #define ERROR_COUNT_SHIFT (1)
  590. #define ERROR_COUNT_MASK (0x3)
  591. #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
  592. #define EP_TYPE(p) ((p) << 3)
  593. #define EP_TYPE_SHIFT (3)
  594. #define ISOC_OUT_EP 1
  595. #define BULK_OUT_EP 2
  596. #define INT_OUT_EP 3
  597. #define CTRL_EP 4
  598. #define ISOC_IN_EP 5
  599. #define BULK_IN_EP 6
  600. #define INT_IN_EP 7
  601. /* bit 6 reserved */
  602. /* bit 7 is Host Initiate Disable - for disabling stream selection */
  603. #define MAX_BURST(p) (((p)&0xff) << 8)
  604. #define MAX_BURST_MASK (0xff)
  605. #define MAX_BURST_SHIFT (8)
  606. #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
  607. #define MAX_PACKET(p) (((p)&0xffff) << 16)
  608. #define MAX_PACKET_MASK (0xffff)
  609. #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
  610. #define MAX_PACKET_SHIFT (16)
  611. /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
  612. * USB2.0 spec 9.6.6.
  613. */
  614. #define GET_MAX_PACKET(p) ((p) & 0x7ff)
  615. /* tx_info bitmasks */
  616. #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
  617. #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
  618. #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
  619. #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
  620. /* deq bitmasks */
  621. #define EP_CTX_CYCLE_MASK (1 << 0)
  622. /**
  623. * struct xhci_input_control_context
  624. * Input control context; see section 6.2.5.
  625. *
  626. * @drop_context: set the bit of the endpoint context you want to disable
  627. * @add_context: set the bit of the endpoint context you want to enable
  628. */
  629. struct xhci_input_control_ctx {
  630. volatile __le32 drop_flags;
  631. volatile __le32 add_flags;
  632. __le32 rsvd2[6];
  633. };
  634. /**
  635. * struct xhci_device_context_array
  636. * @dev_context_ptr array of 64-bit DMA addresses for device contexts
  637. */
  638. struct xhci_device_context_array {
  639. /* 64-bit device addresses; we only write 32-bit addresses */
  640. __le64 dev_context_ptrs[MAX_HC_SLOTS];
  641. };
  642. /* TODO: write function to set the 64-bit device DMA address */
  643. /*
  644. * TODO: change this to be dynamically sized at HC mem init time since the HC
  645. * might not be able to handle the maximum number of devices possible.
  646. */
  647. struct xhci_transfer_event {
  648. /* 64-bit buffer address, or immediate data */
  649. __le64 buffer;
  650. __le32 transfer_len;
  651. /* This field is interpreted differently based on the type of TRB */
  652. volatile __le32 flags;
  653. };
  654. /* Transfer event TRB length bit mask */
  655. /* bits 0:23 */
  656. #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
  657. /** Transfer Event bit fields **/
  658. #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
  659. /* Completion Code - only applicable for some types of TRBs */
  660. #define COMP_CODE_MASK (0xff << 24)
  661. #define COMP_CODE_SHIFT (24)
  662. #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
  663. typedef enum {
  664. COMP_SUCCESS = 1,
  665. /* Data Buffer Error */
  666. COMP_DB_ERR, /* 2 */
  667. /* Babble Detected Error */
  668. COMP_BABBLE, /* 3 */
  669. /* USB Transaction Error */
  670. COMP_TX_ERR, /* 4 */
  671. /* TRB Error - some TRB field is invalid */
  672. COMP_TRB_ERR, /* 5 */
  673. /* Stall Error - USB device is stalled */
  674. COMP_STALL, /* 6 */
  675. /* Resource Error - HC doesn't have memory for that device configuration */
  676. COMP_ENOMEM, /* 7 */
  677. /* Bandwidth Error - not enough room in schedule for this dev config */
  678. COMP_BW_ERR, /* 8 */
  679. /* No Slots Available Error - HC ran out of device slots */
  680. COMP_ENOSLOTS, /* 9 */
  681. /* Invalid Stream Type Error */
  682. COMP_STREAM_ERR, /* 10 */
  683. /* Slot Not Enabled Error - doorbell rung for disabled device slot */
  684. COMP_EBADSLT, /* 11 */
  685. /* Endpoint Not Enabled Error */
  686. COMP_EBADEP,/* 12 */
  687. /* Short Packet */
  688. COMP_SHORT_TX, /* 13 */
  689. /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
  690. COMP_UNDERRUN, /* 14 */
  691. /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
  692. COMP_OVERRUN, /* 15 */
  693. /* Virtual Function Event Ring Full Error */
  694. COMP_VF_FULL, /* 16 */
  695. /* Parameter Error - Context parameter is invalid */
  696. COMP_EINVAL, /* 17 */
  697. /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
  698. COMP_BW_OVER,/* 18 */
  699. /* Context State Error - illegal context state transition requested */
  700. COMP_CTX_STATE,/* 19 */
  701. /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
  702. COMP_PING_ERR,/* 20 */
  703. /* Event Ring is full */
  704. COMP_ER_FULL,/* 21 */
  705. /* Incompatible Device Error */
  706. COMP_DEV_ERR,/* 22 */
  707. /* Missed Service Error - HC couldn't service an isoc ep within interval */
  708. COMP_MISSED_INT,/* 23 */
  709. /* Successfully stopped command ring */
  710. COMP_CMD_STOP, /* 24 */
  711. /* Successfully aborted current command and stopped command ring */
  712. COMP_CMD_ABORT, /* 25 */
  713. /* Stopped - transfer was terminated by a stop endpoint command */
  714. COMP_STOP,/* 26 */
  715. /* Same as COMP_EP_STOPPED, but the transferred length in the event
  716. * is invalid */
  717. COMP_STOP_INVAL, /* 27*/
  718. /* Control Abort Error - Debug Capability - control pipe aborted */
  719. COMP_DBG_ABORT, /* 28 */
  720. /* Max Exit Latency Too Large Error */
  721. COMP_MEL_ERR,/* 29 */
  722. /* TRB type 30 reserved */
  723. /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
  724. COMP_BUFF_OVER = 31,
  725. /* Event Lost Error - xHC has an "internal event overrun condition" */
  726. COMP_ISSUES, /* 32 */
  727. /* Undefined Error - reported when other error codes don't apply */
  728. COMP_UNKNOWN, /* 33 */
  729. /* Invalid Stream ID Error */
  730. COMP_STRID_ERR, /* 34 */
  731. /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
  732. COMP_2ND_BW_ERR, /* 35 */
  733. /* Split Transaction Error */
  734. COMP_SPLIT_ERR /* 36 */
  735. } xhci_comp_code;
  736. struct xhci_link_trb {
  737. /* 64-bit segment pointer*/
  738. volatile __le64 segment_ptr;
  739. volatile __le32 intr_target;
  740. volatile __le32 control;
  741. };
  742. /* control bitfields */
  743. #define LINK_TOGGLE (0x1 << 1)
  744. /* Command completion event TRB */
  745. struct xhci_event_cmd {
  746. /* Pointer to command TRB, or the value passed by the event data trb */
  747. volatile __le64 cmd_trb;
  748. volatile __le32 status;
  749. volatile __le32 flags;
  750. };
  751. /* flags bitmasks */
  752. /* bits 16:23 are the virtual function ID */
  753. /* bits 24:31 are the slot ID */
  754. #define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24)
  755. #define TRB_TO_SLOT_ID_SHIFT (24)
  756. #define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT)
  757. #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
  758. #define SLOT_ID_FOR_TRB_MASK (0xff)
  759. #define SLOT_ID_FOR_TRB_SHIFT (24)
  760. /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
  761. #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
  762. #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
  763. #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
  764. #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
  765. #define LAST_EP_INDEX 30
  766. /* Set TR Dequeue Pointer command TRB fields */
  767. #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
  768. #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
  769. /* Port Status Change Event TRB fields */
  770. /* Port ID - bits 31:24 */
  771. #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
  772. #define PORT_ID_SHIFT (24)
  773. #define PORT_ID_MASK (0xff << PORT_ID_SHIFT)
  774. /* Normal TRB fields */
  775. /* transfer_len bitmasks - bits 0:16 */
  776. #define TRB_LEN(p) ((p) & 0x1ffff)
  777. #define TRB_LEN_MASK (0x1ffff)
  778. /* Interrupter Target - which MSI-X vector to target the completion event at */
  779. #define TRB_INTR_TARGET_SHIFT (22)
  780. #define TRB_INTR_TARGET_MASK (0x3ff)
  781. #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
  782. #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
  783. #define TRB_TBC(p) (((p) & 0x3) << 7)
  784. #define TRB_TLBPC(p) (((p) & 0xf) << 16)
  785. /* Cycle bit - indicates TRB ownership by HC or HCD */
  786. #define TRB_CYCLE (1<<0)
  787. /*
  788. * Force next event data TRB to be evaluated before task switch.
  789. * Used to pass OS data back after a TD completes.
  790. */
  791. #define TRB_ENT (1<<1)
  792. /* Interrupt on short packet */
  793. #define TRB_ISP (1<<2)
  794. /* Set PCIe no snoop attribute */
  795. #define TRB_NO_SNOOP (1<<3)
  796. /* Chain multiple TRBs into a TD */
  797. #define TRB_CHAIN (1<<4)
  798. /* Interrupt on completion */
  799. #define TRB_IOC (1<<5)
  800. /* The buffer pointer contains immediate data */
  801. #define TRB_IDT (1<<6)
  802. /* Block Event Interrupt */
  803. #define TRB_BEI (1<<9)
  804. /* Control transfer TRB specific fields */
  805. #define TRB_DIR_IN (1<<16)
  806. #define TRB_TX_TYPE(p) ((p) << 16)
  807. #define TRB_TX_TYPE_SHIFT (16)
  808. #define TRB_DATA_OUT 2
  809. #define TRB_DATA_IN 3
  810. /* Isochronous TRB specific fields */
  811. #define TRB_SIA (1 << 31)
  812. struct xhci_generic_trb {
  813. volatile __le32 field[4];
  814. };
  815. union xhci_trb {
  816. struct xhci_link_trb link;
  817. struct xhci_transfer_event trans_event;
  818. struct xhci_event_cmd event_cmd;
  819. struct xhci_generic_trb generic;
  820. };
  821. /* TRB bit mask */
  822. #define TRB_TYPE_BITMASK (0xfc00)
  823. #define TRB_TYPE(p) ((p) << 10)
  824. #define TRB_TYPE_SHIFT (10)
  825. #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
  826. /* TRB type IDs */
  827. typedef enum {
  828. /* bulk, interrupt, isoc scatter/gather, and control data stage */
  829. TRB_NORMAL = 1,
  830. /* setup stage for control transfers */
  831. TRB_SETUP, /* 2 */
  832. /* data stage for control transfers */
  833. TRB_DATA, /* 3 */
  834. /* status stage for control transfers */
  835. TRB_STATUS, /* 4 */
  836. /* isoc transfers */
  837. TRB_ISOC, /* 5 */
  838. /* TRB for linking ring segments */
  839. TRB_LINK, /* 6 */
  840. /* TRB for EVENT DATA */
  841. TRB_EVENT_DATA, /* 7 */
  842. /* Transfer Ring No-op (not for the command ring) */
  843. TRB_TR_NOOP, /* 8 */
  844. /* Command TRBs */
  845. /* Enable Slot Command */
  846. TRB_ENABLE_SLOT, /* 9 */
  847. /* Disable Slot Command */
  848. TRB_DISABLE_SLOT, /* 10 */
  849. /* Address Device Command */
  850. TRB_ADDR_DEV, /* 11 */
  851. /* Configure Endpoint Command */
  852. TRB_CONFIG_EP, /* 12 */
  853. /* Evaluate Context Command */
  854. TRB_EVAL_CONTEXT, /* 13 */
  855. /* Reset Endpoint Command */
  856. TRB_RESET_EP, /* 14 */
  857. /* Stop Transfer Ring Command */
  858. TRB_STOP_RING, /* 15 */
  859. /* Set Transfer Ring Dequeue Pointer Command */
  860. TRB_SET_DEQ, /* 16 */
  861. /* Reset Device Command */
  862. TRB_RESET_DEV, /* 17 */
  863. /* Force Event Command (opt) */
  864. TRB_FORCE_EVENT, /* 18 */
  865. /* Negotiate Bandwidth Command (opt) */
  866. TRB_NEG_BANDWIDTH, /* 19 */
  867. /* Set Latency Tolerance Value Command (opt) */
  868. TRB_SET_LT, /* 20 */
  869. /* Get port bandwidth Command */
  870. TRB_GET_BW, /* 21 */
  871. /* Force Header Command - generate a transaction or link management packet */
  872. TRB_FORCE_HEADER, /* 22 */
  873. /* No-op Command - not for transfer rings */
  874. TRB_CMD_NOOP, /* 23 */
  875. /* TRB IDs 24-31 reserved */
  876. /* Event TRBS */
  877. /* Transfer Event */
  878. TRB_TRANSFER = 32,
  879. /* Command Completion Event */
  880. TRB_COMPLETION, /* 33 */
  881. /* Port Status Change Event */
  882. TRB_PORT_STATUS, /* 34 */
  883. /* Bandwidth Request Event (opt) */
  884. TRB_BANDWIDTH_EVENT, /* 35 */
  885. /* Doorbell Event (opt) */
  886. TRB_DOORBELL, /* 36 */
  887. /* Host Controller Event */
  888. TRB_HC_EVENT, /* 37 */
  889. /* Device Notification Event - device sent function wake notification */
  890. TRB_DEV_NOTE, /* 38 */
  891. /* MFINDEX Wrap Event - microframe counter wrapped */
  892. TRB_MFINDEX_WRAP, /* 39 */
  893. /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
  894. /* Nec vendor-specific command completion event. */
  895. TRB_NEC_CMD_COMP = 48, /* 48 */
  896. /* Get NEC firmware revision. */
  897. TRB_NEC_GET_FW, /* 49 */
  898. } trb_type;
  899. #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
  900. /* Above, but for __le32 types -- can avoid work by swapping constants: */
  901. #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
  902. cpu_to_le32(TRB_TYPE(TRB_LINK)))
  903. #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
  904. cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
  905. /*
  906. * TRBS_PER_SEGMENT must be a multiple of 4,
  907. * since the command ring is 64-byte aligned.
  908. * It must also be greater than 16.
  909. */
  910. #define TRBS_PER_SEGMENT 64
  911. /* Allow two commands + a link TRB, along with any reserved command TRBs */
  912. #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
  913. #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
  914. /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
  915. * Change this if you change TRBS_PER_SEGMENT!
  916. */
  917. #define SEGMENT_SHIFT 10
  918. /* TRB buffer pointers can't cross 64KB boundaries */
  919. #define TRB_MAX_BUFF_SHIFT 16
  920. #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
  921. struct xhci_segment {
  922. union xhci_trb *trbs;
  923. /* private to HCD */
  924. struct xhci_segment *next;
  925. };
  926. struct xhci_ring {
  927. struct xhci_segment *first_seg;
  928. union xhci_trb *enqueue;
  929. struct xhci_segment *enq_seg;
  930. union xhci_trb *dequeue;
  931. struct xhci_segment *deq_seg;
  932. /*
  933. * Write the cycle state into the TRB cycle field to give ownership of
  934. * the TRB to the host controller (if we are the producer), or to check
  935. * if we own the TRB (if we are the consumer). See section 4.9.1.
  936. */
  937. volatile u32 cycle_state;
  938. unsigned int num_segs;
  939. };
  940. struct xhci_erst_entry {
  941. /* 64-bit event ring segment address */
  942. __le64 seg_addr;
  943. __le32 seg_size;
  944. /* Set to zero */
  945. __le32 rsvd;
  946. };
  947. struct xhci_erst {
  948. struct xhci_erst_entry *entries;
  949. unsigned int num_entries;
  950. /* Num entries the ERST can contain */
  951. unsigned int erst_size;
  952. };
  953. struct xhci_scratchpad {
  954. u64 *sp_array;
  955. };
  956. /*
  957. * Each segment table entry is 4*32bits long. 1K seems like an ok size:
  958. * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
  959. * meaning 64 ring segments.
  960. * Initial allocated size of the ERST, in number of entries */
  961. #define ERST_NUM_SEGS 1
  962. /* Initial number of event segment rings allocated */
  963. #define ERST_ENTRIES 1
  964. /* Initial allocated size of the ERST, in number of entries */
  965. #define ERST_SIZE 64
  966. /* Poll every 60 seconds */
  967. #define POLL_TIMEOUT 60
  968. /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
  969. #define XHCI_STOP_EP_CMD_TIMEOUT 5
  970. /* XXX: Make these module parameters */
  971. struct xhci_virt_ep {
  972. struct xhci_ring *ring;
  973. unsigned int ep_state;
  974. #define SET_DEQ_PENDING (1 << 0)
  975. #define EP_HALTED (1 << 1) /* For stall handling */
  976. #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
  977. /* Transitioning the endpoint to using streams, don't enqueue URBs */
  978. #define EP_GETTING_STREAMS (1 << 3)
  979. #define EP_HAS_STREAMS (1 << 4)
  980. /* Transitioning the endpoint to not using streams, don't enqueue URBs */
  981. #define EP_GETTING_NO_STREAMS (1 << 5)
  982. };
  983. #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
  984. struct xhci_virt_device {
  985. struct usb_device *udev;
  986. /*
  987. * Commands to the hardware are passed an "input context" that
  988. * tells the hardware what to change in its data structures.
  989. * The hardware will return changes in an "output context" that
  990. * software must allocate for the hardware. We need to keep
  991. * track of input and output contexts separately because
  992. * these commands might fail and we don't trust the hardware.
  993. */
  994. struct xhci_container_ctx *out_ctx;
  995. /* Used for addressing devices and configuration changes */
  996. struct xhci_container_ctx *in_ctx;
  997. /* Rings saved to ensure old alt settings can be re-instated */
  998. #define XHCI_MAX_RINGS_CACHED 31
  999. struct xhci_virt_ep eps[31];
  1000. };
  1001. /* TODO: copied from ehci.h - can be refactored? */
  1002. /* xHCI spec says all registers are little endian */
  1003. static inline unsigned int xhci_readl(uint32_t volatile *regs)
  1004. {
  1005. return readl(regs);
  1006. }
  1007. static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
  1008. {
  1009. writel(val, regs);
  1010. }
  1011. /*
  1012. * Registers should always be accessed with double word or quad word accesses.
  1013. * Some xHCI implementations may support 64-bit address pointers. Registers
  1014. * with 64-bit address pointers should be written to with dword accesses by
  1015. * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
  1016. * xHCI implementations that do not support 64-bit address pointers will ignore
  1017. * the high dword, and write order is irrelevant.
  1018. */
  1019. static inline u64 xhci_readq(__le64 volatile *regs)
  1020. {
  1021. #if BITS_PER_LONG == 64
  1022. return readq(regs);
  1023. #else
  1024. __u32 *ptr = (__u32 *)regs;
  1025. u64 val_lo = readl(ptr);
  1026. u64 val_hi = readl(ptr + 1);
  1027. return val_lo + (val_hi << 32);
  1028. #endif
  1029. }
  1030. static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
  1031. {
  1032. #if BITS_PER_LONG == 64
  1033. writeq(val, regs);
  1034. #else
  1035. __u32 *ptr = (__u32 *)regs;
  1036. u32 val_lo = lower_32_bits(val);
  1037. /* FIXME */
  1038. u32 val_hi = upper_32_bits(val);
  1039. writel(val_lo, ptr);
  1040. writel(val_hi, ptr + 1);
  1041. #endif
  1042. }
  1043. int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
  1044. struct xhci_hcor **ret_hcor);
  1045. void xhci_hcd_stop(int index);
  1046. /*************************************************************
  1047. EXTENDED CAPABILITY DEFINITIONS
  1048. *************************************************************/
  1049. /* Up to 16 ms to halt an HC */
  1050. #define XHCI_MAX_HALT_USEC (16*1000)
  1051. /* HC not running - set to 1 when run/stop bit is cleared. */
  1052. #define XHCI_STS_HALT (1 << 0)
  1053. /* HCCPARAMS offset from PCI base address */
  1054. #define XHCI_HCC_PARAMS_OFFSET 0x10
  1055. /* HCCPARAMS contains the first extended capability pointer */
  1056. #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
  1057. /* Command and Status registers offset from the Operational Registers address */
  1058. #define XHCI_CMD_OFFSET 0x00
  1059. #define XHCI_STS_OFFSET 0x04
  1060. #define XHCI_MAX_EXT_CAPS 50
  1061. /* Capability Register */
  1062. /* bits 7:0 - how long is the Capabilities register */
  1063. #define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff)
  1064. /* Extended capability register fields */
  1065. #define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff)
  1066. #define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff)
  1067. #define XHCI_EXT_CAPS_VAL(p) ((p) >> 16)
  1068. /* Extended capability IDs - ID 0 reserved */
  1069. #define XHCI_EXT_CAPS_LEGACY 1
  1070. #define XHCI_EXT_CAPS_PROTOCOL 2
  1071. #define XHCI_EXT_CAPS_PM 3
  1072. #define XHCI_EXT_CAPS_VIRT 4
  1073. #define XHCI_EXT_CAPS_ROUTE 5
  1074. /* IDs 6-9 reserved */
  1075. #define XHCI_EXT_CAPS_DEBUG 10
  1076. /* USB Legacy Support Capability - section 7.1.1 */
  1077. #define XHCI_HC_BIOS_OWNED (1 << 16)
  1078. #define XHCI_HC_OS_OWNED (1 << 24)
  1079. /* USB Legacy Support Capability - section 7.1.1 */
  1080. /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  1081. #define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
  1082. /* USB Legacy Support Control and Status Register - section 7.1.2 */
  1083. /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  1084. #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
  1085. /* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
  1086. #define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
  1087. /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
  1088. #define XHCI_L1C (1 << 16)
  1089. /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
  1090. #define XHCI_HLC (1 << 19)
  1091. /* command register values to disable interrupts and halt the HC */
  1092. /* start/stop HC execution - do not write unless HC is halted*/
  1093. #define XHCI_CMD_RUN (1 << 0)
  1094. /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
  1095. #define XHCI_CMD_EIE (1 << 2)
  1096. /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
  1097. #define XHCI_CMD_HSEIE (1 << 3)
  1098. /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
  1099. #define XHCI_CMD_EWE (1 << 10)
  1100. #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
  1101. /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
  1102. #define XHCI_STS_CNR (1 << 11)
  1103. struct xhci_ctrl {
  1104. #if CONFIG_IS_ENABLED(DM_USB)
  1105. struct udevice *dev;
  1106. #endif
  1107. struct xhci_hccr *hccr; /* R/O registers, not need for volatile */
  1108. struct xhci_hcor *hcor;
  1109. struct xhci_doorbell_array *dba;
  1110. struct xhci_run_regs *run_regs;
  1111. struct xhci_device_context_array *dcbaa \
  1112. __attribute__ ((aligned(ARCH_DMA_MINALIGN)));
  1113. struct xhci_ring *event_ring;
  1114. struct xhci_ring *cmd_ring;
  1115. struct xhci_ring *transfer_ring;
  1116. struct xhci_segment *seg;
  1117. struct xhci_intr_reg *ir_set;
  1118. struct xhci_erst erst;
  1119. struct xhci_erst_entry entry[ERST_NUM_SEGS];
  1120. struct xhci_scratchpad *scratchpad;
  1121. struct xhci_virt_device *devs[MAX_HC_SLOTS];
  1122. int rootdev;
  1123. };
  1124. unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);
  1125. struct xhci_input_control_ctx
  1126. *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
  1127. struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
  1128. struct xhci_container_ctx *ctx);
  1129. struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
  1130. struct xhci_container_ctx *ctx,
  1131. unsigned int ep_index);
  1132. void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
  1133. struct xhci_container_ctx *in_ctx,
  1134. struct xhci_container_ctx *out_ctx,
  1135. unsigned int ep_index);
  1136. void xhci_slot_copy(struct xhci_ctrl *ctrl,
  1137. struct xhci_container_ctx *in_ctx,
  1138. struct xhci_container_ctx *out_ctx);
  1139. void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
  1140. struct usb_device *udev, int hop_portnr);
  1141. void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr,
  1142. u32 slot_id, u32 ep_index, trb_type cmd);
  1143. void xhci_acknowledge_event(struct xhci_ctrl *ctrl);
  1144. union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected);
  1145. int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
  1146. int length, void *buffer);
  1147. int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe,
  1148. struct devrequest *req, int length, void *buffer);
  1149. int xhci_check_maxpacket(struct usb_device *udev);
  1150. void xhci_flush_cache(uintptr_t addr, u32 type_len);
  1151. void xhci_inval_cache(uintptr_t addr, u32 type_len);
  1152. void xhci_cleanup(struct xhci_ctrl *ctrl);
  1153. struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs);
  1154. int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id);
  1155. int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
  1156. struct xhci_hcor *hcor);
  1157. /**
  1158. * xhci_deregister() - Unregister an XHCI controller
  1159. *
  1160. * @dev: Controller device
  1161. * @return 0 if registered, -ve on error
  1162. */
  1163. int xhci_deregister(struct udevice *dev);
  1164. /**
  1165. * xhci_register() - Register a new XHCI controller
  1166. *
  1167. * @dev: Controller device
  1168. * @hccr: Host controller control registers
  1169. * @hcor: Not sure what this means
  1170. * @return 0 if registered, -ve on error
  1171. */
  1172. int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
  1173. struct xhci_hcor *hcor);
  1174. extern struct dm_usb_ops xhci_usb_ops;
  1175. struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev);
  1176. #endif /* HOST_XHCI_H_ */