dwcddr21mctl.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011 Andes Technology Corp
  4. * Macpaul Lin <macpaul@andestech.com>
  5. */
  6. /*
  7. * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
  8. */
  9. #ifndef __DWCDDR21MCTL_H
  10. #define __DWCDDR21MCTL_H
  11. #ifndef __ASSEMBLY__
  12. struct dwcddr21mctl {
  13. unsigned int ccr; /* Controller Configuration */
  14. unsigned int dcr; /* DRAM Configuration */
  15. unsigned int iocr; /* I/O Configuration */
  16. unsigned int csr; /* Controller Status */
  17. unsigned int drr; /* DRAM refresh */
  18. unsigned int tpr0; /* SDRAM Timing Parameters 0 */
  19. unsigned int tpr1; /* SDRAM Timing Parameters 1 */
  20. unsigned int tpr2; /* SDRAM Timing Parameters 2 */
  21. unsigned int gdllcr; /* Global DLL Control */
  22. unsigned int dllcr[10]; /* DLL Control */
  23. unsigned int rslr[4]; /* Rank System Lantency */
  24. unsigned int rdgr[4]; /* Rank DQS Gating */
  25. unsigned int dqtr[9]; /* DQ Timing */
  26. unsigned int dqstr; /* DQS Timing */
  27. unsigned int dqsbtr; /* DQS_b Timing */
  28. unsigned int odtcr; /* ODT Configuration */
  29. unsigned int dtr[2]; /* Data Training */
  30. unsigned int dtar; /* Data Training Address */
  31. unsigned int rsved[82]; /* Reserved */
  32. unsigned int mr; /* Mode Register */
  33. unsigned int emr; /* Extended Mode Register */
  34. unsigned int emr2; /* Extended Mode Register 2 */
  35. unsigned int emr3; /* Extended Mode Register 3 */
  36. unsigned int hpcr[32]; /* Host Port Configurarion */
  37. unsigned int pqcr[8]; /* Priority Queue Configuration */
  38. unsigned int mmgcr; /* Memory Manager General Config */
  39. };
  40. #endif /* __ASSEMBLY__ */
  41. /*
  42. * Control Configuration Register
  43. */
  44. #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
  45. #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
  46. #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
  47. #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
  48. #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
  49. #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
  50. #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
  51. #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
  52. #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
  53. #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
  54. #define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
  55. #define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
  56. #define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
  57. #define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
  58. /*
  59. * DRAM Configuration Register
  60. */
  61. #define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
  62. #define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
  63. #define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
  64. #define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
  65. #define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
  66. #define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
  67. #define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
  68. #define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
  69. #define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
  70. #define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
  71. #define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
  72. /*
  73. * I/O Configuration Register
  74. */
  75. #define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
  76. #define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
  77. #define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
  78. #define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
  79. #define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
  80. #define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
  81. #define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
  82. /*
  83. * Controller Status Register
  84. */
  85. #define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
  86. #define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
  87. #define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
  88. #define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
  89. #define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
  90. #define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
  91. /*
  92. * DRAM Refresh Register
  93. */
  94. #define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
  95. #define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
  96. #define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
  97. #define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
  98. /*
  99. * SDRAM Timing Parameters Register 0
  100. */
  101. #define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
  102. #define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
  103. #define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
  104. #define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
  105. #define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
  106. #define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
  107. #define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
  108. #define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
  109. #define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
  110. /*
  111. * SDRAM Timing Parameters Register 1
  112. */
  113. #define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
  114. #define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
  115. #define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
  116. #define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
  117. #define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
  118. #define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
  119. #define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
  120. #define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
  121. /*
  122. * SDRAM Timing Parameters Register 2
  123. */
  124. #define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
  125. #define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
  126. #define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
  127. /*
  128. * Global DLL Control Register
  129. */
  130. #define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
  131. #define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
  132. #define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
  133. #define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
  134. #define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
  135. #define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
  136. #define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
  137. #define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
  138. #define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
  139. /*
  140. * DLL Control Register 0-9
  141. */
  142. #define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
  143. #define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
  144. #define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
  145. #define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
  146. #define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
  147. #define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
  148. #define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
  149. #define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
  150. #define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
  151. /*
  152. * Rank System Lantency Register
  153. */
  154. #define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
  155. #define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
  156. #define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
  157. #define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
  158. #define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
  159. #define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
  160. #define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
  161. #define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
  162. #define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
  163. /*
  164. * Rank DQS Gating Register
  165. */
  166. #define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
  167. #define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
  168. #define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
  169. #define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
  170. #define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
  171. #define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
  172. #define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
  173. #define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
  174. #define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
  175. /*
  176. * DQ Timing Register
  177. */
  178. #define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
  179. #define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
  180. #define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
  181. #define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
  182. #define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
  183. #define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
  184. #define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
  185. #define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
  186. /*
  187. * DQS Timing Register
  188. */
  189. #define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
  190. #define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
  191. #define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
  192. #define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
  193. #define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
  194. #define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
  195. #define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
  196. #define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
  197. #define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
  198. /*
  199. * DQS_b (DQSBTR) Timing Register
  200. */
  201. #define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
  202. #define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
  203. #define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
  204. #define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
  205. #define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
  206. #define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
  207. #define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
  208. #define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
  209. #define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
  210. /*
  211. * ODT Configuration Register
  212. */
  213. #define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
  214. #define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
  215. #define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
  216. #define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
  217. #define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
  218. #define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
  219. #define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
  220. #define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
  221. /*
  222. * Data Training Register
  223. */
  224. #define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
  225. #define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
  226. #define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
  227. #define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
  228. #define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
  229. #define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
  230. #define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
  231. #define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
  232. /*
  233. * Data Training Address Register
  234. */
  235. #define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
  236. #define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
  237. #define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
  238. /*
  239. * Mode Register
  240. */
  241. #define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
  242. #define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
  243. #define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
  244. #define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
  245. #define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
  246. #define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
  247. #define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
  248. /*
  249. * Extended Mode register
  250. */
  251. #define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
  252. #define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
  253. #define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
  254. #define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
  255. #define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
  256. #define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
  257. #define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
  258. #define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
  259. #define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
  260. #define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
  261. #define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
  262. #define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0))
  263. #define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1))
  264. #define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0))
  265. #define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1))
  266. /*
  267. * Extended Mode register 2
  268. */
  269. #define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
  270. #define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
  271. #define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
  272. /*
  273. * Extended Mode register 3: [15:0] reserved for JEDEC.
  274. */
  275. /*
  276. * Host port Configuration register 0-31
  277. */
  278. #define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
  279. /*
  280. * Priority Queue Configuration register 0-7
  281. */
  282. #define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
  283. #define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
  284. #define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
  285. #define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
  286. #define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
  287. #define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
  288. #define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
  289. /*
  290. * Memory Manager General Configuration register
  291. */
  292. #define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
  293. #endif /* __DWCDDR21MCTL_H */