sdhci.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #ifndef __SDHCI_HW_H
  10. #define __SDHCI_HW_H
  11. #include <linux/types.h>
  12. #include <asm/io.h>
  13. #include <mmc.h>
  14. #include <asm/gpio.h>
  15. /*
  16. * Controller registers
  17. */
  18. #define SDHCI_DMA_ADDRESS 0x00
  19. #define SDHCI_BLOCK_SIZE 0x04
  20. #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  21. #define SDHCI_BLOCK_COUNT 0x06
  22. #define SDHCI_ARGUMENT 0x08
  23. #define SDHCI_TRANSFER_MODE 0x0C
  24. #define SDHCI_TRNS_DMA BIT(0)
  25. #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
  26. #define SDHCI_TRNS_ACMD12 BIT(2)
  27. #define SDHCI_TRNS_READ BIT(4)
  28. #define SDHCI_TRNS_MULTI BIT(5)
  29. #define SDHCI_COMMAND 0x0E
  30. #define SDHCI_CMD_RESP_MASK 0x03
  31. #define SDHCI_CMD_CRC 0x08
  32. #define SDHCI_CMD_INDEX 0x10
  33. #define SDHCI_CMD_DATA 0x20
  34. #define SDHCI_CMD_ABORTCMD 0xC0
  35. #define SDHCI_CMD_RESP_NONE 0x00
  36. #define SDHCI_CMD_RESP_LONG 0x01
  37. #define SDHCI_CMD_RESP_SHORT 0x02
  38. #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
  39. #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  40. #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  41. #define SDHCI_RESPONSE 0x10
  42. #define SDHCI_BUFFER 0x20
  43. #define SDHCI_PRESENT_STATE 0x24
  44. #define SDHCI_CMD_INHIBIT BIT(0)
  45. #define SDHCI_DATA_INHIBIT BIT(1)
  46. #define SDHCI_DOING_WRITE BIT(8)
  47. #define SDHCI_DOING_READ BIT(9)
  48. #define SDHCI_SPACE_AVAILABLE BIT(10)
  49. #define SDHCI_DATA_AVAILABLE BIT(11)
  50. #define SDHCI_CARD_PRESENT BIT(16)
  51. #define SDHCI_CARD_STATE_STABLE BIT(17)
  52. #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
  53. #define SDHCI_WRITE_PROTECT BIT(19)
  54. #define SDHCI_HOST_CONTROL 0x28
  55. #define SDHCI_CTRL_LED BIT(0)
  56. #define SDHCI_CTRL_4BITBUS BIT(1)
  57. #define SDHCI_CTRL_HISPD BIT(2)
  58. #define SDHCI_CTRL_DMA_MASK 0x18
  59. #define SDHCI_CTRL_SDMA 0x00
  60. #define SDHCI_CTRL_ADMA1 0x08
  61. #define SDHCI_CTRL_ADMA32 0x10
  62. #define SDHCI_CTRL_ADMA64 0x18
  63. #define SDHCI_CTRL_8BITBUS BIT(5)
  64. #define SDHCI_CTRL_CD_TEST_INS BIT(6)
  65. #define SDHCI_CTRL_CD_TEST BIT(7)
  66. #define SDHCI_POWER_CONTROL 0x29
  67. #define SDHCI_POWER_ON 0x01
  68. #define SDHCI_POWER_180 0x0A
  69. #define SDHCI_POWER_300 0x0C
  70. #define SDHCI_POWER_330 0x0E
  71. #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  72. #define SDHCI_WAKE_UP_CONTROL 0x2B
  73. #define SDHCI_WAKE_ON_INT BIT(0)
  74. #define SDHCI_WAKE_ON_INSERT BIT(1)
  75. #define SDHCI_WAKE_ON_REMOVE BIT(2)
  76. #define SDHCI_CLOCK_CONTROL 0x2C
  77. #define SDHCI_DIVIDER_SHIFT 8
  78. #define SDHCI_DIVIDER_HI_SHIFT 6
  79. #define SDHCI_DIV_MASK 0xFF
  80. #define SDHCI_DIV_MASK_LEN 8
  81. #define SDHCI_DIV_HI_MASK 0x300
  82. #define SDHCI_PROG_CLOCK_MODE BIT(5)
  83. #define SDHCI_CLOCK_CARD_EN BIT(2)
  84. #define SDHCI_CLOCK_INT_STABLE BIT(1)
  85. #define SDHCI_CLOCK_INT_EN BIT(0)
  86. #define SDHCI_TIMEOUT_CONTROL 0x2E
  87. #define SDHCI_SOFTWARE_RESET 0x2F
  88. #define SDHCI_RESET_ALL 0x01
  89. #define SDHCI_RESET_CMD 0x02
  90. #define SDHCI_RESET_DATA 0x04
  91. #define SDHCI_INT_STATUS 0x30
  92. #define SDHCI_INT_ENABLE 0x34
  93. #define SDHCI_SIGNAL_ENABLE 0x38
  94. #define SDHCI_INT_RESPONSE BIT(0)
  95. #define SDHCI_INT_DATA_END BIT(1)
  96. #define SDHCI_INT_DMA_END BIT(3)
  97. #define SDHCI_INT_SPACE_AVAIL BIT(4)
  98. #define SDHCI_INT_DATA_AVAIL BIT(5)
  99. #define SDHCI_INT_CARD_INSERT BIT(6)
  100. #define SDHCI_INT_CARD_REMOVE BIT(7)
  101. #define SDHCI_INT_CARD_INT BIT(8)
  102. #define SDHCI_INT_ERROR BIT(15)
  103. #define SDHCI_INT_TIMEOUT BIT(16)
  104. #define SDHCI_INT_CRC BIT(17)
  105. #define SDHCI_INT_END_BIT BIT(18)
  106. #define SDHCI_INT_INDEX BIT(19)
  107. #define SDHCI_INT_DATA_TIMEOUT BIT(20)
  108. #define SDHCI_INT_DATA_CRC BIT(21)
  109. #define SDHCI_INT_DATA_END_BIT BIT(22)
  110. #define SDHCI_INT_BUS_POWER BIT(23)
  111. #define SDHCI_INT_ACMD12ERR BIT(24)
  112. #define SDHCI_INT_ADMA_ERROR BIT(25)
  113. #define SDHCI_INT_NORMAL_MASK 0x00007FFF
  114. #define SDHCI_INT_ERROR_MASK 0xFFFF8000
  115. #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
  116. SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
  117. #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
  118. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
  119. SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
  120. SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
  121. #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
  122. #define SDHCI_ACMD12_ERR 0x3C
  123. #define SDHCI_HOST_CONTROL2 0x3E
  124. #define SDHCI_CTRL_UHS_MASK 0x0007
  125. #define SDHCI_CTRL_UHS_SDR12 0x0000
  126. #define SDHCI_CTRL_UHS_SDR25 0x0001
  127. #define SDHCI_CTRL_UHS_SDR50 0x0002
  128. #define SDHCI_CTRL_UHS_SDR104 0x0003
  129. #define SDHCI_CTRL_UHS_DDR50 0x0004
  130. #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
  131. #define SDHCI_CTRL_VDD_180 0x0008
  132. #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
  133. #define SDHCI_CTRL_DRV_TYPE_B 0x0000
  134. #define SDHCI_CTRL_DRV_TYPE_A 0x0010
  135. #define SDHCI_CTRL_DRV_TYPE_C 0x0020
  136. #define SDHCI_CTRL_DRV_TYPE_D 0x0030
  137. #define SDHCI_CTRL_EXEC_TUNING 0x0040
  138. #define SDHCI_CTRL_TUNED_CLK 0x0080
  139. #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
  140. #define SDHCI_CAPABILITIES 0x40
  141. #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
  142. #define SDHCI_TIMEOUT_CLK_SHIFT 0
  143. #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
  144. #define SDHCI_CLOCK_BASE_MASK 0x00003F00
  145. #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
  146. #define SDHCI_CLOCK_BASE_SHIFT 8
  147. #define SDHCI_MAX_BLOCK_MASK 0x00030000
  148. #define SDHCI_MAX_BLOCK_SHIFT 16
  149. #define SDHCI_CAN_DO_8BIT BIT(18)
  150. #define SDHCI_CAN_DO_ADMA2 BIT(19)
  151. #define SDHCI_CAN_DO_ADMA1 BIT(20)
  152. #define SDHCI_CAN_DO_HISPD BIT(21)
  153. #define SDHCI_CAN_DO_SDMA BIT(22)
  154. #define SDHCI_CAN_VDD_330 BIT(24)
  155. #define SDHCI_CAN_VDD_300 BIT(25)
  156. #define SDHCI_CAN_VDD_180 BIT(26)
  157. #define SDHCI_CAN_64BIT BIT(28)
  158. #define SDHCI_CAPABILITIES_1 0x44
  159. #define SDHCI_SUPPORT_SDR50 0x00000001
  160. #define SDHCI_SUPPORT_SDR104 0x00000002
  161. #define SDHCI_SUPPORT_DDR50 0x00000004
  162. #define SDHCI_USE_SDR50_TUNING 0x00002000
  163. #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
  164. #define SDHCI_CLOCK_MUL_SHIFT 16
  165. #define SDHCI_MAX_CURRENT 0x48
  166. /* 4C-4F reserved for more max current */
  167. #define SDHCI_SET_ACMD12_ERROR 0x50
  168. #define SDHCI_SET_INT_ERROR 0x52
  169. #define SDHCI_ADMA_ERROR 0x54
  170. /* 55-57 reserved */
  171. #define SDHCI_ADMA_ADDRESS 0x58
  172. #define SDHCI_ADMA_ADDRESS_HI 0x5c
  173. /* 60-FB reserved */
  174. #define SDHCI_SLOT_INT_STATUS 0xFC
  175. #define SDHCI_HOST_VERSION 0xFE
  176. #define SDHCI_VENDOR_VER_MASK 0xFF00
  177. #define SDHCI_VENDOR_VER_SHIFT 8
  178. #define SDHCI_SPEC_VER_MASK 0x00FF
  179. #define SDHCI_SPEC_VER_SHIFT 0
  180. #define SDHCI_SPEC_100 0
  181. #define SDHCI_SPEC_200 1
  182. #define SDHCI_SPEC_300 2
  183. #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
  184. /*
  185. * End of controller registers.
  186. */
  187. #define SDHCI_MAX_DIV_SPEC_200 256
  188. #define SDHCI_MAX_DIV_SPEC_300 2046
  189. /*
  190. * quirks
  191. */
  192. #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
  193. #define SDHCI_QUIRK_REG32_RW (1 << 1)
  194. #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
  195. #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
  196. #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
  197. /*
  198. * SDHCI_QUIRK_BROKEN_HISPD_MODE
  199. * the hardware cannot operate correctly in high-speed mode,
  200. * this quirk forces the sdhci host-controller to non high-speed mode
  201. */
  202. #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
  203. #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
  204. #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
  205. /* to make gcc happy */
  206. struct sdhci_host;
  207. /*
  208. * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
  209. */
  210. #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
  211. #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
  212. struct sdhci_ops {
  213. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  214. u32 (*read_l)(struct sdhci_host *host, int reg);
  215. u16 (*read_w)(struct sdhci_host *host, int reg);
  216. u8 (*read_b)(struct sdhci_host *host, int reg);
  217. void (*write_l)(struct sdhci_host *host, u32 val, int reg);
  218. void (*write_w)(struct sdhci_host *host, u16 val, int reg);
  219. void (*write_b)(struct sdhci_host *host, u8 val, int reg);
  220. #endif
  221. int (*get_cd)(struct sdhci_host *host);
  222. void (*set_control_reg)(struct sdhci_host *host);
  223. int (*set_ios_post)(struct sdhci_host *host);
  224. void (*set_clock)(struct sdhci_host *host, u32 div);
  225. int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
  226. void (*set_delay)(struct sdhci_host *host);
  227. int (*deferred_probe)(struct sdhci_host *host);
  228. };
  229. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  230. #define ADMA_MAX_LEN 65532
  231. #ifdef CONFIG_DMA_ADDR_T_64BIT
  232. #define ADMA_DESC_LEN 16
  233. #else
  234. #define ADMA_DESC_LEN 8
  235. #endif
  236. #define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
  237. MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
  238. #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
  239. /* Decriptor table defines */
  240. #define ADMA_DESC_ATTR_VALID BIT(0)
  241. #define ADMA_DESC_ATTR_END BIT(1)
  242. #define ADMA_DESC_ATTR_INT BIT(2)
  243. #define ADMA_DESC_ATTR_ACT1 BIT(4)
  244. #define ADMA_DESC_ATTR_ACT2 BIT(5)
  245. #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
  246. #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
  247. struct sdhci_adma_desc {
  248. u8 attr;
  249. u8 reserved;
  250. u16 len;
  251. u32 addr_lo;
  252. #ifdef CONFIG_DMA_ADDR_T_64BIT
  253. u32 addr_hi;
  254. #endif
  255. } __packed;
  256. #endif
  257. struct sdhci_host {
  258. const char *name;
  259. void *ioaddr;
  260. unsigned int quirks;
  261. unsigned int host_caps;
  262. unsigned int version;
  263. unsigned int max_clk; /* Maximum Base Clock frequency */
  264. unsigned int clk_mul; /* Clock Multiplier value */
  265. unsigned int clock;
  266. struct mmc *mmc;
  267. const struct sdhci_ops *ops;
  268. int index;
  269. int bus_width;
  270. struct gpio_desc pwr_gpio; /* Power GPIO */
  271. struct gpio_desc cd_gpio; /* Card Detect GPIO */
  272. uint voltages;
  273. struct mmc_config cfg;
  274. void *align_buffer;
  275. bool force_align_buffer;
  276. dma_addr_t start_addr;
  277. int flags;
  278. #define USE_SDMA (0x1 << 0)
  279. #define USE_ADMA (0x1 << 1)
  280. #define USE_ADMA64 (0x1 << 2)
  281. #define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
  282. dma_addr_t adma_addr;
  283. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  284. struct sdhci_adma_desc *adma_desc_table;
  285. uint desc_slot;
  286. #endif
  287. };
  288. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  289. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  290. {
  291. if (unlikely(host->ops->write_l))
  292. host->ops->write_l(host, val, reg);
  293. else
  294. writel(val, host->ioaddr + reg);
  295. }
  296. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  297. {
  298. if (unlikely(host->ops->write_w))
  299. host->ops->write_w(host, val, reg);
  300. else
  301. writew(val, host->ioaddr + reg);
  302. }
  303. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  304. {
  305. if (unlikely(host->ops->write_b))
  306. host->ops->write_b(host, val, reg);
  307. else
  308. writeb(val, host->ioaddr + reg);
  309. }
  310. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  311. {
  312. if (unlikely(host->ops->read_l))
  313. return host->ops->read_l(host, reg);
  314. else
  315. return readl(host->ioaddr + reg);
  316. }
  317. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  318. {
  319. if (unlikely(host->ops->read_w))
  320. return host->ops->read_w(host, reg);
  321. else
  322. return readw(host->ioaddr + reg);
  323. }
  324. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  325. {
  326. if (unlikely(host->ops->read_b))
  327. return host->ops->read_b(host, reg);
  328. else
  329. return readb(host->ioaddr + reg);
  330. }
  331. #else
  332. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  333. {
  334. writel(val, host->ioaddr + reg);
  335. }
  336. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  337. {
  338. writew(val, host->ioaddr + reg);
  339. }
  340. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  341. {
  342. writeb(val, host->ioaddr + reg);
  343. }
  344. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  345. {
  346. return readl(host->ioaddr + reg);
  347. }
  348. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  349. {
  350. return readw(host->ioaddr + reg);
  351. }
  352. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  353. {
  354. return readb(host->ioaddr + reg);
  355. }
  356. #endif
  357. #ifdef CONFIG_BLK
  358. /**
  359. * sdhci_setup_cfg() - Set up the configuration for DWMMC
  360. *
  361. * This is used to set up an SDHCI device when you are using CONFIG_BLK.
  362. *
  363. * This should be called from your MMC driver's probe() method once you have
  364. * the information required.
  365. *
  366. * Generally your driver will have a platform data structure which holds both
  367. * the configuration (struct mmc_config) and the MMC device info (struct mmc).
  368. * For example:
  369. *
  370. * struct msm_sdhc_plat {
  371. * struct mmc_config cfg;
  372. * struct mmc mmc;
  373. * };
  374. *
  375. * ...
  376. *
  377. * Inside U_BOOT_DRIVER():
  378. * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
  379. *
  380. * To access platform data:
  381. * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
  382. *
  383. * See msm_sdhci.c for an example.
  384. *
  385. * @cfg: Configuration structure to fill in (generally &plat->mmc)
  386. * @host: SDHCI host structure
  387. * @f_max: Maximum supported clock frequency in HZ (0 for default)
  388. * @f_min: Minimum supported clock frequency in HZ (0 for default)
  389. */
  390. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  391. u32 f_max, u32 f_min);
  392. /**
  393. * sdhci_bind() - Set up a new MMC block device
  394. *
  395. * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
  396. * It should be called from your driver's bind() method.
  397. *
  398. * See msm_sdhci.c for an example.
  399. *
  400. * @dev: Device to set up
  401. * @mmc: Pointer to mmc structure (normally &plat->mmc)
  402. * @cfg: Empty configuration structure (generally &plat->cfg). This is
  403. * normally all zeroes at this point. The only purpose of passing
  404. * this in is to set mmc->cfg to it.
  405. * @return 0 if OK, -ve if the block device could not be created
  406. */
  407. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  408. #else
  409. /**
  410. * add_sdhci() - Add a new SDHCI interface
  411. *
  412. * This is used when you are not using CONFIG_BLK. Convert your driver over!
  413. *
  414. * @host: SDHCI host structure
  415. * @f_max: Maximum supported clock frequency in HZ (0 for default)
  416. * @f_min: Minimum supported clock frequency in HZ (0 for default)
  417. * @return 0 if OK, -ve on error
  418. */
  419. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
  420. #endif /* !CONFIG_BLK */
  421. void sdhci_set_uhs_timing(struct sdhci_host *host);
  422. #ifdef CONFIG_DM_MMC
  423. /* Export the operations to drivers */
  424. int sdhci_probe(struct udevice *dev);
  425. int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
  426. extern const struct dm_mmc_ops sdhci_ops;
  427. #else
  428. #endif
  429. #endif /* __SDHCI_HW_H */