sp805_wdt.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Watchdog driver for SP805 on some Layerscape SoC
  4. *
  5. * Copyright 2019 NXP
  6. */
  7. #include <asm/io.h>
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm/device.h>
  11. #include <dm/fdtaddr.h>
  12. #include <dm/read.h>
  13. #include <linux/bitops.h>
  14. #include <watchdog.h>
  15. #include <wdt.h>
  16. #include <linux/err.h>
  17. #define WDTLOAD 0x000
  18. #define WDTCONTROL 0x008
  19. #define WDTINTCLR 0x00C
  20. #define WDTLOCK 0xC00
  21. #define TIME_OUT_MIN_MSECS 1
  22. #define TIME_OUT_MAX_MSECS 120000
  23. #define SYS_FSL_WDT_CLK_DIV 16
  24. #define INT_ENABLE BIT(0)
  25. #define RESET_ENABLE BIT(1)
  26. #define DISABLE 0
  27. #define UNLOCK 0x1ACCE551
  28. #define LOCK 0x00000001
  29. #define INT_MASK BIT(0)
  30. DECLARE_GLOBAL_DATA_PTR;
  31. struct sp805_wdt_priv {
  32. void __iomem *reg;
  33. unsigned long clk_rate;
  34. };
  35. static int sp805_wdt_reset(struct udevice *dev)
  36. {
  37. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  38. writel(UNLOCK, priv->reg + WDTLOCK);
  39. writel(INT_MASK, priv->reg + WDTINTCLR);
  40. writel(LOCK, priv->reg + WDTLOCK);
  41. readl(priv->reg + WDTLOCK);
  42. return 0;
  43. }
  44. static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  45. {
  46. u32 load_value;
  47. u32 load_time;
  48. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  49. load_time = (u32)timeout;
  50. if (timeout < TIME_OUT_MIN_MSECS)
  51. load_time = TIME_OUT_MIN_MSECS;
  52. else if (timeout > TIME_OUT_MAX_MSECS)
  53. load_time = TIME_OUT_MAX_MSECS;
  54. /* sp805 runs counter with given value twice, so when the max timeout is
  55. * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
  56. * not overflow.
  57. */
  58. if (gd->bus_clk) {
  59. load_value = (gd->bus_clk) /
  60. (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
  61. } else {
  62. /* platform provide clk */
  63. load_value = (timeout / 2) * (priv->clk_rate / 1000);
  64. }
  65. writel(UNLOCK, priv->reg + WDTLOCK);
  66. writel(load_value, priv->reg + WDTLOAD);
  67. writel(INT_MASK, priv->reg + WDTINTCLR);
  68. writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
  69. writel(LOCK, priv->reg + WDTLOCK);
  70. readl(priv->reg + WDTLOCK);
  71. return 0;
  72. }
  73. static int sp805_wdt_stop(struct udevice *dev)
  74. {
  75. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  76. writel(UNLOCK, priv->reg + WDTLOCK);
  77. writel(DISABLE, priv->reg + WDTCONTROL);
  78. writel(LOCK, priv->reg + WDTLOCK);
  79. readl(priv->reg + WDTLOCK);
  80. return 0;
  81. }
  82. static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
  83. {
  84. sp805_wdt_start(dev, 0, flags);
  85. return 0;
  86. }
  87. static int sp805_wdt_probe(struct udevice *dev)
  88. {
  89. debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev->seq);
  90. return 0;
  91. }
  92. static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
  93. {
  94. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  95. struct clk clk;
  96. priv->reg = (void __iomem *)dev_read_addr(dev);
  97. if (IS_ERR(priv->reg))
  98. return PTR_ERR(priv->reg);
  99. if (!clk_get_by_index(dev, 0, &clk))
  100. priv->clk_rate = clk_get_rate(&clk);
  101. return 0;
  102. }
  103. static const struct wdt_ops sp805_wdt_ops = {
  104. .start = sp805_wdt_start,
  105. .reset = sp805_wdt_reset,
  106. .stop = sp805_wdt_stop,
  107. .expire_now = sp805_wdt_expire_now,
  108. };
  109. static const struct udevice_id sp805_wdt_ids[] = {
  110. { .compatible = "arm,sp805-wdt" },
  111. {}
  112. };
  113. U_BOOT_DRIVER(sp805_wdt) = {
  114. .name = "sp805_wdt",
  115. .id = UCLASS_WDT,
  116. .of_match = sp805_wdt_ids,
  117. .probe = sp805_wdt_probe,
  118. .priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
  119. .ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
  120. .ops = &sp805_wdt_ops,
  121. };