designware_wdt.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Altera Corporation <www.altera.com>
  4. */
  5. #include <clk.h>
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <reset.h>
  9. #include <wdt.h>
  10. #include <asm/io.h>
  11. #include <asm/utils.h>
  12. #define DW_WDT_CR 0x00
  13. #define DW_WDT_TORR 0x04
  14. #define DW_WDT_CRR 0x0C
  15. #define DW_WDT_CR_EN_OFFSET 0x00
  16. #define DW_WDT_CR_RMOD_OFFSET 0x01
  17. #define DW_WDT_CRR_RESTART_VAL 0x76
  18. struct designware_wdt_priv {
  19. void __iomem *base;
  20. unsigned int clk_khz;
  21. };
  22. /*
  23. * Set the watchdog time interval.
  24. * Counter is 32 bit.
  25. */
  26. static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
  27. unsigned int timeout)
  28. {
  29. signed int i;
  30. /* calculate the timeout range value */
  31. i = log_2_n_round_up(timeout * clk_khz) - 16;
  32. i = clamp(i, 0, 15);
  33. writel(i | (i << 4), base + DW_WDT_TORR);
  34. return 0;
  35. }
  36. static void designware_wdt_enable(void __iomem *base)
  37. {
  38. writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
  39. }
  40. static unsigned int designware_wdt_is_enabled(void __iomem *base)
  41. {
  42. return readl(base + DW_WDT_CR) & BIT(0);
  43. }
  44. static void designware_wdt_reset_common(void __iomem *base)
  45. {
  46. if (designware_wdt_is_enabled(base))
  47. /* restart the watchdog counter */
  48. writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
  49. }
  50. #if !CONFIG_IS_ENABLED(WDT)
  51. void hw_watchdog_reset(void)
  52. {
  53. designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
  54. }
  55. void hw_watchdog_init(void)
  56. {
  57. /* reset to disable the watchdog */
  58. hw_watchdog_reset();
  59. /* set timer in miliseconds */
  60. designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
  61. CONFIG_DW_WDT_CLOCK_KHZ,
  62. CONFIG_WATCHDOG_TIMEOUT_MSECS);
  63. /* enable the watchdog */
  64. designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
  65. /* reset the watchdog */
  66. hw_watchdog_reset();
  67. }
  68. #else
  69. static int designware_wdt_reset(struct udevice *dev)
  70. {
  71. struct designware_wdt_priv *priv = dev_get_priv(dev);
  72. designware_wdt_reset_common(priv->base);
  73. return 0;
  74. }
  75. static int designware_wdt_stop(struct udevice *dev)
  76. {
  77. struct designware_wdt_priv *priv = dev_get_priv(dev);
  78. designware_wdt_reset(dev);
  79. writel(0, priv->base + DW_WDT_CR);
  80. return 0;
  81. }
  82. static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  83. {
  84. struct designware_wdt_priv *priv = dev_get_priv(dev);
  85. designware_wdt_stop(dev);
  86. /* set timer in miliseconds */
  87. designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
  88. designware_wdt_enable(priv->base);
  89. /* reset the watchdog */
  90. return designware_wdt_reset(dev);
  91. }
  92. static int designware_wdt_probe(struct udevice *dev)
  93. {
  94. struct designware_wdt_priv *priv = dev_get_priv(dev);
  95. __maybe_unused int ret;
  96. priv->base = dev_remap_addr(dev);
  97. if (!priv->base)
  98. return -EINVAL;
  99. #if CONFIG_IS_ENABLED(CLK)
  100. struct clk clk;
  101. ret = clk_get_by_index(dev, 0, &clk);
  102. if (ret)
  103. return ret;
  104. priv->clk_khz = clk_get_rate(&clk);
  105. if (!priv->clk_khz)
  106. return -EINVAL;
  107. #else
  108. priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
  109. #endif
  110. #if CONFIG_IS_ENABLED(DM_RESET)
  111. struct reset_ctl_bulk resets;
  112. ret = reset_get_bulk(dev, &resets);
  113. if (ret)
  114. return ret;
  115. ret = reset_deassert_bulk(&resets);
  116. if (ret)
  117. return ret;
  118. #endif
  119. /* reset to disable the watchdog */
  120. return designware_wdt_stop(dev);
  121. }
  122. static const struct wdt_ops designware_wdt_ops = {
  123. .start = designware_wdt_start,
  124. .reset = designware_wdt_reset,
  125. .stop = designware_wdt_stop,
  126. };
  127. static const struct udevice_id designware_wdt_ids[] = {
  128. { .compatible = "snps,dw-wdt"},
  129. {}
  130. };
  131. U_BOOT_DRIVER(designware_wdt) = {
  132. .name = "designware_wdt",
  133. .id = UCLASS_WDT,
  134. .of_match = designware_wdt_ids,
  135. .priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
  136. .probe = designware_wdt_probe,
  137. .ops = &designware_wdt_ops,
  138. .flags = DM_FLAG_PRE_RELOC,
  139. };
  140. #endif