uniphier_spi.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * uniphier_spi.c - Socionext UniPhier SPI driver
  4. * Copyright 2019 Socionext, Inc.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <time.h>
  10. #include <dm/device_compat.h>
  11. #include <linux/bitfield.h>
  12. #include <linux/io.h>
  13. #include <spi.h>
  14. #include <wait_bit.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define SSI_CTL 0x00
  17. #define SSI_CTL_EN BIT(0)
  18. #define SSI_CKS 0x04
  19. #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
  20. #define SSI_CKS_CKPHS BIT(14)
  21. #define SSI_CKS_CKINIT BIT(13)
  22. #define SSI_CKS_CKDLY BIT(12)
  23. #define SSI_TXWDS 0x08
  24. #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
  25. #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
  26. #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
  27. #define SSI_RXWDS 0x0c
  28. #define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
  29. #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
  30. #define SSI_FPS 0x10
  31. #define SSI_FPS_FSPOL BIT(15)
  32. #define SSI_FPS_FSTRT BIT(14)
  33. #define SSI_SR 0x14
  34. #define SSI_SR_BUSY BIT(7)
  35. #define SSI_SR_TNF BIT(5)
  36. #define SSI_SR_RNE BIT(0)
  37. #define SSI_IE 0x18
  38. #define SSI_IC 0x1c
  39. #define SSI_IC_TCIC BIT(4)
  40. #define SSI_IC_RCIC BIT(3)
  41. #define SSI_IC_RORIC BIT(0)
  42. #define SSI_FC 0x20
  43. #define SSI_FC_TXFFL BIT(12)
  44. #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
  45. #define SSI_FC_RXFFL BIT(4)
  46. #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
  47. #define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
  48. #define SSI_FIFO_DEPTH 8U
  49. #define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
  50. #define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
  51. #define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
  52. struct uniphier_spi_platdata {
  53. void __iomem *base;
  54. u32 frequency; /* input frequency */
  55. u32 speed_hz;
  56. uint deactivate_delay_us; /* Delay to wait after deactivate */
  57. uint activate_delay_us; /* Delay to wait after activate */
  58. };
  59. struct uniphier_spi_priv {
  60. void __iomem *base;
  61. u8 mode;
  62. u8 fifo_depth;
  63. u8 bits_per_word;
  64. ulong last_transaction_us; /* Time of last transaction end */
  65. };
  66. static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
  67. {
  68. u32 val;
  69. val = readl(priv->base + SSI_CTL);
  70. if (enable)
  71. val |= SSI_CTL_EN;
  72. else
  73. val &= ~SSI_CTL_EN;
  74. writel(val, priv->base + SSI_CTL);
  75. }
  76. static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
  77. {
  78. pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
  79. pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
  80. pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
  81. pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
  82. pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
  83. pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
  84. pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
  85. pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
  86. pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
  87. pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
  88. }
  89. static void spi_cs_activate(struct udevice *dev)
  90. {
  91. struct udevice *bus = dev->parent;
  92. struct uniphier_spi_platdata *plat = bus->platdata;
  93. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  94. ulong delay_us; /* The delay completed so far */
  95. u32 val;
  96. /* If it's too soon to do another transaction, wait */
  97. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  98. delay_us = timer_get_us() - priv->last_transaction_us;
  99. if (delay_us < plat->deactivate_delay_us)
  100. udelay(plat->deactivate_delay_us - delay_us);
  101. }
  102. val = readl(priv->base + SSI_FPS);
  103. if (priv->mode & SPI_CS_HIGH)
  104. val |= SSI_FPS_FSPOL;
  105. else
  106. val &= ~SSI_FPS_FSPOL;
  107. writel(val, priv->base + SSI_FPS);
  108. if (plat->activate_delay_us)
  109. udelay(plat->activate_delay_us);
  110. }
  111. static void spi_cs_deactivate(struct udevice *dev)
  112. {
  113. struct udevice *bus = dev->parent;
  114. struct uniphier_spi_platdata *plat = bus->platdata;
  115. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  116. u32 val;
  117. val = readl(priv->base + SSI_FPS);
  118. if (priv->mode & SPI_CS_HIGH)
  119. val &= ~SSI_FPS_FSPOL;
  120. else
  121. val |= SSI_FPS_FSPOL;
  122. writel(val, priv->base + SSI_FPS);
  123. /* Remember time of this transaction so we can honour the bus delay */
  124. if (plat->deactivate_delay_us)
  125. priv->last_transaction_us = timer_get_us();
  126. }
  127. static int uniphier_spi_claim_bus(struct udevice *dev)
  128. {
  129. struct udevice *bus = dev->parent;
  130. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  131. u32 val, size;
  132. uniphier_spi_enable(priv, false);
  133. /* disable interrupts */
  134. writel(0, priv->base + SSI_IE);
  135. /* bits_per_word */
  136. size = priv->bits_per_word;
  137. val = readl(priv->base + SSI_TXWDS);
  138. val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
  139. val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
  140. val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
  141. writel(val, priv->base + SSI_TXWDS);
  142. val = readl(priv->base + SSI_RXWDS);
  143. val &= ~SSI_RXWDS_DTLEN_MASK;
  144. val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
  145. writel(val, priv->base + SSI_RXWDS);
  146. /* reset FIFOs */
  147. val = SSI_FC_TXFFL | SSI_FC_RXFFL;
  148. writel(val, priv->base + SSI_FC);
  149. /* FIFO threthold */
  150. val = readl(priv->base + SSI_FC);
  151. val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
  152. val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
  153. val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
  154. writel(val, priv->base + SSI_FC);
  155. /* clear interrupts */
  156. writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
  157. priv->base + SSI_IC);
  158. uniphier_spi_enable(priv, true);
  159. return 0;
  160. }
  161. static int uniphier_spi_release_bus(struct udevice *dev)
  162. {
  163. struct udevice *bus = dev->parent;
  164. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  165. uniphier_spi_enable(priv, false);
  166. return 0;
  167. }
  168. static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
  169. const void *dout, void *din, unsigned long flags)
  170. {
  171. struct udevice *bus = dev->parent;
  172. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  173. const u8 *tx_buf = dout;
  174. u8 *rx_buf = din, buf;
  175. u32 len = bitlen / 8;
  176. u32 tx_len, rx_len;
  177. u32 ts, status;
  178. int ret = 0;
  179. if (bitlen % 8) {
  180. dev_err(dev, "Non byte aligned SPI transfer\n");
  181. return -EINVAL;
  182. }
  183. if (flags & SPI_XFER_BEGIN)
  184. spi_cs_activate(dev);
  185. uniphier_spi_enable(priv, true);
  186. ts = get_timer(0);
  187. tx_len = len;
  188. rx_len = len;
  189. uniphier_spi_regdump(priv);
  190. while (tx_len || rx_len) {
  191. ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
  192. SSI_REG_TIMEOUT * 1000, false);
  193. if (ret) {
  194. if (ret == -ETIMEDOUT)
  195. dev_err(dev, "access timeout\n");
  196. break;
  197. }
  198. status = readl(priv->base + SSI_SR);
  199. /* write the data into TX */
  200. if (tx_len && (status & SSI_SR_TNF)) {
  201. buf = tx_buf ? *tx_buf++ : 0;
  202. writel(buf, priv->base + SSI_XDR);
  203. tx_len--;
  204. }
  205. /* read the data from RX */
  206. if (rx_len && (status & SSI_SR_RNE)) {
  207. buf = readl(priv->base + SSI_XDR);
  208. if (rx_buf)
  209. *rx_buf++ = buf;
  210. rx_len--;
  211. }
  212. if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
  213. dev_err(dev, "transfer timeout\n");
  214. ret = -ETIMEDOUT;
  215. break;
  216. }
  217. }
  218. if (flags & SPI_XFER_END)
  219. spi_cs_deactivate(dev);
  220. uniphier_spi_enable(priv, false);
  221. return ret;
  222. }
  223. static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
  224. {
  225. struct uniphier_spi_platdata *plat = bus->platdata;
  226. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  227. u32 val, ckdiv;
  228. if (speed > plat->frequency)
  229. speed = plat->frequency;
  230. /* baudrate */
  231. ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
  232. ckdiv = round_up(ckdiv, 2);
  233. val = readl(priv->base + SSI_CKS);
  234. val &= ~SSI_CKS_CKRAT_MASK;
  235. val |= ckdiv & SSI_CKS_CKRAT_MASK;
  236. writel(val, priv->base + SSI_CKS);
  237. return 0;
  238. }
  239. static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
  240. {
  241. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  242. u32 val1, val2;
  243. /*
  244. * clock setting
  245. * CKPHS capture timing. 0:rising edge, 1:falling edge
  246. * CKINIT clock initial level. 0:low, 1:high
  247. * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
  248. * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
  249. *
  250. * frame setting
  251. * FSPOL frame signal porarity. 0: low, 1: high
  252. * FSTRT start frame timing
  253. * 0: rising edge of clock, 1: falling edge of clock
  254. */
  255. val1 = readl(priv->base + SSI_CKS);
  256. val2 = readl(priv->base + SSI_FPS);
  257. switch (mode & (SPI_CPOL | SPI_CPHA)) {
  258. case SPI_MODE_0:
  259. /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
  260. val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
  261. val1 &= ~SSI_CKS_CKINIT;
  262. val2 &= ~SSI_FPS_FSTRT;
  263. break;
  264. case SPI_MODE_1:
  265. /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
  266. val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
  267. val2 |= SSI_FPS_FSTRT;
  268. break;
  269. case SPI_MODE_2:
  270. /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
  271. val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
  272. val1 &= ~SSI_CKS_CKPHS;
  273. val2 |= SSI_FPS_FSTRT;
  274. break;
  275. case SPI_MODE_3:
  276. /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
  277. val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
  278. val1 &= ~SSI_CKS_CKDLY;
  279. val2 &= ~SSI_FPS_FSTRT;
  280. break;
  281. }
  282. writel(val1, priv->base + SSI_CKS);
  283. writel(val2, priv->base + SSI_FPS);
  284. /* format */
  285. val1 = readl(priv->base + SSI_TXWDS);
  286. val2 = readl(priv->base + SSI_RXWDS);
  287. if (mode & SPI_LSB_FIRST) {
  288. val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
  289. val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
  290. }
  291. writel(val1, priv->base + SSI_TXWDS);
  292. writel(val2, priv->base + SSI_RXWDS);
  293. priv->mode = mode;
  294. return 0;
  295. }
  296. static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
  297. {
  298. struct uniphier_spi_platdata *plat = bus->platdata;
  299. const void *blob = gd->fdt_blob;
  300. int node = dev_of_offset(bus);
  301. plat->base = devfdt_get_addr_ptr(bus);
  302. plat->frequency =
  303. fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
  304. plat->deactivate_delay_us =
  305. fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
  306. plat->activate_delay_us =
  307. fdtdec_get_int(blob, node, "spi-activate-delay", 0);
  308. plat->speed_hz = plat->frequency / 2;
  309. return 0;
  310. }
  311. static int uniphier_spi_probe(struct udevice *bus)
  312. {
  313. struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
  314. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  315. priv->base = plat->base;
  316. priv->fifo_depth = SSI_FIFO_DEPTH;
  317. priv->bits_per_word = 8;
  318. return 0;
  319. }
  320. static const struct dm_spi_ops uniphier_spi_ops = {
  321. .claim_bus = uniphier_spi_claim_bus,
  322. .release_bus = uniphier_spi_release_bus,
  323. .xfer = uniphier_spi_xfer,
  324. .set_speed = uniphier_spi_set_speed,
  325. .set_mode = uniphier_spi_set_mode,
  326. };
  327. static const struct udevice_id uniphier_spi_ids[] = {
  328. { .compatible = "socionext,uniphier-scssi" },
  329. { /* Sentinel */ }
  330. };
  331. U_BOOT_DRIVER(uniphier_spi) = {
  332. .name = "uniphier_spi",
  333. .id = UCLASS_SPI,
  334. .of_match = uniphier_spi_ids,
  335. .ops = &uniphier_spi_ops,
  336. .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
  337. .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
  338. .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
  339. .probe = uniphier_spi_probe,
  340. };