ti_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI QSPI driver
  4. *
  5. * Copyright (C) 2013, Texas Instruments, Incorporated
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/omap.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <spi-mem.h>
  14. #include <dm.h>
  15. #include <asm/gpio.h>
  16. #include <asm/omap_gpio.h>
  17. #include <asm/omap_common.h>
  18. #include <asm/ti-common/ti-edma3.h>
  19. #include <linux/err.h>
  20. #include <linux/kernel.h>
  21. #include <regmap.h>
  22. #include <syscon.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* ti qpsi register bit masks */
  25. #define QSPI_TIMEOUT 2000000
  26. #define QSPI_FCLK 192000000
  27. #define QSPI_DRA7XX_FCLK 76800000
  28. #define QSPI_WLEN_MAX_BITS 128
  29. #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
  30. #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  31. /* clock control */
  32. #define QSPI_CLK_EN BIT(31)
  33. #define QSPI_CLK_DIV_MAX 0xffff
  34. /* command */
  35. #define QSPI_EN_CS(n) (n << 28)
  36. #define QSPI_WLEN(n) ((n-1) << 19)
  37. #define QSPI_3_PIN BIT(18)
  38. #define QSPI_RD_SNGL BIT(16)
  39. #define QSPI_WR_SNGL (2 << 16)
  40. #define QSPI_INVAL (4 << 16)
  41. #define QSPI_RD_QUAD (7 << 16)
  42. /* device control */
  43. #define QSPI_CKPHA(n) (1 << (2 + n*8))
  44. #define QSPI_CSPOL(n) (1 << (1 + n*8))
  45. #define QSPI_CKPOL(n) (1 << (n*8))
  46. /* status */
  47. #define QSPI_WC BIT(1)
  48. #define QSPI_BUSY BIT(0)
  49. #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
  50. #define QSPI_XFER_DONE QSPI_WC
  51. #define MM_SWITCH 0x01
  52. #define MEM_CS(cs) ((cs + 1) << 8)
  53. #define MEM_CS_UNSELECT 0xfffff8ff
  54. #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
  55. #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
  56. #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
  57. #define QSPI_SETUP0_ADDR_SHIFT (8)
  58. #define QSPI_SETUP0_DBITS_SHIFT (10)
  59. #define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
  60. /* ti qspi register set */
  61. struct ti_qspi_regs {
  62. u32 pid;
  63. u32 pad0[3];
  64. u32 sysconfig;
  65. u32 pad1[3];
  66. u32 int_stat_raw;
  67. u32 int_stat_en;
  68. u32 int_en_set;
  69. u32 int_en_ctlr;
  70. u32 intc_eoi;
  71. u32 pad2[3];
  72. u32 clk_ctrl;
  73. u32 dc;
  74. u32 cmd;
  75. u32 status;
  76. u32 data;
  77. u32 setup0;
  78. u32 setup1;
  79. u32 setup2;
  80. u32 setup3;
  81. u32 memswitch;
  82. u32 data1;
  83. u32 data2;
  84. u32 data3;
  85. };
  86. /* ti qspi priv */
  87. struct ti_qspi_priv {
  88. void *memory_map;
  89. size_t mmap_size;
  90. uint max_hz;
  91. u32 num_cs;
  92. struct ti_qspi_regs *base;
  93. void *ctrl_mod_mmap;
  94. ulong fclk;
  95. unsigned int mode;
  96. u32 cmd;
  97. u32 dc;
  98. };
  99. static int ti_qspi_set_speed(struct udevice *bus, uint hz)
  100. {
  101. struct ti_qspi_priv *priv = dev_get_priv(bus);
  102. uint clk_div;
  103. if (!hz)
  104. clk_div = 0;
  105. else
  106. clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
  107. /* truncate clk_div value to QSPI_CLK_DIV_MAX */
  108. if (clk_div > QSPI_CLK_DIV_MAX)
  109. clk_div = QSPI_CLK_DIV_MAX;
  110. debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
  111. /* disable SCLK */
  112. writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
  113. &priv->base->clk_ctrl);
  114. /* enable SCLK and program the clk divider */
  115. writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
  116. return 0;
  117. }
  118. static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
  119. {
  120. writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
  121. /* dummy readl to ensure bus sync */
  122. readl(&priv->base->cmd);
  123. }
  124. static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
  125. {
  126. u32 val;
  127. val = readl(ctrl_mod_mmap);
  128. if (enable)
  129. val |= MEM_CS(cs);
  130. else
  131. val &= MEM_CS_UNSELECT;
  132. writel(val, ctrl_mod_mmap);
  133. }
  134. static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  135. const void *dout, void *din, unsigned long flags)
  136. {
  137. struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
  138. struct ti_qspi_priv *priv;
  139. struct udevice *bus;
  140. uint words = bitlen >> 3; /* fixed 8-bit word length */
  141. const uchar *txp = dout;
  142. uchar *rxp = din;
  143. uint status;
  144. int timeout;
  145. unsigned int cs = slave->cs;
  146. bus = dev->parent;
  147. priv = dev_get_priv(bus);
  148. if (cs > priv->num_cs) {
  149. debug("invalid qspi chip select\n");
  150. return -EINVAL;
  151. }
  152. if (bitlen == 0)
  153. return -1;
  154. if (bitlen % 8) {
  155. debug("spi_xfer: Non byte aligned SPI transfer\n");
  156. return -1;
  157. }
  158. /* Setup command reg */
  159. priv->cmd = 0;
  160. priv->cmd |= QSPI_WLEN(8);
  161. priv->cmd |= QSPI_EN_CS(cs);
  162. if (priv->mode & SPI_3WIRE)
  163. priv->cmd |= QSPI_3_PIN;
  164. priv->cmd |= 0xfff;
  165. while (words) {
  166. u8 xfer_len = 0;
  167. if (txp) {
  168. u32 cmd = priv->cmd;
  169. if (words >= QSPI_WLEN_MAX_BYTES) {
  170. u32 *txbuf = (u32 *)txp;
  171. u32 data;
  172. data = cpu_to_be32(*txbuf++);
  173. writel(data, &priv->base->data3);
  174. data = cpu_to_be32(*txbuf++);
  175. writel(data, &priv->base->data2);
  176. data = cpu_to_be32(*txbuf++);
  177. writel(data, &priv->base->data1);
  178. data = cpu_to_be32(*txbuf++);
  179. writel(data, &priv->base->data);
  180. cmd &= ~QSPI_WLEN_MASK;
  181. cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
  182. xfer_len = QSPI_WLEN_MAX_BYTES;
  183. } else {
  184. writeb(*txp, &priv->base->data);
  185. xfer_len = 1;
  186. }
  187. debug("tx cmd %08x dc %08x\n",
  188. cmd | QSPI_WR_SNGL, priv->dc);
  189. writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
  190. status = readl(&priv->base->status);
  191. timeout = QSPI_TIMEOUT;
  192. while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
  193. if (--timeout < 0) {
  194. printf("spi_xfer: TX timeout!\n");
  195. return -1;
  196. }
  197. status = readl(&priv->base->status);
  198. }
  199. txp += xfer_len;
  200. debug("tx done, status %08x\n", status);
  201. }
  202. if (rxp) {
  203. debug("rx cmd %08x dc %08x\n",
  204. ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
  205. writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
  206. status = readl(&priv->base->status);
  207. timeout = QSPI_TIMEOUT;
  208. while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
  209. if (--timeout < 0) {
  210. printf("spi_xfer: RX timeout!\n");
  211. return -1;
  212. }
  213. status = readl(&priv->base->status);
  214. }
  215. *rxp++ = readl(&priv->base->data);
  216. xfer_len = 1;
  217. debug("rx done, status %08x, read %02x\n",
  218. status, *(rxp-1));
  219. }
  220. words -= xfer_len;
  221. }
  222. /* Terminate frame */
  223. if (flags & SPI_XFER_END)
  224. ti_qspi_cs_deactivate(priv);
  225. return 0;
  226. }
  227. /* TODO: control from sf layer to here through dm-spi */
  228. static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
  229. {
  230. #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
  231. unsigned int addr = (unsigned int) (data);
  232. unsigned int edma_slot_num = 1;
  233. /* Invalidate the area, so no writeback into the RAM races with DMA */
  234. invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
  235. /* enable edma3 clocks */
  236. enable_edma3_clocks();
  237. /* Call edma3 api to do actual DMA transfer */
  238. edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
  239. /* disable edma3 clocks */
  240. disable_edma3_clocks();
  241. #else
  242. memcpy_fromio(data, offset, len);
  243. #endif
  244. *((unsigned int *)offset) += len;
  245. }
  246. static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
  247. u8 opcode, u8 data_nbits, u8 addr_width,
  248. u8 dummy_bytes)
  249. {
  250. u32 memval = opcode;
  251. switch (data_nbits) {
  252. case 4:
  253. memval |= QSPI_SETUP0_READ_QUAD;
  254. break;
  255. case 2:
  256. memval |= QSPI_SETUP0_READ_DUAL;
  257. break;
  258. default:
  259. memval |= QSPI_SETUP0_READ_NORMAL;
  260. break;
  261. }
  262. memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
  263. dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
  264. writel(memval, TI_QSPI_SETUP_REG(priv, cs));
  265. }
  266. static int ti_qspi_set_mode(struct udevice *bus, uint mode)
  267. {
  268. struct ti_qspi_priv *priv = dev_get_priv(bus);
  269. priv->dc = 0;
  270. if (mode & SPI_CPHA)
  271. priv->dc |= QSPI_CKPHA(0);
  272. if (mode & SPI_CPOL)
  273. priv->dc |= QSPI_CKPOL(0);
  274. if (mode & SPI_CS_HIGH)
  275. priv->dc |= QSPI_CSPOL(0);
  276. return 0;
  277. }
  278. static int ti_qspi_exec_mem_op(struct spi_slave *slave,
  279. const struct spi_mem_op *op)
  280. {
  281. struct dm_spi_slave_platdata *slave_plat;
  282. struct ti_qspi_priv *priv;
  283. struct udevice *bus;
  284. u32 from = 0;
  285. int ret = 0;
  286. bus = slave->dev->parent;
  287. priv = dev_get_priv(bus);
  288. slave_plat = dev_get_parent_platdata(slave->dev);
  289. /* Only optimize read path. */
  290. if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
  291. !op->addr.nbytes || op->addr.nbytes > 4)
  292. return -ENOTSUPP;
  293. /* Address exceeds MMIO window size, fall back to regular mode. */
  294. from = op->addr.val;
  295. if (from + op->data.nbytes > priv->mmap_size)
  296. return -ENOTSUPP;
  297. ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
  298. op->data.buswidth, op->addr.nbytes,
  299. op->dummy.nbytes);
  300. ti_qspi_copy_mmap((void *)op->data.buf.in,
  301. (void *)priv->memory_map + from, op->data.nbytes);
  302. return ret;
  303. }
  304. static int ti_qspi_claim_bus(struct udevice *dev)
  305. {
  306. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  307. struct ti_qspi_priv *priv;
  308. struct udevice *bus;
  309. bus = dev->parent;
  310. priv = dev_get_priv(bus);
  311. if (slave_plat->cs > priv->num_cs) {
  312. debug("invalid qspi chip select\n");
  313. return -EINVAL;
  314. }
  315. writel(MM_SWITCH, &priv->base->memswitch);
  316. if (priv->ctrl_mod_mmap)
  317. ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
  318. slave_plat->cs, true);
  319. writel(priv->dc, &priv->base->dc);
  320. writel(0, &priv->base->cmd);
  321. writel(0, &priv->base->data);
  322. priv->dc <<= slave_plat->cs * 8;
  323. writel(priv->dc, &priv->base->dc);
  324. return 0;
  325. }
  326. static int ti_qspi_release_bus(struct udevice *dev)
  327. {
  328. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  329. struct ti_qspi_priv *priv;
  330. struct udevice *bus;
  331. bus = dev->parent;
  332. priv = dev_get_priv(bus);
  333. writel(~MM_SWITCH, &priv->base->memswitch);
  334. if (priv->ctrl_mod_mmap)
  335. ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
  336. slave_plat->cs, false);
  337. writel(0, &priv->base->dc);
  338. writel(0, &priv->base->cmd);
  339. writel(0, &priv->base->data);
  340. writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
  341. return 0;
  342. }
  343. static int ti_qspi_probe(struct udevice *bus)
  344. {
  345. struct ti_qspi_priv *priv = dev_get_priv(bus);
  346. priv->fclk = dev_get_driver_data(bus);
  347. return 0;
  348. }
  349. static void *map_syscon_chipselects(struct udevice *bus)
  350. {
  351. #if CONFIG_IS_ENABLED(SYSCON)
  352. struct udevice *syscon;
  353. struct regmap *regmap;
  354. const fdt32_t *cell;
  355. int len, err;
  356. err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
  357. "syscon-chipselects", &syscon);
  358. if (err) {
  359. debug("%s: unable to find syscon device (%d)\n", __func__,
  360. err);
  361. return NULL;
  362. }
  363. regmap = syscon_get_regmap(syscon);
  364. if (IS_ERR(regmap)) {
  365. debug("%s: unable to find regmap (%ld)\n", __func__,
  366. PTR_ERR(regmap));
  367. return NULL;
  368. }
  369. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
  370. "syscon-chipselects", &len);
  371. if (len < 2*sizeof(fdt32_t)) {
  372. debug("%s: offset not available\n", __func__);
  373. return NULL;
  374. }
  375. return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
  376. #else
  377. fdt_addr_t addr;
  378. addr = devfdt_get_addr_index(bus, 2);
  379. return (addr == FDT_ADDR_T_NONE) ? NULL :
  380. map_physmem(addr, 0, MAP_NOCACHE);
  381. #endif
  382. }
  383. static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
  384. {
  385. struct ti_qspi_priv *priv = dev_get_priv(bus);
  386. const void *blob = gd->fdt_blob;
  387. int node = dev_of_offset(bus);
  388. fdt_addr_t mmap_addr;
  389. fdt_addr_t mmap_size;
  390. priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
  391. priv->base = map_physmem(devfdt_get_addr(bus),
  392. sizeof(struct ti_qspi_regs), MAP_NOCACHE);
  393. mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
  394. priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
  395. priv->mmap_size = mmap_size;
  396. priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
  397. if (priv->max_hz < 0) {
  398. debug("Error: Max frequency missing\n");
  399. return -ENODEV;
  400. }
  401. priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
  402. debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
  403. (int)priv->base, priv->max_hz);
  404. return 0;
  405. }
  406. static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
  407. .exec_op = ti_qspi_exec_mem_op,
  408. };
  409. static const struct dm_spi_ops ti_qspi_ops = {
  410. .claim_bus = ti_qspi_claim_bus,
  411. .release_bus = ti_qspi_release_bus,
  412. .xfer = ti_qspi_xfer,
  413. .set_speed = ti_qspi_set_speed,
  414. .set_mode = ti_qspi_set_mode,
  415. .mem_ops = &ti_qspi_mem_ops,
  416. };
  417. static const struct udevice_id ti_qspi_ids[] = {
  418. { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
  419. { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
  420. { }
  421. };
  422. U_BOOT_DRIVER(ti_qspi) = {
  423. .name = "ti_qspi",
  424. .id = UCLASS_SPI,
  425. .of_match = ti_qspi_ids,
  426. .ops = &ti_qspi_ops,
  427. .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
  428. .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
  429. .probe = ti_qspi_probe,
  430. };