tegra210_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NVIDIA Tegra210 QSPI controller driver
  4. *
  5. * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
  6. *
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch-tegra/clk_rst.h>
  14. #include <spi.h>
  15. #include <fdtdec.h>
  16. #include "tegra_spi.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /* COMMAND1 */
  19. #define QSPI_CMD1_GO BIT(31)
  20. #define QSPI_CMD1_M_S BIT(30)
  21. #define QSPI_CMD1_MODE_MASK GENMASK(1,0)
  22. #define QSPI_CMD1_MODE_SHIFT 28
  23. #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
  24. #define QSPI_CMD1_CS_SEL_SHIFT 26
  25. #define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
  26. #define QSPI_CMD1_CS_SW_HW BIT(21)
  27. #define QSPI_CMD1_CS_SW_VAL BIT(20)
  28. #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
  29. #define QSPI_CMD1_IDLE_SDA_SHIFT 18
  30. #define QSPI_CMD1_BIDIR BIT(17)
  31. #define QSPI_CMD1_LSBI_FE BIT(16)
  32. #define QSPI_CMD1_LSBY_FE BIT(15)
  33. #define QSPI_CMD1_BOTH_EN_BIT BIT(14)
  34. #define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
  35. #define QSPI_CMD1_RX_EN BIT(12)
  36. #define QSPI_CMD1_TX_EN BIT(11)
  37. #define QSPI_CMD1_PACKED BIT(5)
  38. #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
  39. #define QSPI_CMD1_BITLEN_SHIFT 0
  40. /* COMMAND2 */
  41. #define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
  42. #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
  43. #define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
  44. #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
  45. /* TRANSFER STATUS */
  46. #define QSPI_XFER_STS_RDY BIT(30)
  47. /* FIFO STATUS */
  48. #define QSPI_FIFO_STS_CS_INACTIVE BIT(31)
  49. #define QSPI_FIFO_STS_FRAME_END BIT(30)
  50. #define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
  51. #define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
  52. #define QSPI_FIFO_STS_ERR BIT(8)
  53. #define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7)
  54. #define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6)
  55. #define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5)
  56. #define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4)
  57. #define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
  58. #define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
  59. #define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
  60. #define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
  61. #define QSPI_TIMEOUT 1000
  62. struct qspi_regs {
  63. u32 command1; /* 000:QSPI_COMMAND1 register */
  64. u32 command2; /* 004:QSPI_COMMAND2 register */
  65. u32 timing1; /* 008:QSPI_CS_TIM1 register */
  66. u32 timing2; /* 00c:QSPI_CS_TIM2 register */
  67. u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
  68. u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
  69. u32 tx_data; /* 018:QSPI_TX_DATA register */
  70. u32 rx_data; /* 01c:QSPI_RX_DATA register */
  71. u32 dma_ctl; /* 020:QSPI_DMA_CTL register */
  72. u32 dma_blk; /* 024:QSPI_DMA_BLK register */
  73. u32 rsvd[56]; /* 028-107 reserved */
  74. u32 tx_fifo; /* 108:QSPI_FIFO1 register */
  75. u32 rsvd2[31]; /* 10c-187 reserved */
  76. u32 rx_fifo; /* 188:QSPI_FIFO2 register */
  77. u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */
  78. };
  79. struct tegra210_qspi_priv {
  80. struct qspi_regs *regs;
  81. unsigned int freq;
  82. unsigned int mode;
  83. int periph_id;
  84. int valid;
  85. int last_transaction_us;
  86. };
  87. static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
  88. {
  89. struct tegra_spi_platdata *plat = bus->platdata;
  90. plat->base = dev_read_addr(bus);
  91. plat->periph_id = clock_decode_periph_id(bus);
  92. if (plat->periph_id == PERIPH_ID_NONE) {
  93. debug("%s: could not decode periph id %d\n", __func__,
  94. plat->periph_id);
  95. return -FDT_ERR_NOTFOUND;
  96. }
  97. /* Use 500KHz as a suitable default */
  98. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  99. 500000);
  100. plat->deactivate_delay_us = dev_read_u32_default(bus,
  101. "spi-deactivate-delay",
  102. 0);
  103. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  104. __func__, plat->base, plat->periph_id, plat->frequency,
  105. plat->deactivate_delay_us);
  106. return 0;
  107. }
  108. static int tegra210_qspi_probe(struct udevice *bus)
  109. {
  110. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  111. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  112. priv->regs = (struct qspi_regs *)plat->base;
  113. struct qspi_regs *regs = priv->regs;
  114. priv->last_transaction_us = timer_get_us();
  115. priv->freq = plat->frequency;
  116. priv->periph_id = plat->periph_id;
  117. debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
  118. priv->periph_id);
  119. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  120. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
  121. /* Set tap delays here, clock change above resets QSPI controller */
  122. u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
  123. (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
  124. writel(reg, &regs->command2);
  125. debug("%s: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
  126. return 0;
  127. }
  128. static int tegra210_qspi_claim_bus(struct udevice *dev)
  129. {
  130. struct udevice *bus = dev->parent;
  131. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  132. struct qspi_regs *regs = priv->regs;
  133. debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
  134. /* Set master mode and sw controlled CS */
  135. setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
  136. (priv->mode << QSPI_CMD1_MODE_SHIFT));
  137. debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
  138. return 0;
  139. }
  140. /**
  141. * Activate the CS by driving it LOW
  142. *
  143. * @param slave Pointer to spi_slave to which controller has to
  144. * communicate with
  145. */
  146. static void spi_cs_activate(struct udevice *dev)
  147. {
  148. struct udevice *bus = dev->parent;
  149. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  150. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  151. /* If it's too soon to do another transaction, wait */
  152. if (pdata->deactivate_delay_us &&
  153. priv->last_transaction_us) {
  154. ulong delay_us; /* The delay completed so far */
  155. delay_us = timer_get_us() - priv->last_transaction_us;
  156. if (delay_us < pdata->deactivate_delay_us)
  157. udelay(pdata->deactivate_delay_us - delay_us);
  158. }
  159. clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  160. }
  161. /**
  162. * Deactivate the CS by driving it HIGH
  163. *
  164. * @param slave Pointer to spi_slave to which controller has to
  165. * communicate with
  166. */
  167. static void spi_cs_deactivate(struct udevice *dev)
  168. {
  169. struct udevice *bus = dev->parent;
  170. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  171. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  172. setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  173. /* Remember time of this transaction so we can honour the bus delay */
  174. if (pdata->deactivate_delay_us)
  175. priv->last_transaction_us = timer_get_us();
  176. debug("Deactivate CS, bus '%s'\n", bus->name);
  177. }
  178. static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  179. const void *data_out, void *data_in,
  180. unsigned long flags)
  181. {
  182. struct udevice *bus = dev->parent;
  183. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  184. struct qspi_regs *regs = priv->regs;
  185. u32 reg, tmpdout, tmpdin = 0;
  186. const u8 *dout = data_out;
  187. u8 *din = data_in;
  188. int num_bytes, tm, ret;
  189. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  190. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  191. if (bitlen % 8)
  192. return -1;
  193. num_bytes = bitlen / 8;
  194. ret = 0;
  195. /* clear all error status bits */
  196. reg = readl(&regs->fifo_status);
  197. writel(reg, &regs->fifo_status);
  198. /* flush RX/TX FIFOs */
  199. setbits_le32(&regs->fifo_status,
  200. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  201. QSPI_FIFO_STS_TX_FIFO_FLUSH));
  202. tm = QSPI_TIMEOUT;
  203. while ((tm && readl(&regs->fifo_status) &
  204. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  205. QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
  206. tm--;
  207. udelay(1);
  208. }
  209. if (!tm) {
  210. printf("%s: timeout during QSPI FIFO flush!\n",
  211. __func__);
  212. return -1;
  213. }
  214. /*
  215. * Notes:
  216. * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
  217. * 2. don't set RX_EN and TX_EN yet.
  218. * (SW needs to make sure that while programming the blk_size,
  219. * tx_en and rx_en bits must be zero)
  220. * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
  221. * i.e., both dout and din are not NULL.
  222. */
  223. clrsetbits_le32(&regs->command1,
  224. (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
  225. QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
  226. (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
  227. /* set xfer size to 1 block (32 bits) */
  228. writel(0, &regs->dma_blk);
  229. if (flags & SPI_XFER_BEGIN)
  230. spi_cs_activate(dev);
  231. /* handle data in 32-bit chunks */
  232. while (num_bytes > 0) {
  233. int bytes;
  234. tmpdout = 0;
  235. bytes = (num_bytes > 4) ? 4 : num_bytes;
  236. if (dout != NULL) {
  237. memcpy((void *)&tmpdout, (void *)dout, bytes);
  238. dout += bytes;
  239. num_bytes -= bytes;
  240. writel(tmpdout, &regs->tx_fifo);
  241. setbits_le32(&regs->command1, QSPI_CMD1_TX_EN);
  242. }
  243. if (din != NULL)
  244. setbits_le32(&regs->command1, QSPI_CMD1_RX_EN);
  245. /* clear ready bit */
  246. setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY);
  247. clrsetbits_le32(&regs->command1,
  248. QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
  249. (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
  250. /* Need to stabilize other reg bits before GO bit set.
  251. * As per the TRM:
  252. * "For successful operation at various freq combinations,
  253. * a minimum of 4-5 spi_clk cycle delay might be required
  254. * before enabling the PIO or DMA bits. The worst case delay
  255. * calculation can be done considering slowest qspi_clk as
  256. * 1MHz. Based on that 1us delay should be enough before
  257. * enabling PIO or DMA." Padded another 1us for safety.
  258. */
  259. udelay(2);
  260. setbits_le32(&regs->command1, QSPI_CMD1_GO);
  261. udelay(1);
  262. /*
  263. * Wait for SPI transmit FIFO to empty, or to time out.
  264. * The RX FIFO status will be read and cleared last
  265. */
  266. for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
  267. u32 fifo_status, xfer_status;
  268. xfer_status = readl(&regs->xfer_status);
  269. if (!(xfer_status & QSPI_XFER_STS_RDY))
  270. continue;
  271. fifo_status = readl(&regs->fifo_status);
  272. if (fifo_status & QSPI_FIFO_STS_ERR) {
  273. debug("%s: got a fifo error: ", __func__);
  274. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
  275. debug("tx FIFO overflow ");
  276. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
  277. debug("tx FIFO underrun ");
  278. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
  279. debug("rx FIFO overflow ");
  280. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
  281. debug("rx FIFO underrun ");
  282. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
  283. debug("tx FIFO full ");
  284. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
  285. debug("tx FIFO empty ");
  286. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
  287. debug("rx FIFO full ");
  288. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
  289. debug("rx FIFO empty ");
  290. debug("\n");
  291. break;
  292. }
  293. if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
  294. tmpdin = readl(&regs->rx_fifo);
  295. if (din != NULL) {
  296. memcpy(din, &tmpdin, bytes);
  297. din += bytes;
  298. num_bytes -= bytes;
  299. }
  300. }
  301. break;
  302. }
  303. if (tm >= QSPI_TIMEOUT)
  304. ret = tm;
  305. /* clear ACK RDY, etc. bits */
  306. writel(readl(&regs->fifo_status), &regs->fifo_status);
  307. }
  308. if (flags & SPI_XFER_END)
  309. spi_cs_deactivate(dev);
  310. debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
  311. __func__, tmpdin, readl(&regs->fifo_status));
  312. if (ret) {
  313. printf("%s: timeout during SPI transfer, tm %d\n",
  314. __func__, ret);
  315. return -1;
  316. }
  317. return ret;
  318. }
  319. static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
  320. {
  321. struct tegra_spi_platdata *plat = bus->platdata;
  322. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  323. if (speed > plat->frequency)
  324. speed = plat->frequency;
  325. priv->freq = speed;
  326. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  327. return 0;
  328. }
  329. static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
  330. {
  331. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  332. priv->mode = mode;
  333. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  334. return 0;
  335. }
  336. static const struct dm_spi_ops tegra210_qspi_ops = {
  337. .claim_bus = tegra210_qspi_claim_bus,
  338. .xfer = tegra210_qspi_xfer,
  339. .set_speed = tegra210_qspi_set_speed,
  340. .set_mode = tegra210_qspi_set_mode,
  341. /*
  342. * cs_info is not needed, since we require all chip selects to be
  343. * in the device tree explicitly
  344. */
  345. };
  346. static const struct udevice_id tegra210_qspi_ids[] = {
  347. { .compatible = "nvidia,tegra210-qspi" },
  348. { }
  349. };
  350. U_BOOT_DRIVER(tegra210_qspi) = {
  351. .name = "tegra210-qspi",
  352. .id = UCLASS_SPI,
  353. .of_match = tegra210_qspi_ids,
  354. .ops = &tegra210_qspi_ops,
  355. .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata,
  356. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  357. .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv),
  358. .per_child_auto_alloc_size = sizeof(struct spi_slave),
  359. .probe = tegra210_qspi_probe,
  360. };