tegra114_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NVIDIA Tegra SPI controller (T114 and later)
  4. *
  5. * Copyright (c) 2010-2013 NVIDIA Corporation
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <time.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch-tegra/clk_rst.h>
  13. #include <spi.h>
  14. #include "tegra_spi.h"
  15. /* COMMAND1 */
  16. #define SPI_CMD1_GO BIT(31)
  17. #define SPI_CMD1_M_S BIT(30)
  18. #define SPI_CMD1_MODE_MASK GENMASK(1, 0)
  19. #define SPI_CMD1_MODE_SHIFT 28
  20. #define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
  21. #define SPI_CMD1_CS_SEL_SHIFT 26
  22. #define SPI_CMD1_CS_POL_INACTIVE3 BIT(25)
  23. #define SPI_CMD1_CS_POL_INACTIVE2 BIT(24)
  24. #define SPI_CMD1_CS_POL_INACTIVE1 BIT(23)
  25. #define SPI_CMD1_CS_POL_INACTIVE0 BIT(22)
  26. #define SPI_CMD1_CS_SW_HW BIT(21)
  27. #define SPI_CMD1_CS_SW_VAL BIT(20)
  28. #define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
  29. #define SPI_CMD1_IDLE_SDA_SHIFT 18
  30. #define SPI_CMD1_BIDIR BIT(17)
  31. #define SPI_CMD1_LSBI_FE BIT(16)
  32. #define SPI_CMD1_LSBY_FE BIT(15)
  33. #define SPI_CMD1_BOTH_EN_BIT BIT(14)
  34. #define SPI_CMD1_BOTH_EN_BYTE BIT(13)
  35. #define SPI_CMD1_RX_EN BIT(12)
  36. #define SPI_CMD1_TX_EN BIT(11)
  37. #define SPI_CMD1_PACKED BIT(5)
  38. #define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
  39. #define SPI_CMD1_BIT_LEN_SHIFT 0
  40. /* COMMAND2 */
  41. #define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
  42. #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
  43. #define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
  44. #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
  45. /* TRANSFER STATUS */
  46. #define SPI_XFER_STS_RDY BIT(30)
  47. /* FIFO STATUS */
  48. #define SPI_FIFO_STS_CS_INACTIVE BIT(31)
  49. #define SPI_FIFO_STS_FRAME_END BIT(30)
  50. #define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
  51. #define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
  52. #define SPI_FIFO_STS_ERR BIT(8)
  53. #define SPI_FIFO_STS_TX_FIFO_OVF BIT(7)
  54. #define SPI_FIFO_STS_TX_FIFO_UNR BIT(6)
  55. #define SPI_FIFO_STS_RX_FIFO_OVF BIT(5)
  56. #define SPI_FIFO_STS_RX_FIFO_UNR BIT(4)
  57. #define SPI_FIFO_STS_TX_FIFO_FULL BIT(3)
  58. #define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
  59. #define SPI_FIFO_STS_RX_FIFO_FULL BIT(1)
  60. #define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
  61. #define SPI_TIMEOUT 1000
  62. #define TEGRA_SPI_MAX_FREQ 52000000
  63. struct spi_regs {
  64. u32 command1; /* 000:SPI_COMMAND1 register */
  65. u32 command2; /* 004:SPI_COMMAND2 register */
  66. u32 timing1; /* 008:SPI_CS_TIM1 register */
  67. u32 timing2; /* 00c:SPI_CS_TIM2 register */
  68. u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
  69. u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
  70. u32 tx_data; /* 018:SPI_TX_DATA register */
  71. u32 rx_data; /* 01c:SPI_RX_DATA register */
  72. u32 dma_ctl; /* 020:SPI_DMA_CTL register */
  73. u32 dma_blk; /* 024:SPI_DMA_BLK register */
  74. u32 rsvd[56]; /* 028-107 reserved */
  75. u32 tx_fifo; /* 108:SPI_FIFO1 register */
  76. u32 rsvd2[31]; /* 10c-187 reserved */
  77. u32 rx_fifo; /* 188:SPI_FIFO2 register */
  78. u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
  79. };
  80. struct tegra114_spi_priv {
  81. struct spi_regs *regs;
  82. unsigned int freq;
  83. unsigned int mode;
  84. int periph_id;
  85. int valid;
  86. int last_transaction_us;
  87. };
  88. static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
  89. {
  90. struct tegra_spi_platdata *plat = bus->platdata;
  91. plat->base = dev_read_addr(bus);
  92. plat->periph_id = clock_decode_periph_id(bus);
  93. if (plat->periph_id == PERIPH_ID_NONE) {
  94. debug("%s: could not decode periph id %d\n", __func__,
  95. plat->periph_id);
  96. return -FDT_ERR_NOTFOUND;
  97. }
  98. /* Use 500KHz as a suitable default */
  99. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  100. 500000);
  101. plat->deactivate_delay_us = dev_read_u32_default(bus,
  102. "spi-deactivate-delay", 0);
  103. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  104. __func__, plat->base, plat->periph_id, plat->frequency,
  105. plat->deactivate_delay_us);
  106. return 0;
  107. }
  108. static int tegra114_spi_probe(struct udevice *bus)
  109. {
  110. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  111. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  112. struct spi_regs *regs;
  113. ulong rate;
  114. priv->regs = (struct spi_regs *)plat->base;
  115. regs = priv->regs;
  116. priv->last_transaction_us = timer_get_us();
  117. priv->freq = plat->frequency;
  118. priv->periph_id = plat->periph_id;
  119. /*
  120. * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
  121. * back to the oscillator if that is too fast.
  122. */
  123. rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  124. priv->freq);
  125. if (rate > priv->freq + 100000) {
  126. rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
  127. priv->freq);
  128. if (rate != priv->freq) {
  129. printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
  130. bus->name, priv->freq, rate);
  131. }
  132. }
  133. udelay(plat->deactivate_delay_us);
  134. /* Clear stale status here */
  135. setbits_le32(&regs->fifo_status,
  136. SPI_FIFO_STS_ERR |
  137. SPI_FIFO_STS_TX_FIFO_OVF |
  138. SPI_FIFO_STS_TX_FIFO_UNR |
  139. SPI_FIFO_STS_RX_FIFO_OVF |
  140. SPI_FIFO_STS_RX_FIFO_UNR |
  141. SPI_FIFO_STS_TX_FIFO_FULL |
  142. SPI_FIFO_STS_TX_FIFO_EMPTY |
  143. SPI_FIFO_STS_RX_FIFO_FULL |
  144. SPI_FIFO_STS_RX_FIFO_EMPTY);
  145. debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
  146. setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
  147. (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
  148. debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
  149. return 0;
  150. }
  151. /**
  152. * Activate the CS by driving it LOW
  153. *
  154. * @param slave Pointer to spi_slave to which controller has to
  155. * communicate with
  156. */
  157. static void spi_cs_activate(struct udevice *dev)
  158. {
  159. struct udevice *bus = dev->parent;
  160. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  161. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  162. /* If it's too soon to do another transaction, wait */
  163. if (pdata->deactivate_delay_us &&
  164. priv->last_transaction_us) {
  165. ulong delay_us; /* The delay completed so far */
  166. delay_us = timer_get_us() - priv->last_transaction_us;
  167. if (delay_us < pdata->deactivate_delay_us)
  168. udelay(pdata->deactivate_delay_us - delay_us);
  169. }
  170. clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
  171. }
  172. /**
  173. * Deactivate the CS by driving it HIGH
  174. *
  175. * @param slave Pointer to spi_slave to which controller has to
  176. * communicate with
  177. */
  178. static void spi_cs_deactivate(struct udevice *dev)
  179. {
  180. struct udevice *bus = dev->parent;
  181. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  182. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  183. setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
  184. /* Remember time of this transaction so we can honour the bus delay */
  185. if (pdata->deactivate_delay_us)
  186. priv->last_transaction_us = timer_get_us();
  187. debug("Deactivate CS, bus '%s'\n", bus->name);
  188. }
  189. static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
  190. const void *data_out, void *data_in,
  191. unsigned long flags)
  192. {
  193. struct udevice *bus = dev->parent;
  194. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  195. struct spi_regs *regs = priv->regs;
  196. u32 reg, tmpdout, tmpdin = 0;
  197. const u8 *dout = data_out;
  198. u8 *din = data_in;
  199. int num_bytes;
  200. int ret;
  201. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  202. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  203. if (bitlen % 8)
  204. return -1;
  205. num_bytes = bitlen / 8;
  206. ret = 0;
  207. if (flags & SPI_XFER_BEGIN)
  208. spi_cs_activate(dev);
  209. /* clear all error status bits */
  210. reg = readl(&regs->fifo_status);
  211. writel(reg, &regs->fifo_status);
  212. clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
  213. SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
  214. (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
  215. /* set xfer size to 1 block (32 bits) */
  216. writel(0, &regs->dma_blk);
  217. /* handle data in 32-bit chunks */
  218. while (num_bytes > 0) {
  219. int bytes;
  220. int tm, i;
  221. tmpdout = 0;
  222. bytes = (num_bytes > 4) ? 4 : num_bytes;
  223. if (dout != NULL) {
  224. for (i = 0; i < bytes; ++i)
  225. tmpdout = (tmpdout << 8) | dout[i];
  226. dout += bytes;
  227. }
  228. num_bytes -= bytes;
  229. /* clear ready bit */
  230. setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
  231. clrsetbits_le32(&regs->command1,
  232. SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
  233. (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
  234. writel(tmpdout, &regs->tx_fifo);
  235. setbits_le32(&regs->command1, SPI_CMD1_GO);
  236. /*
  237. * Wait for SPI transmit FIFO to empty, or to time out.
  238. * The RX FIFO status will be read and cleared last
  239. */
  240. for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
  241. u32 fifo_status, xfer_status;
  242. xfer_status = readl(&regs->xfer_status);
  243. if (!(xfer_status & SPI_XFER_STS_RDY))
  244. continue;
  245. fifo_status = readl(&regs->fifo_status);
  246. if (fifo_status & SPI_FIFO_STS_ERR) {
  247. debug("%s: got a fifo error: ", __func__);
  248. if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
  249. debug("tx FIFO overflow ");
  250. if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
  251. debug("tx FIFO underrun ");
  252. if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
  253. debug("rx FIFO overflow ");
  254. if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
  255. debug("rx FIFO underrun ");
  256. if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
  257. debug("tx FIFO full ");
  258. if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
  259. debug("tx FIFO empty ");
  260. if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
  261. debug("rx FIFO full ");
  262. if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
  263. debug("rx FIFO empty ");
  264. debug("\n");
  265. break;
  266. }
  267. if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
  268. tmpdin = readl(&regs->rx_fifo);
  269. /* swap bytes read in */
  270. if (din != NULL) {
  271. for (i = bytes - 1; i >= 0; --i) {
  272. din[i] = tmpdin & 0xff;
  273. tmpdin >>= 8;
  274. }
  275. din += bytes;
  276. }
  277. /* We can exit when we've had both RX and TX */
  278. break;
  279. }
  280. }
  281. if (tm >= SPI_TIMEOUT)
  282. ret = tm;
  283. /* clear ACK RDY, etc. bits */
  284. writel(readl(&regs->fifo_status), &regs->fifo_status);
  285. }
  286. if (flags & SPI_XFER_END)
  287. spi_cs_deactivate(dev);
  288. debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
  289. __func__, tmpdin, readl(&regs->fifo_status));
  290. if (ret) {
  291. printf("%s: timeout during SPI transfer, tm %d\n",
  292. __func__, ret);
  293. return -1;
  294. }
  295. return ret;
  296. }
  297. static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
  298. {
  299. struct tegra_spi_platdata *plat = bus->platdata;
  300. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  301. if (speed > plat->frequency)
  302. speed = plat->frequency;
  303. priv->freq = speed;
  304. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  305. return 0;
  306. }
  307. static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
  308. {
  309. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  310. priv->mode = mode;
  311. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  312. return 0;
  313. }
  314. static const struct dm_spi_ops tegra114_spi_ops = {
  315. .xfer = tegra114_spi_xfer,
  316. .set_speed = tegra114_spi_set_speed,
  317. .set_mode = tegra114_spi_set_mode,
  318. /*
  319. * cs_info is not needed, since we require all chip selects to be
  320. * in the device tree explicitly
  321. */
  322. };
  323. static const struct udevice_id tegra114_spi_ids[] = {
  324. { .compatible = "nvidia,tegra114-spi" },
  325. { }
  326. };
  327. U_BOOT_DRIVER(tegra114_spi) = {
  328. .name = "tegra114_spi",
  329. .id = UCLASS_SPI,
  330. .of_match = tegra114_spi_ids,
  331. .ops = &tegra114_spi_ops,
  332. .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
  333. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  334. .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
  335. .probe = tegra114_spi_probe,
  336. };