stm32_spi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  4. *
  5. * Driver for STMicroelectronics Serial peripheral interface (SPI)
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <reset.h>
  13. #include <spi.h>
  14. #include <dm/device_compat.h>
  15. #include <asm/io.h>
  16. #include <asm/gpio.h>
  17. #include <linux/bitfield.h>
  18. #include <linux/iopoll.h>
  19. /* STM32 SPI registers */
  20. #define STM32_SPI_CR1 0x00
  21. #define STM32_SPI_CR2 0x04
  22. #define STM32_SPI_CFG1 0x08
  23. #define STM32_SPI_CFG2 0x0C
  24. #define STM32_SPI_SR 0x14
  25. #define STM32_SPI_IFCR 0x18
  26. #define STM32_SPI_TXDR 0x20
  27. #define STM32_SPI_RXDR 0x30
  28. #define STM32_SPI_I2SCFGR 0x50
  29. /* STM32_SPI_CR1 bit fields */
  30. #define SPI_CR1_SPE BIT(0)
  31. #define SPI_CR1_MASRX BIT(8)
  32. #define SPI_CR1_CSTART BIT(9)
  33. #define SPI_CR1_CSUSP BIT(10)
  34. #define SPI_CR1_HDDIR BIT(11)
  35. #define SPI_CR1_SSI BIT(12)
  36. /* STM32_SPI_CR2 bit fields */
  37. #define SPI_CR2_TSIZE GENMASK(15, 0)
  38. /* STM32_SPI_CFG1 bit fields */
  39. #define SPI_CFG1_DSIZE GENMASK(4, 0)
  40. #define SPI_CFG1_DSIZE_MIN 3
  41. #define SPI_CFG1_FTHLV_SHIFT 5
  42. #define SPI_CFG1_FTHLV GENMASK(8, 5)
  43. #define SPI_CFG1_MBR_SHIFT 28
  44. #define SPI_CFG1_MBR GENMASK(30, 28)
  45. #define SPI_CFG1_MBR_MIN 0
  46. #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
  47. /* STM32_SPI_CFG2 bit fields */
  48. #define SPI_CFG2_COMM_SHIFT 17
  49. #define SPI_CFG2_COMM GENMASK(18, 17)
  50. #define SPI_CFG2_MASTER BIT(22)
  51. #define SPI_CFG2_LSBFRST BIT(23)
  52. #define SPI_CFG2_CPHA BIT(24)
  53. #define SPI_CFG2_CPOL BIT(25)
  54. #define SPI_CFG2_SSM BIT(26)
  55. #define SPI_CFG2_AFCNTR BIT(31)
  56. /* STM32_SPI_SR bit fields */
  57. #define SPI_SR_RXP BIT(0)
  58. #define SPI_SR_TXP BIT(1)
  59. #define SPI_SR_EOT BIT(3)
  60. #define SPI_SR_TXTF BIT(4)
  61. #define SPI_SR_OVR BIT(6)
  62. #define SPI_SR_SUSP BIT(11)
  63. #define SPI_SR_RXPLVL_SHIFT 13
  64. #define SPI_SR_RXPLVL GENMASK(14, 13)
  65. #define SPI_SR_RXWNE BIT(15)
  66. /* STM32_SPI_IFCR bit fields */
  67. #define SPI_IFCR_ALL GENMASK(11, 3)
  68. /* STM32_SPI_I2SCFGR bit fields */
  69. #define SPI_I2SCFGR_I2SMOD BIT(0)
  70. #define MAX_CS_COUNT 4
  71. /* SPI Master Baud Rate min/max divisor */
  72. #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
  73. #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
  74. #define STM32_SPI_TIMEOUT_US 100000
  75. /* SPI Communication mode */
  76. #define SPI_FULL_DUPLEX 0
  77. #define SPI_SIMPLEX_TX 1
  78. #define SPI_SIMPLEX_RX 2
  79. #define SPI_HALF_DUPLEX 3
  80. struct stm32_spi_priv {
  81. void __iomem *base;
  82. struct clk clk;
  83. struct reset_ctl rst_ctl;
  84. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  85. ulong bus_clk_rate;
  86. unsigned int fifo_size;
  87. unsigned int cur_bpw;
  88. unsigned int cur_hz;
  89. unsigned int cur_xferlen; /* current transfer length in bytes */
  90. unsigned int tx_len; /* number of data to be written in bytes */
  91. unsigned int rx_len; /* number of data to be read in bytes */
  92. const void *tx_buf; /* data to be written, or NULL */
  93. void *rx_buf; /* data to be read, or NULL */
  94. u32 cur_mode;
  95. bool cs_high;
  96. };
  97. static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
  98. {
  99. while ((priv->tx_len > 0) &&
  100. (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
  101. u32 offs = priv->cur_xferlen - priv->tx_len;
  102. if (priv->tx_len >= sizeof(u32) &&
  103. IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
  104. const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
  105. writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
  106. priv->tx_len -= sizeof(u32);
  107. } else if (priv->tx_len >= sizeof(u16) &&
  108. IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
  109. const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
  110. writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
  111. priv->tx_len -= sizeof(u16);
  112. } else {
  113. const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
  114. writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
  115. priv->tx_len -= sizeof(u8);
  116. }
  117. }
  118. debug("%s: %d bytes left\n", __func__, priv->tx_len);
  119. }
  120. static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
  121. {
  122. u32 sr = readl(priv->base + STM32_SPI_SR);
  123. u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
  124. while ((priv->rx_len > 0) &&
  125. ((sr & SPI_SR_RXP) ||
  126. ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
  127. u32 offs = priv->cur_xferlen - priv->rx_len;
  128. if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
  129. (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
  130. u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
  131. *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
  132. priv->rx_len -= sizeof(u32);
  133. } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
  134. (priv->rx_len >= sizeof(u16) ||
  135. (!(sr & SPI_SR_RXWNE) &&
  136. (rxplvl >= 2 || priv->cur_bpw > 8)))) {
  137. u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
  138. *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
  139. priv->rx_len -= sizeof(u16);
  140. } else {
  141. u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
  142. *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
  143. priv->rx_len -= sizeof(u8);
  144. }
  145. sr = readl(priv->base + STM32_SPI_SR);
  146. rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
  147. }
  148. debug("%s: %d bytes left\n", __func__, priv->rx_len);
  149. }
  150. static int stm32_spi_enable(struct stm32_spi_priv *priv)
  151. {
  152. debug("%s\n", __func__);
  153. /* Enable the SPI hardware */
  154. setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
  155. return 0;
  156. }
  157. static int stm32_spi_disable(struct stm32_spi_priv *priv)
  158. {
  159. debug("%s\n", __func__);
  160. /* Disable the SPI hardware */
  161. clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
  162. return 0;
  163. }
  164. static int stm32_spi_claim_bus(struct udevice *slave)
  165. {
  166. struct udevice *bus = dev_get_parent(slave);
  167. struct stm32_spi_priv *priv = dev_get_priv(bus);
  168. debug("%s\n", __func__);
  169. /* Enable the SPI hardware */
  170. return stm32_spi_enable(priv);
  171. }
  172. static int stm32_spi_release_bus(struct udevice *slave)
  173. {
  174. struct udevice *bus = dev_get_parent(slave);
  175. struct stm32_spi_priv *priv = dev_get_priv(bus);
  176. debug("%s\n", __func__);
  177. /* Disable the SPI hardware */
  178. return stm32_spi_disable(priv);
  179. }
  180. static void stm32_spi_stopxfer(struct udevice *dev)
  181. {
  182. struct stm32_spi_priv *priv = dev_get_priv(dev);
  183. u32 cr1, sr;
  184. int ret;
  185. debug("%s\n", __func__);
  186. cr1 = readl(priv->base + STM32_SPI_CR1);
  187. if (!(cr1 & SPI_CR1_SPE))
  188. return;
  189. /* Wait on EOT or suspend the flow */
  190. ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
  191. !(sr & SPI_SR_EOT), 100000);
  192. if (ret < 0) {
  193. if (cr1 & SPI_CR1_CSTART) {
  194. writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
  195. if (readl_poll_timeout(priv->base + STM32_SPI_SR,
  196. sr, !(sr & SPI_SR_SUSP),
  197. 100000) < 0)
  198. dev_err(dev, "Suspend request timeout\n");
  199. }
  200. }
  201. /* clear status flags */
  202. setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
  203. }
  204. static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
  205. {
  206. struct stm32_spi_priv *priv = dev_get_priv(dev);
  207. debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
  208. if (cs >= MAX_CS_COUNT)
  209. return -ENODEV;
  210. if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
  211. return -EINVAL;
  212. if (priv->cs_high)
  213. enable = !enable;
  214. return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
  215. }
  216. static int stm32_spi_set_mode(struct udevice *bus, uint mode)
  217. {
  218. struct stm32_spi_priv *priv = dev_get_priv(bus);
  219. u32 cfg2_clrb = 0, cfg2_setb = 0;
  220. debug("%s: mode=%d\n", __func__, mode);
  221. if (mode & SPI_CPOL)
  222. cfg2_setb |= SPI_CFG2_CPOL;
  223. else
  224. cfg2_clrb |= SPI_CFG2_CPOL;
  225. if (mode & SPI_CPHA)
  226. cfg2_setb |= SPI_CFG2_CPHA;
  227. else
  228. cfg2_clrb |= SPI_CFG2_CPHA;
  229. if (mode & SPI_LSB_FIRST)
  230. cfg2_setb |= SPI_CFG2_LSBFRST;
  231. else
  232. cfg2_clrb |= SPI_CFG2_LSBFRST;
  233. if (cfg2_clrb || cfg2_setb)
  234. clrsetbits_le32(priv->base + STM32_SPI_CFG2,
  235. cfg2_clrb, cfg2_setb);
  236. if (mode & SPI_CS_HIGH)
  237. priv->cs_high = true;
  238. else
  239. priv->cs_high = false;
  240. return 0;
  241. }
  242. static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
  243. {
  244. struct stm32_spi_priv *priv = dev_get_priv(dev);
  245. u32 fthlv, half_fifo;
  246. /* data packet should not exceed 1/2 of fifo space */
  247. half_fifo = (priv->fifo_size / 2);
  248. /* data_packet should not exceed transfer length */
  249. fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
  250. /* align packet size with data registers access */
  251. fthlv -= (fthlv % 4);
  252. if (!fthlv)
  253. fthlv = 1;
  254. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
  255. (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
  256. return 0;
  257. }
  258. static int stm32_spi_set_speed(struct udevice *bus, uint hz)
  259. {
  260. struct stm32_spi_priv *priv = dev_get_priv(bus);
  261. u32 mbrdiv;
  262. long div;
  263. debug("%s: hz=%d\n", __func__, hz);
  264. if (priv->cur_hz == hz)
  265. return 0;
  266. div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
  267. if (div < STM32_MBR_DIV_MIN ||
  268. div > STM32_MBR_DIV_MAX)
  269. return -EINVAL;
  270. /* Determine the first power of 2 greater than or equal to div */
  271. if (div & (div - 1))
  272. mbrdiv = fls(div);
  273. else
  274. mbrdiv = fls(div) - 1;
  275. if (!mbrdiv)
  276. return -EINVAL;
  277. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
  278. (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
  279. priv->cur_hz = hz;
  280. return 0;
  281. }
  282. static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
  283. const void *dout, void *din, unsigned long flags)
  284. {
  285. struct udevice *bus = dev_get_parent(slave);
  286. struct dm_spi_slave_platdata *slave_plat;
  287. struct stm32_spi_priv *priv = dev_get_priv(bus);
  288. u32 sr;
  289. u32 ifcr = 0;
  290. u32 xferlen;
  291. u32 mode;
  292. int xfer_status = 0;
  293. xferlen = bitlen / 8;
  294. if (xferlen <= SPI_CR2_TSIZE)
  295. writel(xferlen, priv->base + STM32_SPI_CR2);
  296. else
  297. return -EMSGSIZE;
  298. priv->tx_buf = dout;
  299. priv->rx_buf = din;
  300. priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
  301. priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
  302. mode = SPI_FULL_DUPLEX;
  303. if (!priv->tx_buf)
  304. mode = SPI_SIMPLEX_RX;
  305. else if (!priv->rx_buf)
  306. mode = SPI_SIMPLEX_TX;
  307. if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
  308. priv->cur_mode = mode;
  309. priv->cur_xferlen = xferlen;
  310. /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
  311. stm32_spi_disable(priv);
  312. clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
  313. mode << SPI_CFG2_COMM_SHIFT);
  314. stm32_spi_set_fthlv(bus, xferlen);
  315. /* Enable the SPI hardware */
  316. stm32_spi_enable(priv);
  317. }
  318. debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
  319. priv->tx_len, priv->rx_len);
  320. slave_plat = dev_get_parent_platdata(slave);
  321. if (flags & SPI_XFER_BEGIN)
  322. stm32_spi_set_cs(bus, slave_plat->cs, false);
  323. /* Be sure to have data in fifo before starting data transfer */
  324. if (priv->tx_buf)
  325. stm32_spi_write_txfifo(priv);
  326. setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
  327. while (1) {
  328. sr = readl(priv->base + STM32_SPI_SR);
  329. if (sr & SPI_SR_OVR) {
  330. dev_err(bus, "Overrun: RX data lost\n");
  331. xfer_status = -EIO;
  332. break;
  333. }
  334. if (sr & SPI_SR_SUSP) {
  335. dev_warn(bus, "System too slow is limiting data throughput\n");
  336. if (priv->rx_buf && priv->rx_len > 0)
  337. stm32_spi_read_rxfifo(priv);
  338. ifcr |= SPI_SR_SUSP;
  339. }
  340. if (sr & SPI_SR_TXTF)
  341. ifcr |= SPI_SR_TXTF;
  342. if (sr & SPI_SR_TXP)
  343. if (priv->tx_buf && priv->tx_len > 0)
  344. stm32_spi_write_txfifo(priv);
  345. if (sr & SPI_SR_RXP)
  346. if (priv->rx_buf && priv->rx_len > 0)
  347. stm32_spi_read_rxfifo(priv);
  348. if (sr & SPI_SR_EOT) {
  349. if (priv->rx_buf && priv->rx_len > 0)
  350. stm32_spi_read_rxfifo(priv);
  351. break;
  352. }
  353. writel(ifcr, priv->base + STM32_SPI_IFCR);
  354. }
  355. /* clear status flags */
  356. setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
  357. stm32_spi_stopxfer(bus);
  358. if (flags & SPI_XFER_END)
  359. stm32_spi_set_cs(bus, slave_plat->cs, true);
  360. return xfer_status;
  361. }
  362. static int stm32_spi_get_fifo_size(struct udevice *dev)
  363. {
  364. struct stm32_spi_priv *priv = dev_get_priv(dev);
  365. u32 count = 0;
  366. stm32_spi_enable(priv);
  367. while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
  368. writeb(++count, priv->base + STM32_SPI_TXDR);
  369. stm32_spi_disable(priv);
  370. debug("%s %d x 8-bit fifo size\n", __func__, count);
  371. return count;
  372. }
  373. static int stm32_spi_probe(struct udevice *dev)
  374. {
  375. struct stm32_spi_priv *priv = dev_get_priv(dev);
  376. unsigned long clk_rate;
  377. int ret;
  378. unsigned int i;
  379. priv->base = dev_remap_addr(dev);
  380. if (!priv->base)
  381. return -EINVAL;
  382. /* enable clock */
  383. ret = clk_get_by_index(dev, 0, &priv->clk);
  384. if (ret < 0)
  385. return ret;
  386. ret = clk_enable(&priv->clk);
  387. if (ret < 0)
  388. return ret;
  389. clk_rate = clk_get_rate(&priv->clk);
  390. if (!clk_rate) {
  391. ret = -EINVAL;
  392. goto clk_err;
  393. }
  394. priv->bus_clk_rate = clk_rate;
  395. /* perform reset */
  396. ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
  397. if (ret < 0)
  398. goto clk_err;
  399. reset_assert(&priv->rst_ctl);
  400. udelay(2);
  401. reset_deassert(&priv->rst_ctl);
  402. ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
  403. ARRAY_SIZE(priv->cs_gpios), 0);
  404. if (ret < 0) {
  405. pr_err("Can't get %s cs gpios: %d", dev->name, ret);
  406. goto reset_err;
  407. }
  408. priv->fifo_size = stm32_spi_get_fifo_size(dev);
  409. priv->cur_mode = SPI_FULL_DUPLEX;
  410. priv->cur_xferlen = 0;
  411. priv->cur_bpw = SPI_DEFAULT_WORDLEN;
  412. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
  413. priv->cur_bpw - 1);
  414. for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
  415. if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
  416. continue;
  417. dm_gpio_set_dir_flags(&priv->cs_gpios[i],
  418. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  419. }
  420. /* Ensure I2SMOD bit is kept cleared */
  421. clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
  422. /*
  423. * - SS input value high
  424. * - transmitter half duplex direction
  425. * - automatic communication suspend when RX-Fifo is full
  426. */
  427. setbits_le32(priv->base + STM32_SPI_CR1,
  428. SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
  429. /*
  430. * - Set the master mode (default Motorola mode)
  431. * - Consider 1 master/n slaves configuration and
  432. * SS input value is determined by the SSI bit
  433. * - keep control of all associated GPIOs
  434. */
  435. setbits_le32(priv->base + STM32_SPI_CFG2,
  436. SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
  437. return 0;
  438. reset_err:
  439. reset_free(&priv->rst_ctl);
  440. clk_err:
  441. clk_disable(&priv->clk);
  442. clk_free(&priv->clk);
  443. return ret;
  444. };
  445. static int stm32_spi_remove(struct udevice *dev)
  446. {
  447. struct stm32_spi_priv *priv = dev_get_priv(dev);
  448. int ret;
  449. stm32_spi_stopxfer(dev);
  450. stm32_spi_disable(priv);
  451. ret = reset_assert(&priv->rst_ctl);
  452. if (ret < 0)
  453. return ret;
  454. reset_free(&priv->rst_ctl);
  455. ret = clk_disable(&priv->clk);
  456. if (ret < 0)
  457. return ret;
  458. clk_free(&priv->clk);
  459. return ret;
  460. };
  461. static const struct dm_spi_ops stm32_spi_ops = {
  462. .claim_bus = stm32_spi_claim_bus,
  463. .release_bus = stm32_spi_release_bus,
  464. .set_mode = stm32_spi_set_mode,
  465. .set_speed = stm32_spi_set_speed,
  466. .xfer = stm32_spi_xfer,
  467. };
  468. static const struct udevice_id stm32_spi_ids[] = {
  469. { .compatible = "st,stm32h7-spi", },
  470. { }
  471. };
  472. U_BOOT_DRIVER(stm32_spi) = {
  473. .name = "stm32_spi",
  474. .id = UCLASS_SPI,
  475. .of_match = stm32_spi_ids,
  476. .ops = &stm32_spi_ops,
  477. .priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
  478. .probe = stm32_spi_probe,
  479. .remove = stm32_spi_remove,
  480. };