stm32_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. *
  5. * Michael Kurz, <michi.kurz@gmail.com>
  6. *
  7. * STM32 QSPI driver
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <reset.h>
  12. #include <spi-mem.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/iopoll.h>
  15. #include <linux/ioport.h>
  16. #include <linux/sizes.h>
  17. struct stm32_qspi_regs {
  18. u32 cr; /* 0x00 */
  19. u32 dcr; /* 0x04 */
  20. u32 sr; /* 0x08 */
  21. u32 fcr; /* 0x0C */
  22. u32 dlr; /* 0x10 */
  23. u32 ccr; /* 0x14 */
  24. u32 ar; /* 0x18 */
  25. u32 abr; /* 0x1C */
  26. u32 dr; /* 0x20 */
  27. u32 psmkr; /* 0x24 */
  28. u32 psmar; /* 0x28 */
  29. u32 pir; /* 0x2C */
  30. u32 lptr; /* 0x30 */
  31. };
  32. /*
  33. * QUADSPI control register
  34. */
  35. #define STM32_QSPI_CR_EN BIT(0)
  36. #define STM32_QSPI_CR_ABORT BIT(1)
  37. #define STM32_QSPI_CR_DMAEN BIT(2)
  38. #define STM32_QSPI_CR_TCEN BIT(3)
  39. #define STM32_QSPI_CR_SSHIFT BIT(4)
  40. #define STM32_QSPI_CR_DFM BIT(6)
  41. #define STM32_QSPI_CR_FSEL BIT(7)
  42. #define STM32_QSPI_CR_FTHRES_SHIFT 8
  43. #define STM32_QSPI_CR_TEIE BIT(16)
  44. #define STM32_QSPI_CR_TCIE BIT(17)
  45. #define STM32_QSPI_CR_FTIE BIT(18)
  46. #define STM32_QSPI_CR_SMIE BIT(19)
  47. #define STM32_QSPI_CR_TOIE BIT(20)
  48. #define STM32_QSPI_CR_APMS BIT(22)
  49. #define STM32_QSPI_CR_PMM BIT(23)
  50. #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
  51. #define STM32_QSPI_CR_PRESCALER_SHIFT 24
  52. /*
  53. * QUADSPI device configuration register
  54. */
  55. #define STM32_QSPI_DCR_CKMODE BIT(0)
  56. #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
  57. #define STM32_QSPI_DCR_CSHT_SHIFT 8
  58. #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
  59. #define STM32_QSPI_DCR_FSIZE_SHIFT 16
  60. /*
  61. * QUADSPI status register
  62. */
  63. #define STM32_QSPI_SR_TEF BIT(0)
  64. #define STM32_QSPI_SR_TCF BIT(1)
  65. #define STM32_QSPI_SR_FTF BIT(2)
  66. #define STM32_QSPI_SR_SMF BIT(3)
  67. #define STM32_QSPI_SR_TOF BIT(4)
  68. #define STM32_QSPI_SR_BUSY BIT(5)
  69. /*
  70. * QUADSPI flag clear register
  71. */
  72. #define STM32_QSPI_FCR_CTEF BIT(0)
  73. #define STM32_QSPI_FCR_CTCF BIT(1)
  74. #define STM32_QSPI_FCR_CSMF BIT(3)
  75. #define STM32_QSPI_FCR_CTOF BIT(4)
  76. /*
  77. * QUADSPI communication configuration register
  78. */
  79. #define STM32_QSPI_CCR_DDRM BIT(31)
  80. #define STM32_QSPI_CCR_DHHC BIT(30)
  81. #define STM32_QSPI_CCR_SIOO BIT(28)
  82. #define STM32_QSPI_CCR_FMODE_SHIFT 26
  83. #define STM32_QSPI_CCR_DMODE_SHIFT 24
  84. #define STM32_QSPI_CCR_DCYC_SHIFT 18
  85. #define STM32_QSPI_CCR_ABSIZE_SHIFT 16
  86. #define STM32_QSPI_CCR_ABMODE_SHIFT 14
  87. #define STM32_QSPI_CCR_ADSIZE_SHIFT 12
  88. #define STM32_QSPI_CCR_ADMODE_SHIFT 10
  89. #define STM32_QSPI_CCR_IMODE_SHIFT 8
  90. #define STM32_QSPI_CCR_IND_WRITE 0
  91. #define STM32_QSPI_CCR_IND_READ 1
  92. #define STM32_QSPI_CCR_MEM_MAP 3
  93. #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
  94. #define STM32_QSPI_MAX_CHIP 2
  95. #define STM32_QSPI_FIFO_TIMEOUT_US 30000
  96. #define STM32_QSPI_CMD_TIMEOUT_US 1000000
  97. #define STM32_BUSY_TIMEOUT_US 100000
  98. #define STM32_ABT_TIMEOUT_US 100000
  99. struct stm32_qspi_flash {
  100. u32 cr;
  101. u32 dcr;
  102. bool initialized;
  103. };
  104. struct stm32_qspi_priv {
  105. struct stm32_qspi_regs *regs;
  106. struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
  107. void __iomem *mm_base;
  108. resource_size_t mm_size;
  109. ulong clock_rate;
  110. int cs_used;
  111. };
  112. static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
  113. {
  114. u32 sr;
  115. int ret;
  116. ret = readl_poll_timeout(&priv->regs->sr, sr,
  117. !(sr & STM32_QSPI_SR_BUSY),
  118. STM32_BUSY_TIMEOUT_US);
  119. if (ret)
  120. pr_err("busy timeout (stat:%#x)\n", sr);
  121. return ret;
  122. }
  123. static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
  124. const struct spi_mem_op *op)
  125. {
  126. u32 sr;
  127. int ret;
  128. if (!op->data.nbytes)
  129. return _stm32_qspi_wait_for_not_busy(priv);
  130. ret = readl_poll_timeout(&priv->regs->sr, sr,
  131. sr & STM32_QSPI_SR_TCF,
  132. STM32_QSPI_CMD_TIMEOUT_US);
  133. if (ret) {
  134. pr_err("cmd timeout (stat:%#x)\n", sr);
  135. } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
  136. pr_err("transfer error (stat:%#x)\n", sr);
  137. ret = -EIO;
  138. }
  139. /* clear flags */
  140. writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
  141. return ret;
  142. }
  143. static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
  144. {
  145. *val = readb(addr);
  146. }
  147. static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
  148. {
  149. writeb(*val, addr);
  150. }
  151. static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
  152. const struct spi_mem_op *op)
  153. {
  154. void (*fifo)(u8 *val, void __iomem *addr);
  155. u32 len = op->data.nbytes, sr;
  156. u8 *buf;
  157. int ret;
  158. if (op->data.dir == SPI_MEM_DATA_IN) {
  159. fifo = _stm32_qspi_read_fifo;
  160. buf = op->data.buf.in;
  161. } else {
  162. fifo = _stm32_qspi_write_fifo;
  163. buf = (u8 *)op->data.buf.out;
  164. }
  165. while (len--) {
  166. ret = readl_poll_timeout(&priv->regs->sr, sr,
  167. sr & STM32_QSPI_SR_FTF,
  168. STM32_QSPI_FIFO_TIMEOUT_US);
  169. if (ret) {
  170. pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
  171. return ret;
  172. }
  173. fifo(buf++, &priv->regs->dr);
  174. }
  175. return 0;
  176. }
  177. static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
  178. const struct spi_mem_op *op)
  179. {
  180. memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
  181. op->data.nbytes);
  182. return 0;
  183. }
  184. static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
  185. const struct spi_mem_op *op,
  186. u8 mode)
  187. {
  188. if (!op->data.nbytes)
  189. return 0;
  190. if (mode == STM32_QSPI_CCR_MEM_MAP)
  191. return stm32_qspi_mm(priv, op);
  192. return _stm32_qspi_poll(priv, op);
  193. }
  194. static int _stm32_qspi_get_mode(u8 buswidth)
  195. {
  196. if (buswidth == 4)
  197. return 3;
  198. return buswidth;
  199. }
  200. static int stm32_qspi_exec_op(struct spi_slave *slave,
  201. const struct spi_mem_op *op)
  202. {
  203. struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
  204. u32 cr, ccr, addr_max;
  205. u8 mode = STM32_QSPI_CCR_IND_WRITE;
  206. int timeout, ret;
  207. debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
  208. __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  209. op->dummy.buswidth, op->data.buswidth,
  210. op->addr.val, op->data.nbytes);
  211. ret = _stm32_qspi_wait_for_not_busy(priv);
  212. if (ret)
  213. return ret;
  214. addr_max = op->addr.val + op->data.nbytes + 1;
  215. if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
  216. if (addr_max < priv->mm_size && op->addr.buswidth)
  217. mode = STM32_QSPI_CCR_MEM_MAP;
  218. else
  219. mode = STM32_QSPI_CCR_IND_READ;
  220. }
  221. if (op->data.nbytes)
  222. writel(op->data.nbytes - 1, &priv->regs->dlr);
  223. ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
  224. ccr |= op->cmd.opcode;
  225. ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
  226. << STM32_QSPI_CCR_IMODE_SHIFT);
  227. if (op->addr.nbytes) {
  228. ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
  229. ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
  230. << STM32_QSPI_CCR_ADMODE_SHIFT);
  231. }
  232. if (op->dummy.buswidth && op->dummy.nbytes)
  233. ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
  234. << STM32_QSPI_CCR_DCYC_SHIFT);
  235. if (op->data.nbytes)
  236. ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
  237. << STM32_QSPI_CCR_DMODE_SHIFT);
  238. writel(ccr, &priv->regs->ccr);
  239. if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
  240. writel(op->addr.val, &priv->regs->ar);
  241. ret = _stm32_qspi_tx(priv, op, mode);
  242. /*
  243. * Abort in:
  244. * -error case
  245. * -read memory map: prefetching must be stopped if we read the last
  246. * byte of device (device size - fifo size). like device size is not
  247. * knows, the prefetching is always stop.
  248. */
  249. if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
  250. goto abort;
  251. /* Wait end of tx in indirect mode */
  252. ret = _stm32_qspi_wait_cmd(priv, op);
  253. if (ret)
  254. goto abort;
  255. return 0;
  256. abort:
  257. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
  258. /* Wait clear of abort bit by hw */
  259. timeout = readl_poll_timeout(&priv->regs->cr, cr,
  260. !(cr & STM32_QSPI_CR_ABORT),
  261. STM32_ABT_TIMEOUT_US);
  262. writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
  263. if (ret || timeout)
  264. pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
  265. return ret;
  266. }
  267. static int stm32_qspi_probe(struct udevice *bus)
  268. {
  269. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  270. struct resource res;
  271. struct clk clk;
  272. struct reset_ctl reset_ctl;
  273. int ret;
  274. ret = dev_read_resource_byname(bus, "qspi", &res);
  275. if (ret) {
  276. dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
  277. return ret;
  278. }
  279. priv->regs = (struct stm32_qspi_regs *)res.start;
  280. ret = dev_read_resource_byname(bus, "qspi_mm", &res);
  281. if (ret) {
  282. dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
  283. return ret;
  284. }
  285. priv->mm_base = (void __iomem *)res.start;
  286. priv->mm_size = resource_size(&res);
  287. if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
  288. return -EINVAL;
  289. debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
  290. __func__, priv->regs, priv->mm_base, priv->mm_size);
  291. ret = clk_get_by_index(bus, 0, &clk);
  292. if (ret < 0)
  293. return ret;
  294. ret = clk_enable(&clk);
  295. if (ret) {
  296. dev_err(bus, "failed to enable clock\n");
  297. return ret;
  298. }
  299. priv->clock_rate = clk_get_rate(&clk);
  300. if (!priv->clock_rate) {
  301. clk_disable(&clk);
  302. return -EINVAL;
  303. }
  304. ret = reset_get_by_index(bus, 0, &reset_ctl);
  305. if (ret) {
  306. if (ret != -ENOENT) {
  307. dev_err(bus, "failed to get reset\n");
  308. clk_disable(&clk);
  309. return ret;
  310. }
  311. } else {
  312. /* Reset QSPI controller */
  313. reset_assert(&reset_ctl);
  314. udelay(2);
  315. reset_deassert(&reset_ctl);
  316. }
  317. priv->cs_used = -1;
  318. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
  319. /* Set dcr fsize to max address */
  320. setbits_le32(&priv->regs->dcr,
  321. STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
  322. return 0;
  323. }
  324. static int stm32_qspi_claim_bus(struct udevice *dev)
  325. {
  326. struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
  327. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  328. int slave_cs = slave_plat->cs;
  329. if (slave_cs >= STM32_QSPI_MAX_CHIP)
  330. return -ENODEV;
  331. if (priv->cs_used != slave_cs) {
  332. struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
  333. priv->cs_used = slave_cs;
  334. if (flash->initialized) {
  335. /* Set the configuration: speed + cs */
  336. writel(flash->cr, &priv->regs->cr);
  337. writel(flash->dcr, &priv->regs->dcr);
  338. } else {
  339. /* Set chip select */
  340. clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
  341. priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
  342. /* Save the configuration: speed + cs */
  343. flash->cr = readl(&priv->regs->cr);
  344. flash->dcr = readl(&priv->regs->dcr);
  345. flash->initialized = true;
  346. }
  347. }
  348. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  349. return 0;
  350. }
  351. static int stm32_qspi_release_bus(struct udevice *dev)
  352. {
  353. struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
  354. clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  355. return 0;
  356. }
  357. static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
  358. {
  359. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  360. u32 qspi_clk = priv->clock_rate;
  361. u32 prescaler = 255;
  362. u32 csht;
  363. int ret;
  364. if (speed > 0) {
  365. prescaler = 0;
  366. if (qspi_clk) {
  367. prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
  368. if (prescaler > 255)
  369. prescaler = 255;
  370. }
  371. }
  372. csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
  373. csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
  374. ret = _stm32_qspi_wait_for_not_busy(priv);
  375. if (ret)
  376. return ret;
  377. clrsetbits_le32(&priv->regs->cr,
  378. STM32_QSPI_CR_PRESCALER_MASK <<
  379. STM32_QSPI_CR_PRESCALER_SHIFT,
  380. prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
  381. clrsetbits_le32(&priv->regs->dcr,
  382. STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
  383. csht << STM32_QSPI_DCR_CSHT_SHIFT);
  384. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
  385. (qspi_clk / (prescaler + 1)));
  386. return 0;
  387. }
  388. static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
  389. {
  390. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  391. int ret;
  392. ret = _stm32_qspi_wait_for_not_busy(priv);
  393. if (ret)
  394. return ret;
  395. if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
  396. setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  397. else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
  398. clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  399. else
  400. return -ENODEV;
  401. if (mode & SPI_CS_HIGH)
  402. return -ENODEV;
  403. debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
  404. if (mode & SPI_RX_QUAD)
  405. debug("quad, tx: ");
  406. else if (mode & SPI_RX_DUAL)
  407. debug("dual, tx: ");
  408. else
  409. debug("single, tx: ");
  410. if (mode & SPI_TX_QUAD)
  411. debug("quad\n");
  412. else if (mode & SPI_TX_DUAL)
  413. debug("dual\n");
  414. else
  415. debug("single\n");
  416. return 0;
  417. }
  418. static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
  419. .exec_op = stm32_qspi_exec_op,
  420. };
  421. static const struct dm_spi_ops stm32_qspi_ops = {
  422. .claim_bus = stm32_qspi_claim_bus,
  423. .release_bus = stm32_qspi_release_bus,
  424. .set_speed = stm32_qspi_set_speed,
  425. .set_mode = stm32_qspi_set_mode,
  426. .mem_ops = &stm32_qspi_mem_ops,
  427. };
  428. static const struct udevice_id stm32_qspi_ids[] = {
  429. { .compatible = "st,stm32f469-qspi" },
  430. { }
  431. };
  432. U_BOOT_DRIVER(stm32_qspi) = {
  433. .name = "stm32_qspi",
  434. .id = UCLASS_SPI,
  435. .of_match = stm32_qspi_ids,
  436. .ops = &stm32_qspi_ops,
  437. .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
  438. .probe = stm32_qspi_probe,
  439. };