sh_qspi.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH QSPI (Quad SPI) driver
  4. *
  5. * Copyright (C) 2013 Renesas Electronics Corporation
  6. * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  7. */
  8. #include <common.h>
  9. #include <console.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <wait_bit.h>
  13. #include <asm/arch/rmobile.h>
  14. #include <asm/io.h>
  15. /* SH QSPI register bit masks <REG>_<BIT> */
  16. #define SPCR_MSTR 0x08
  17. #define SPCR_SPE 0x40
  18. #define SPSR_SPRFF 0x80
  19. #define SPSR_SPTEF 0x20
  20. #define SPPCR_IO3FV 0x04
  21. #define SPPCR_IO2FV 0x02
  22. #define SPPCR_IO1FV 0x01
  23. #define SPBDCR_RXBC0 BIT(0)
  24. #define SPCMD_SCKDEN BIT(15)
  25. #define SPCMD_SLNDEN BIT(14)
  26. #define SPCMD_SPNDEN BIT(13)
  27. #define SPCMD_SSLKP BIT(7)
  28. #define SPCMD_BRDV0 BIT(2)
  29. #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
  30. SPCMD_SPNDEN | SPCMD_SSLKP | \
  31. SPCMD_BRDV0
  32. #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
  33. SPCMD_BRDV0
  34. #define SPBFCR_TXRST BIT(7)
  35. #define SPBFCR_RXRST BIT(6)
  36. #define SPBFCR_TXTRG 0x30
  37. #define SPBFCR_RXTRG 0x07
  38. /* SH QSPI register set */
  39. struct sh_qspi_regs {
  40. u8 spcr;
  41. u8 sslp;
  42. u8 sppcr;
  43. u8 spsr;
  44. u32 spdr;
  45. u8 spscr;
  46. u8 spssr;
  47. u8 spbr;
  48. u8 spdcr;
  49. u8 spckd;
  50. u8 sslnd;
  51. u8 spnd;
  52. u8 dummy0;
  53. u16 spcmd0;
  54. u16 spcmd1;
  55. u16 spcmd2;
  56. u16 spcmd3;
  57. u8 spbfcr;
  58. u8 dummy1;
  59. u16 spbdcr;
  60. u32 spbmul0;
  61. u32 spbmul1;
  62. u32 spbmul2;
  63. u32 spbmul3;
  64. };
  65. struct sh_qspi_slave {
  66. #ifndef CONFIG_DM_SPI
  67. struct spi_slave slave;
  68. #endif
  69. struct sh_qspi_regs *regs;
  70. };
  71. static void sh_qspi_init(struct sh_qspi_slave *ss)
  72. {
  73. /* QSPI initialize */
  74. /* Set master mode only */
  75. writeb(SPCR_MSTR, &ss->regs->spcr);
  76. /* Set SSL signal level */
  77. writeb(0x00, &ss->regs->sslp);
  78. /* Set MOSI signal value when transfer is in idle state */
  79. writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
  80. /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
  81. writeb(0x01, &ss->regs->spbr);
  82. /* Disable Dummy Data Transmission */
  83. writeb(0x00, &ss->regs->spdcr);
  84. /* Set clock delay value */
  85. writeb(0x00, &ss->regs->spckd);
  86. /* Set SSL negation delay value */
  87. writeb(0x00, &ss->regs->sslnd);
  88. /* Set next-access delay value */
  89. writeb(0x00, &ss->regs->spnd);
  90. /* Set equence command */
  91. writew(SPCMD_INIT2, &ss->regs->spcmd0);
  92. /* Reset transfer and receive Buffer */
  93. setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  94. /* Clear transfer and receive Buffer control bit */
  95. clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  96. /* Set equence control method. Use equence0 only */
  97. writeb(0x00, &ss->regs->spscr);
  98. /* Enable SPI function */
  99. setbits_8(&ss->regs->spcr, SPCR_SPE);
  100. }
  101. static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
  102. {
  103. /* Set master mode only */
  104. writeb(SPCR_MSTR, &ss->regs->spcr);
  105. /* Set command */
  106. writew(SPCMD_INIT1, &ss->regs->spcmd0);
  107. /* Reset transfer and receive Buffer */
  108. setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  109. /* Clear transfer and receive Buffer control bit */
  110. clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  111. /* Set equence control method. Use equence0 only */
  112. writeb(0x00, &ss->regs->spscr);
  113. /* Enable SPI function */
  114. setbits_8(&ss->regs->spcr, SPCR_SPE);
  115. }
  116. static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
  117. {
  118. /* Disable SPI Function */
  119. clrbits_8(&ss->regs->spcr, SPCR_SPE);
  120. }
  121. static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
  122. const void *dout, void *din, unsigned long flags)
  123. {
  124. u32 nbyte, chunk;
  125. int i, ret = 0;
  126. u8 dtdata = 0, drdata;
  127. u8 *tdata = &dtdata, *rdata = &drdata;
  128. u32 *spbmul0 = &ss->regs->spbmul0;
  129. if (dout == NULL && din == NULL) {
  130. if (flags & SPI_XFER_END)
  131. sh_qspi_cs_deactivate(ss);
  132. return 0;
  133. }
  134. if (bitlen % 8) {
  135. printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
  136. return 1;
  137. }
  138. nbyte = bitlen / 8;
  139. if (flags & SPI_XFER_BEGIN) {
  140. sh_qspi_cs_activate(ss);
  141. /* Set 1048576 byte */
  142. writel(0x100000, spbmul0);
  143. }
  144. if (flags & SPI_XFER_END)
  145. writel(nbyte, spbmul0);
  146. if (dout != NULL)
  147. tdata = (u8 *)dout;
  148. if (din != NULL)
  149. rdata = din;
  150. while (nbyte > 0) {
  151. /*
  152. * Check if there is 32 Byte chunk and if there is, transfer
  153. * it in one burst, otherwise transfer on byte-by-byte basis.
  154. */
  155. chunk = (nbyte >= 32) ? 32 : 1;
  156. clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
  157. chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
  158. ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
  159. true, 1000, true);
  160. if (ret)
  161. return ret;
  162. for (i = 0; i < chunk; i++) {
  163. writeb(*tdata, &ss->regs->spdr);
  164. if (dout != NULL)
  165. tdata++;
  166. }
  167. ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
  168. true, 1000, true);
  169. if (ret)
  170. return ret;
  171. for (i = 0; i < chunk; i++) {
  172. *rdata = readb(&ss->regs->spdr);
  173. if (din != NULL)
  174. rdata++;
  175. }
  176. nbyte -= chunk;
  177. }
  178. if (flags & SPI_XFER_END)
  179. sh_qspi_cs_deactivate(ss);
  180. return ret;
  181. }
  182. #ifndef CONFIG_DM_SPI
  183. static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
  184. {
  185. return container_of(slave, struct sh_qspi_slave, slave);
  186. }
  187. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  188. {
  189. return 1;
  190. }
  191. void spi_cs_activate(struct spi_slave *slave)
  192. {
  193. struct sh_qspi_slave *ss = to_sh_qspi(slave);
  194. sh_qspi_cs_activate(ss);
  195. }
  196. void spi_cs_deactivate(struct spi_slave *slave)
  197. {
  198. struct sh_qspi_slave *ss = to_sh_qspi(slave);
  199. sh_qspi_cs_deactivate(ss);
  200. }
  201. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  202. unsigned int max_hz, unsigned int mode)
  203. {
  204. struct sh_qspi_slave *ss;
  205. if (!spi_cs_is_valid(bus, cs))
  206. return NULL;
  207. ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
  208. if (!ss) {
  209. printf("SPI_error: Fail to allocate sh_qspi_slave\n");
  210. return NULL;
  211. }
  212. ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
  213. /* Init SH QSPI */
  214. sh_qspi_init(ss);
  215. return &ss->slave;
  216. }
  217. void spi_free_slave(struct spi_slave *slave)
  218. {
  219. struct sh_qspi_slave *spi = to_sh_qspi(slave);
  220. free(spi);
  221. }
  222. int spi_claim_bus(struct spi_slave *slave)
  223. {
  224. return 0;
  225. }
  226. void spi_release_bus(struct spi_slave *slave)
  227. {
  228. }
  229. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  230. const void *dout, void *din, unsigned long flags)
  231. {
  232. struct sh_qspi_slave *ss = to_sh_qspi(slave);
  233. return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
  234. }
  235. #else
  236. #include <dm.h>
  237. static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  238. const void *dout, void *din, unsigned long flags)
  239. {
  240. struct udevice *bus = dev->parent;
  241. struct sh_qspi_slave *ss = dev_get_platdata(bus);
  242. return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
  243. }
  244. static int sh_qspi_set_speed(struct udevice *dev, uint speed)
  245. {
  246. /* This is a SPI NOR controller, do nothing. */
  247. return 0;
  248. }
  249. static int sh_qspi_set_mode(struct udevice *dev, uint mode)
  250. {
  251. /* This is a SPI NOR controller, do nothing. */
  252. return 0;
  253. }
  254. static int sh_qspi_probe(struct udevice *dev)
  255. {
  256. struct sh_qspi_slave *ss = dev_get_platdata(dev);
  257. sh_qspi_init(ss);
  258. return 0;
  259. }
  260. static int sh_qspi_ofdata_to_platdata(struct udevice *dev)
  261. {
  262. struct sh_qspi_slave *plat = dev_get_platdata(dev);
  263. plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
  264. return 0;
  265. }
  266. static const struct dm_spi_ops sh_qspi_ops = {
  267. .xfer = sh_qspi_xfer,
  268. .set_speed = sh_qspi_set_speed,
  269. .set_mode = sh_qspi_set_mode,
  270. };
  271. static const struct udevice_id sh_qspi_ids[] = {
  272. { .compatible = "renesas,qspi" },
  273. { }
  274. };
  275. U_BOOT_DRIVER(sh_qspi) = {
  276. .name = "sh_qspi",
  277. .id = UCLASS_SPI,
  278. .of_match = sh_qspi_ids,
  279. .ops = &sh_qspi_ops,
  280. .ofdata_to_platdata = sh_qspi_ofdata_to_platdata,
  281. .platdata_auto_alloc_size = sizeof(struct sh_qspi_slave),
  282. .probe = sh_qspi_probe,
  283. };
  284. #endif