pic32_spi.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Microchip PIC32 SPI controller driver.
  4. *
  5. * Copyright (c) 2015, Microchip Technology Inc.
  6. * Purna Chandra Mandal <purna.mandal@microchip.com>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <linux/compat.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <asm/types.h>
  15. #include <asm/io.h>
  16. #include <asm/gpio.h>
  17. #include <dt-bindings/clock/microchip,clock.h>
  18. #include <mach/pic32.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* PIC32 SPI controller registers */
  21. struct pic32_reg_spi {
  22. struct pic32_reg_atomic ctrl;
  23. struct pic32_reg_atomic status;
  24. struct pic32_reg_atomic buf;
  25. struct pic32_reg_atomic baud;
  26. struct pic32_reg_atomic ctrl2;
  27. };
  28. /* Bit fields in SPI Control Register */
  29. #define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
  30. #define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
  31. #define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
  32. #define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
  33. #define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
  34. #define PIC32_SPI_CTRL_BPW_8 0x0
  35. #define PIC32_SPI_CTRL_BPW_16 0x1
  36. #define PIC32_SPI_CTRL_BPW_32 0x2
  37. #define PIC32_SPI_CTRL_BPW_SHIFT 10
  38. #define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
  39. #define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
  40. #define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
  41. #define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
  42. #define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
  43. /* Bit fields in SPI Status Register */
  44. #define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
  45. #define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
  46. #define PIC32_SPI_STAT_TF_LVL_SHIFT 16
  47. #define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
  48. #define PIC32_SPI_STAT_RF_LVL_SHIFT 24
  49. /* Bit fields in SPI Baud Register */
  50. #define PIC32_SPI_BAUD_MASK 0x1ff
  51. struct pic32_spi_priv {
  52. struct pic32_reg_spi *regs;
  53. u32 fifo_depth; /* FIFO depth in bytes */
  54. u32 fifo_n_word; /* FIFO depth in words */
  55. struct gpio_desc cs_gpio;
  56. /* Current SPI slave specific */
  57. ulong clk_rate;
  58. u32 speed_hz; /* spi-clk rate */
  59. int mode;
  60. /* Current message/transfer state */
  61. const void *tx;
  62. const void *tx_end;
  63. const void *rx;
  64. const void *rx_end;
  65. u32 len;
  66. /* SPI FiFo accessor */
  67. void (*rx_fifo)(struct pic32_spi_priv *);
  68. void (*tx_fifo)(struct pic32_spi_priv *);
  69. };
  70. static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
  71. {
  72. writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
  73. }
  74. static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
  75. {
  76. writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
  77. }
  78. static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
  79. {
  80. u32 sr = readl(&priv->regs->status.raw);
  81. return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
  82. }
  83. static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
  84. {
  85. u32 sr = readl(&priv->regs->status.raw);
  86. return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
  87. }
  88. /* Return the max entries we can fill into tx fifo */
  89. static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
  90. {
  91. u32 tx_left, tx_room, rxtx_gap;
  92. tx_left = (priv->tx_end - priv->tx) / n_bytes;
  93. tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
  94. rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
  95. rxtx_gap /= n_bytes;
  96. return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
  97. }
  98. /* Return the max entries we should read out of rx fifo */
  99. static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
  100. {
  101. u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
  102. return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
  103. }
  104. #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
  105. static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
  106. { \
  107. __type val; \
  108. u32 mx = pic32_rx_max(priv, sizeof(__type)); \
  109. \
  110. for (; mx; mx--) { \
  111. val = read##__bwl(&priv->regs->buf.raw); \
  112. if (priv->rx_end - priv->len) \
  113. *(__type *)(priv->rx) = val; \
  114. priv->rx += sizeof(__type); \
  115. } \
  116. } \
  117. \
  118. static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
  119. { \
  120. __type val; \
  121. u32 mx = pic32_tx_max(priv, sizeof(__type)); \
  122. \
  123. for (; mx ; mx--) { \
  124. val = (__type) ~0U; \
  125. if (priv->tx_end - priv->len) \
  126. val = *(__type *)(priv->tx); \
  127. write##__bwl(val, &priv->regs->buf.raw); \
  128. priv->tx += sizeof(__type); \
  129. } \
  130. }
  131. BUILD_SPI_FIFO_RW(byte, u8, b);
  132. BUILD_SPI_FIFO_RW(word, u16, w);
  133. BUILD_SPI_FIFO_RW(dword, u32, l);
  134. static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
  135. unsigned int wordlen)
  136. {
  137. u32 bits_per_word;
  138. u32 val;
  139. switch (wordlen) {
  140. case 8:
  141. priv->rx_fifo = pic32_spi_rx_byte;
  142. priv->tx_fifo = pic32_spi_tx_byte;
  143. bits_per_word = PIC32_SPI_CTRL_BPW_8;
  144. break;
  145. case 16:
  146. priv->rx_fifo = pic32_spi_rx_word;
  147. priv->tx_fifo = pic32_spi_tx_word;
  148. bits_per_word = PIC32_SPI_CTRL_BPW_16;
  149. break;
  150. case 32:
  151. priv->rx_fifo = pic32_spi_rx_dword;
  152. priv->tx_fifo = pic32_spi_tx_dword;
  153. bits_per_word = PIC32_SPI_CTRL_BPW_32;
  154. break;
  155. default:
  156. printf("pic32-spi: unsupported wordlen\n");
  157. return -EINVAL;
  158. }
  159. /* set bits-per-word */
  160. val = readl(&priv->regs->ctrl.raw);
  161. val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
  162. val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
  163. writel(val, &priv->regs->ctrl.raw);
  164. /* calculate maximum number of words fifo can hold */
  165. priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
  166. return 0;
  167. }
  168. static int pic32_spi_claim_bus(struct udevice *slave)
  169. {
  170. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  171. /* enable chip */
  172. pic32_spi_enable(priv);
  173. return 0;
  174. }
  175. static int pic32_spi_release_bus(struct udevice *slave)
  176. {
  177. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  178. /* disable chip */
  179. pic32_spi_disable(priv);
  180. return 0;
  181. }
  182. static void spi_cs_activate(struct pic32_spi_priv *priv)
  183. {
  184. if (!dm_gpio_is_valid(&priv->cs_gpio))
  185. return;
  186. dm_gpio_set_value(&priv->cs_gpio, 1);
  187. }
  188. static void spi_cs_deactivate(struct pic32_spi_priv *priv)
  189. {
  190. if (!dm_gpio_is_valid(&priv->cs_gpio))
  191. return;
  192. dm_gpio_set_value(&priv->cs_gpio, 0);
  193. }
  194. static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
  195. const void *tx_buf, void *rx_buf,
  196. unsigned long flags)
  197. {
  198. struct dm_spi_slave_platdata *slave_plat;
  199. struct udevice *bus = slave->parent;
  200. struct pic32_spi_priv *priv;
  201. int len = bitlen / 8;
  202. int ret = 0;
  203. ulong tbase;
  204. priv = dev_get_priv(bus);
  205. slave_plat = dev_get_parent_platdata(slave);
  206. debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
  207. bus->seq, slave_plat->cs, flags);
  208. debug("msg tx %p, rx %p submitted of %d byte(s)\n",
  209. tx_buf, rx_buf, len);
  210. /* assert cs */
  211. if (flags & SPI_XFER_BEGIN)
  212. spi_cs_activate(priv);
  213. /* set current transfer information */
  214. priv->tx = tx_buf;
  215. priv->rx = rx_buf;
  216. priv->tx_end = priv->tx + len;
  217. priv->rx_end = priv->rx + len;
  218. priv->len = len;
  219. /* transact by polling */
  220. tbase = get_timer(0);
  221. for (;;) {
  222. priv->tx_fifo(priv);
  223. priv->rx_fifo(priv);
  224. /* received sufficient data */
  225. if (priv->rx >= priv->rx_end) {
  226. ret = 0;
  227. break;
  228. }
  229. if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
  230. printf("pic32_spi: error, xfer timedout.\n");
  231. flags |= SPI_XFER_END;
  232. ret = -ETIMEDOUT;
  233. break;
  234. }
  235. }
  236. /* deassert cs */
  237. if (flags & SPI_XFER_END)
  238. spi_cs_deactivate(priv);
  239. return ret;
  240. }
  241. static int pic32_spi_set_speed(struct udevice *bus, uint speed)
  242. {
  243. struct pic32_spi_priv *priv = dev_get_priv(bus);
  244. u32 div;
  245. debug("%s: %s, speed %u\n", __func__, bus->name, speed);
  246. /* div = [clk_in / (2 * spi_clk)] - 1 */
  247. div = (priv->clk_rate / 2 / speed) - 1;
  248. div &= PIC32_SPI_BAUD_MASK;
  249. writel(div, &priv->regs->baud.raw);
  250. priv->speed_hz = speed;
  251. return 0;
  252. }
  253. static int pic32_spi_set_mode(struct udevice *bus, uint mode)
  254. {
  255. struct pic32_spi_priv *priv = dev_get_priv(bus);
  256. u32 val;
  257. debug("%s: %s, mode %d\n", __func__, bus->name, mode);
  258. /* set spi-clk mode */
  259. val = readl(&priv->regs->ctrl.raw);
  260. /* HIGH when idle */
  261. if (mode & SPI_CPOL)
  262. val |= PIC32_SPI_CTRL_CKP;
  263. else
  264. val &= ~PIC32_SPI_CTRL_CKP;
  265. /* TX at idle-to-active clk transition */
  266. if (mode & SPI_CPHA)
  267. val &= ~PIC32_SPI_CTRL_CKE;
  268. else
  269. val |= PIC32_SPI_CTRL_CKE;
  270. /* RX at end of tx */
  271. val |= PIC32_SPI_CTRL_SMP;
  272. writel(val, &priv->regs->ctrl.raw);
  273. priv->mode = mode;
  274. return 0;
  275. }
  276. static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
  277. {
  278. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  279. return pic32_spi_set_word_size(priv, wordlen);
  280. }
  281. static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
  282. {
  283. u32 val;
  284. /* disable module */
  285. pic32_spi_disable(priv);
  286. val = readl(&priv->regs->ctrl);
  287. /* enable enhanced fifo of 128bit deep */
  288. val |= PIC32_SPI_CTRL_ENHBUF;
  289. priv->fifo_depth = 16;
  290. /* disable framing mode */
  291. val &= ~PIC32_SPI_CTRL_FRMEN;
  292. /* enable master mode */
  293. val |= PIC32_SPI_CTRL_MSTEN;
  294. /* select clk source */
  295. val &= ~PIC32_SPI_CTRL_MCLKSEL;
  296. /* set manual /CS mode */
  297. val &= ~PIC32_SPI_CTRL_MSSEN;
  298. writel(val, &priv->regs->ctrl);
  299. /* clear rx overflow indicator */
  300. writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
  301. }
  302. static int pic32_spi_probe(struct udevice *bus)
  303. {
  304. struct pic32_spi_priv *priv = dev_get_priv(bus);
  305. struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
  306. int node = dev_of_offset(bus);
  307. struct udevice *clkdev;
  308. fdt_addr_t addr;
  309. fdt_size_t size;
  310. int ret;
  311. debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
  312. addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
  313. if (addr == FDT_ADDR_T_NONE)
  314. return -EINVAL;
  315. priv->regs = ioremap(addr, size);
  316. if (!priv->regs)
  317. return -EINVAL;
  318. dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
  319. 250000000);
  320. /* get clock rate */
  321. ret = clk_get_by_index(bus, 0, &clkdev);
  322. if (ret < 0) {
  323. printf("pic32-spi: error, clk not found\n");
  324. return ret;
  325. }
  326. priv->clk_rate = clk_get_periph_rate(clkdev, ret);
  327. /* initialize HW */
  328. pic32_spi_hw_init(priv);
  329. /* set word len */
  330. pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
  331. /* PIC32 SPI controller can automatically drive /CS during transfer
  332. * depending on fifo fill-level. /CS will stay asserted as long as
  333. * TX fifo is non-empty, else will be deasserted confirming completion
  334. * of the ongoing transfer. To avoid this sort of error we will drive
  335. * /CS manually by toggling cs-gpio pins.
  336. */
  337. ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
  338. &priv->cs_gpio, GPIOD_IS_OUT);
  339. if (ret) {
  340. printf("pic32-spi: error, cs-gpios not found\n");
  341. return ret;
  342. }
  343. return 0;
  344. }
  345. static const struct dm_spi_ops pic32_spi_ops = {
  346. .claim_bus = pic32_spi_claim_bus,
  347. .release_bus = pic32_spi_release_bus,
  348. .xfer = pic32_spi_xfer,
  349. .set_speed = pic32_spi_set_speed,
  350. .set_mode = pic32_spi_set_mode,
  351. .set_wordlen = pic32_spi_set_wordlen,
  352. };
  353. static const struct udevice_id pic32_spi_ids[] = {
  354. { .compatible = "microchip,pic32mzda-spi" },
  355. { }
  356. };
  357. U_BOOT_DRIVER(pic32_spi) = {
  358. .name = "pic32_spi",
  359. .id = UCLASS_SPI,
  360. .of_match = pic32_spi_ids,
  361. .ops = &pic32_spi_ops,
  362. .priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
  363. .probe = pic32_spi_probe,
  364. };