omap3_spi.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
  4. * Christophe Ricard <christophe.ricard@gmail.com>
  5. *
  6. * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
  7. *
  8. * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
  9. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  10. *
  11. * Copyright (C) 2007 Atmel Corporation
  12. *
  13. * Parts taken from linux/drivers/spi/omap2_mcspi.c
  14. * Copyright (C) 2005, 2006 Nokia Corporation
  15. *
  16. * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <spi.h>
  21. #include <malloc.h>
  22. #include <asm/io.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
  25. #define OMAP3_MCSPI1_BASE 0x48030100
  26. #define OMAP3_MCSPI2_BASE 0x481A0100
  27. #else
  28. #define OMAP3_MCSPI1_BASE 0x48098000
  29. #define OMAP3_MCSPI2_BASE 0x4809A000
  30. #define OMAP3_MCSPI3_BASE 0x480B8000
  31. #define OMAP3_MCSPI4_BASE 0x480BA000
  32. #endif
  33. #define OMAP4_MCSPI_REG_OFFSET 0x100
  34. struct omap2_mcspi_platform_config {
  35. unsigned int regs_offset;
  36. };
  37. /* per-register bitmasks */
  38. #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
  39. #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
  40. #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
  41. #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
  42. #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
  43. #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
  44. #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
  45. #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
  46. #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
  47. #define OMAP3_MCSPI_CHCONF_POL BIT(1)
  48. #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
  49. #define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
  50. #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
  51. #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
  52. #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
  53. #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
  54. #define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
  55. #define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
  56. #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
  57. #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
  58. #define OMAP3_MCSPI_CHCONF_IS BIT(18)
  59. #define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
  60. #define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
  61. #define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
  62. #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
  63. #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
  64. #define OMAP3_MCSPI_CHCTRL_EN BIT(0)
  65. #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
  66. #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
  67. #define MCSPI_PINDIR_D0_IN_D1_OUT 0
  68. #define MCSPI_PINDIR_D0_OUT_D1_IN 1
  69. #define OMAP3_MCSPI_MAX_FREQ 48000000
  70. #define SPI_WAIT_TIMEOUT 10
  71. /* OMAP3 McSPI registers */
  72. struct mcspi_channel {
  73. unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
  74. unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
  75. unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
  76. unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
  77. unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
  78. };
  79. struct mcspi {
  80. unsigned char res1[0x10];
  81. unsigned int sysconfig; /* 0x10 */
  82. unsigned int sysstatus; /* 0x14 */
  83. unsigned int irqstatus; /* 0x18 */
  84. unsigned int irqenable; /* 0x1C */
  85. unsigned int wakeupenable; /* 0x20 */
  86. unsigned int syst; /* 0x24 */
  87. unsigned int modulctrl; /* 0x28 */
  88. struct mcspi_channel channel[4];
  89. /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
  90. /* channel1: 0x40 - 0x50, bus 0 & 1 */
  91. /* channel2: 0x54 - 0x64, bus 0 & 1 */
  92. /* channel3: 0x68 - 0x78, bus 0 */
  93. };
  94. struct omap3_spi_priv {
  95. #ifndef CONFIG_DM_SPI
  96. struct spi_slave slave;
  97. #endif
  98. struct mcspi *regs;
  99. unsigned int cs;
  100. unsigned int freq;
  101. unsigned int mode;
  102. unsigned int wordlen;
  103. unsigned int pin_dir:1;
  104. };
  105. static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
  106. {
  107. writel(val, &priv->regs->channel[priv->cs].chconf);
  108. /* Flash post writes to make immediate effect */
  109. readl(&priv->regs->channel[priv->cs].chconf);
  110. }
  111. static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
  112. {
  113. writel(enable, &priv->regs->channel[priv->cs].chctrl);
  114. /* Flash post writes to make immediate effect */
  115. readl(&priv->regs->channel[priv->cs].chctrl);
  116. }
  117. static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
  118. const void *txp, unsigned long flags)
  119. {
  120. ulong start;
  121. int i, chconf;
  122. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  123. /* Enable the channel */
  124. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  125. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  126. chconf |= (priv->wordlen - 1) << 7;
  127. chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
  128. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  129. omap3_spi_write_chconf(priv, chconf);
  130. for (i = 0; i < len; i++) {
  131. /* wait till TX register is empty (TXS == 1) */
  132. start = get_timer(0);
  133. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  134. OMAP3_MCSPI_CHSTAT_TXS)) {
  135. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  136. printf("SPI TXS timed out, status=0x%08x\n",
  137. readl(&priv->regs->channel[priv->cs].chstat));
  138. return -1;
  139. }
  140. }
  141. /* Write the data */
  142. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  143. if (priv->wordlen > 16)
  144. writel(((u32 *)txp)[i], tx);
  145. else if (priv->wordlen > 8)
  146. writel(((u16 *)txp)[i], tx);
  147. else
  148. writel(((u8 *)txp)[i], tx);
  149. }
  150. /* wait to finish of transfer */
  151. while ((readl(&priv->regs->channel[priv->cs].chstat) &
  152. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
  153. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
  154. ;
  155. /* Disable the channel otherwise the next immediate RX will get affected */
  156. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  157. if (flags & SPI_XFER_END) {
  158. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  159. omap3_spi_write_chconf(priv, chconf);
  160. }
  161. return 0;
  162. }
  163. static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
  164. void *rxp, unsigned long flags)
  165. {
  166. int i, chconf;
  167. ulong start;
  168. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  169. /* Enable the channel */
  170. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  171. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  172. chconf |= (priv->wordlen - 1) << 7;
  173. chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
  174. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  175. omap3_spi_write_chconf(priv, chconf);
  176. writel(0, &priv->regs->channel[priv->cs].tx);
  177. for (i = 0; i < len; i++) {
  178. start = get_timer(0);
  179. /* Wait till RX register contains data (RXS == 1) */
  180. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  181. OMAP3_MCSPI_CHSTAT_RXS)) {
  182. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  183. printf("SPI RXS timed out, status=0x%08x\n",
  184. readl(&priv->regs->channel[priv->cs].chstat));
  185. return -1;
  186. }
  187. }
  188. /* Disable the channel to prevent furher receiving */
  189. if (i == (len - 1))
  190. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  191. /* Read the data */
  192. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  193. if (priv->wordlen > 16)
  194. ((u32 *)rxp)[i] = readl(rx);
  195. else if (priv->wordlen > 8)
  196. ((u16 *)rxp)[i] = (u16)readl(rx);
  197. else
  198. ((u8 *)rxp)[i] = (u8)readl(rx);
  199. }
  200. if (flags & SPI_XFER_END) {
  201. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  202. omap3_spi_write_chconf(priv, chconf);
  203. }
  204. return 0;
  205. }
  206. /*McSPI Transmit Receive Mode*/
  207. static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
  208. const void *txp, void *rxp, unsigned long flags)
  209. {
  210. ulong start;
  211. int chconf, i = 0;
  212. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  213. /*Enable SPI channel*/
  214. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  215. /*set TRANSMIT-RECEIVE Mode*/
  216. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  217. chconf |= (priv->wordlen - 1) << 7;
  218. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  219. omap3_spi_write_chconf(priv, chconf);
  220. /*Shift in and out 1 byte at time*/
  221. for (i=0; i < len; i++){
  222. /* Write: wait for TX empty (TXS == 1)*/
  223. start = get_timer(0);
  224. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  225. OMAP3_MCSPI_CHSTAT_TXS)) {
  226. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  227. printf("SPI TXS timed out, status=0x%08x\n",
  228. readl(&priv->regs->channel[priv->cs].chstat));
  229. return -1;
  230. }
  231. }
  232. /* Write the data */
  233. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  234. if (priv->wordlen > 16)
  235. writel(((u32 *)txp)[i], tx);
  236. else if (priv->wordlen > 8)
  237. writel(((u16 *)txp)[i], tx);
  238. else
  239. writel(((u8 *)txp)[i], tx);
  240. /*Read: wait for RX containing data (RXS == 1)*/
  241. start = get_timer(0);
  242. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  243. OMAP3_MCSPI_CHSTAT_RXS)) {
  244. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  245. printf("SPI RXS timed out, status=0x%08x\n",
  246. readl(&priv->regs->channel[priv->cs].chstat));
  247. return -1;
  248. }
  249. }
  250. /* Read the data */
  251. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  252. if (priv->wordlen > 16)
  253. ((u32 *)rxp)[i] = readl(rx);
  254. else if (priv->wordlen > 8)
  255. ((u16 *)rxp)[i] = (u16)readl(rx);
  256. else
  257. ((u8 *)rxp)[i] = (u8)readl(rx);
  258. }
  259. /* Disable the channel */
  260. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  261. /*if transfer must be terminated disable the channel*/
  262. if (flags & SPI_XFER_END) {
  263. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  264. omap3_spi_write_chconf(priv, chconf);
  265. }
  266. return 0;
  267. }
  268. static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
  269. const void *dout, void *din, unsigned long flags)
  270. {
  271. unsigned int len;
  272. int ret = -1;
  273. if (priv->wordlen < 4 || priv->wordlen > 32) {
  274. printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
  275. return -1;
  276. }
  277. if (bitlen % priv->wordlen)
  278. return -1;
  279. len = bitlen / priv->wordlen;
  280. if (bitlen == 0) { /* only change CS */
  281. int chconf = readl(&priv->regs->channel[priv->cs].chconf);
  282. if (flags & SPI_XFER_BEGIN) {
  283. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  284. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  285. omap3_spi_write_chconf(priv, chconf);
  286. }
  287. if (flags & SPI_XFER_END) {
  288. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  289. omap3_spi_write_chconf(priv, chconf);
  290. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  291. }
  292. ret = 0;
  293. } else {
  294. if (dout != NULL && din != NULL)
  295. ret = omap3_spi_txrx(priv, len, dout, din, flags);
  296. else if (dout != NULL)
  297. ret = omap3_spi_write(priv, len, dout, flags);
  298. else if (din != NULL)
  299. ret = omap3_spi_read(priv, len, din, flags);
  300. }
  301. return ret;
  302. }
  303. static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
  304. {
  305. uint32_t confr, div = 0;
  306. confr = readl(&priv->regs->channel[priv->cs].chconf);
  307. /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
  308. if (priv->freq) {
  309. while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
  310. > priv->freq)
  311. div++;
  312. } else {
  313. div = 0xC;
  314. }
  315. /* set clock divisor */
  316. confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
  317. confr |= div << 2;
  318. omap3_spi_write_chconf(priv, confr);
  319. }
  320. static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
  321. {
  322. uint32_t confr;
  323. confr = readl(&priv->regs->channel[priv->cs].chconf);
  324. /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
  325. * REVISIT: this controller could support SPI_3WIRE mode.
  326. */
  327. if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
  328. confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
  329. confr |= OMAP3_MCSPI_CHCONF_DPE0;
  330. } else {
  331. confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
  332. confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
  333. }
  334. /* set SPI mode 0..3 */
  335. confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
  336. if (priv->mode & SPI_CPHA)
  337. confr |= OMAP3_MCSPI_CHCONF_PHA;
  338. if (priv->mode & SPI_CPOL)
  339. confr |= OMAP3_MCSPI_CHCONF_POL;
  340. /* set chipselect polarity; manage with FORCE */
  341. if (!(priv->mode & SPI_CS_HIGH))
  342. confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
  343. else
  344. confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
  345. /* Transmit & receive mode */
  346. confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
  347. omap3_spi_write_chconf(priv, confr);
  348. }
  349. static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
  350. {
  351. unsigned int confr;
  352. /* McSPI individual channel configuration */
  353. confr = readl(&priv->regs->channel[priv->cs].chconf);
  354. /* wordlength */
  355. confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
  356. confr |= (priv->wordlen - 1) << 7;
  357. omap3_spi_write_chconf(priv, confr);
  358. }
  359. static void spi_reset(struct mcspi *regs)
  360. {
  361. unsigned int tmp;
  362. writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
  363. do {
  364. tmp = readl(&regs->sysstatus);
  365. } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
  366. writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
  367. OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
  368. OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
  369. writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
  370. }
  371. static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
  372. {
  373. unsigned int conf;
  374. /*
  375. * setup when switching from (reset default) slave mode
  376. * to single-channel master mode
  377. */
  378. conf = readl(&priv->regs->modulctrl);
  379. conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
  380. conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
  381. writel(conf, &priv->regs->modulctrl);
  382. }
  383. #ifndef CONFIG_DM_SPI
  384. static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
  385. {
  386. return container_of(slave, struct omap3_spi_priv, slave);
  387. }
  388. void spi_free_slave(struct spi_slave *slave)
  389. {
  390. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  391. free(priv);
  392. }
  393. int spi_claim_bus(struct spi_slave *slave)
  394. {
  395. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  396. spi_reset(priv->regs);
  397. _omap3_spi_claim_bus(priv);
  398. _omap3_spi_set_wordlen(priv);
  399. _omap3_spi_set_mode(priv);
  400. _omap3_spi_set_speed(priv);
  401. return 0;
  402. }
  403. void spi_release_bus(struct spi_slave *slave)
  404. {
  405. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  406. writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
  407. }
  408. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  409. unsigned int max_hz, unsigned int mode)
  410. {
  411. struct omap3_spi_priv *priv;
  412. struct mcspi *regs;
  413. /*
  414. * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
  415. * with different number of chip selects (CS, channels):
  416. * McSPI1 has 4 CS (bus 0, cs 0 - 3)
  417. * McSPI2 has 2 CS (bus 1, cs 0 - 1)
  418. * McSPI3 has 2 CS (bus 2, cs 0 - 1)
  419. * McSPI4 has 1 CS (bus 3, cs 0)
  420. */
  421. switch (bus) {
  422. case 0:
  423. regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
  424. break;
  425. #ifdef OMAP3_MCSPI2_BASE
  426. case 1:
  427. regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
  428. break;
  429. #endif
  430. #ifdef OMAP3_MCSPI3_BASE
  431. case 2:
  432. regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
  433. break;
  434. #endif
  435. #ifdef OMAP3_MCSPI4_BASE
  436. case 3:
  437. regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
  438. break;
  439. #endif
  440. default:
  441. printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus);
  442. return NULL;
  443. }
  444. if (((bus == 0) && (cs > 3)) ||
  445. ((bus == 1) && (cs > 1)) ||
  446. ((bus == 2) && (cs > 1)) ||
  447. ((bus == 3) && (cs > 0))) {
  448. printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
  449. return NULL;
  450. }
  451. if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
  452. printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n",
  453. max_hz);
  454. return NULL;
  455. }
  456. if (mode > SPI_MODE_3) {
  457. printf("SPI error: unsupported SPI mode %i\n", mode);
  458. return NULL;
  459. }
  460. priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
  461. if (!priv) {
  462. printf("SPI error: malloc of SPI structure failed\n");
  463. return NULL;
  464. }
  465. priv->regs = regs;
  466. priv->cs = cs;
  467. priv->freq = max_hz;
  468. priv->mode = mode;
  469. priv->wordlen = priv->slave.wordlen;
  470. #if 0
  471. /* Please migrate to DM_SPI support for this feature. */
  472. priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
  473. #endif
  474. return &priv->slave;
  475. }
  476. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  477. const void *dout, void *din, unsigned long flags)
  478. {
  479. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  480. return _spi_xfer(priv, bitlen, dout, din, flags);
  481. }
  482. #else
  483. static int omap3_spi_claim_bus(struct udevice *dev)
  484. {
  485. struct udevice *bus = dev->parent;
  486. struct omap3_spi_priv *priv = dev_get_priv(bus);
  487. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  488. priv->cs = slave_plat->cs;
  489. priv->freq = slave_plat->max_hz;
  490. _omap3_spi_claim_bus(priv);
  491. return 0;
  492. }
  493. static int omap3_spi_release_bus(struct udevice *dev)
  494. {
  495. struct udevice *bus = dev->parent;
  496. struct omap3_spi_priv *priv = dev_get_priv(bus);
  497. writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
  498. return 0;
  499. }
  500. static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
  501. {
  502. struct udevice *bus = dev->parent;
  503. struct omap3_spi_priv *priv = dev_get_priv(bus);
  504. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  505. priv->cs = slave_plat->cs;
  506. priv->wordlen = wordlen;
  507. _omap3_spi_set_wordlen(priv);
  508. return 0;
  509. }
  510. static int omap3_spi_probe(struct udevice *dev)
  511. {
  512. struct omap3_spi_priv *priv = dev_get_priv(dev);
  513. const void *blob = gd->fdt_blob;
  514. int node = dev_of_offset(dev);
  515. struct omap2_mcspi_platform_config* data =
  516. (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
  517. priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
  518. if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
  519. priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
  520. else
  521. priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
  522. priv->wordlen = SPI_DEFAULT_WORDLEN;
  523. spi_reset(priv->regs);
  524. return 0;
  525. }
  526. static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
  527. const void *dout, void *din, unsigned long flags)
  528. {
  529. struct udevice *bus = dev->parent;
  530. struct omap3_spi_priv *priv = dev_get_priv(bus);
  531. return _spi_xfer(priv, bitlen, dout, din, flags);
  532. }
  533. static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
  534. {
  535. struct omap3_spi_priv *priv = dev_get_priv(dev);
  536. priv->freq = speed;
  537. _omap3_spi_set_speed(priv);
  538. return 0;
  539. }
  540. static int omap3_spi_set_mode(struct udevice *dev, uint mode)
  541. {
  542. struct omap3_spi_priv *priv = dev_get_priv(dev);
  543. priv->mode = mode;
  544. _omap3_spi_set_mode(priv);
  545. return 0;
  546. }
  547. static const struct dm_spi_ops omap3_spi_ops = {
  548. .claim_bus = omap3_spi_claim_bus,
  549. .release_bus = omap3_spi_release_bus,
  550. .set_wordlen = omap3_spi_set_wordlen,
  551. .xfer = omap3_spi_xfer,
  552. .set_speed = omap3_spi_set_speed,
  553. .set_mode = omap3_spi_set_mode,
  554. /*
  555. * cs_info is not needed, since we require all chip selects to be
  556. * in the device tree explicitly
  557. */
  558. };
  559. static struct omap2_mcspi_platform_config omap2_pdata = {
  560. .regs_offset = 0,
  561. };
  562. static struct omap2_mcspi_platform_config omap4_pdata = {
  563. .regs_offset = OMAP4_MCSPI_REG_OFFSET,
  564. };
  565. static const struct udevice_id omap3_spi_ids[] = {
  566. { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
  567. { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
  568. { }
  569. };
  570. U_BOOT_DRIVER(omap3_spi) = {
  571. .name = "omap3_spi",
  572. .id = UCLASS_SPI,
  573. .of_match = omap3_spi_ids,
  574. .probe = omap3_spi_probe,
  575. .ops = &omap3_spi_ops,
  576. .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
  577. };
  578. #endif