nxp_fspi.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NXP FlexSPI(FSPI) controller driver.
  4. *
  5. * Copyright (c) 2019 Michael Walle <michael@walle.cc>
  6. * Copyright (c) 2019 NXP
  7. *
  8. * This driver was originally ported from the linux kernel v5.4-rc3, which had
  9. * the following notes:
  10. *
  11. * FlexSPI is a flexsible SPI host controller which supports two SPI
  12. * channels and up to 4 external devices. Each channel supports
  13. * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
  14. * data lines).
  15. *
  16. * FlexSPI controller is driven by the LUT(Look-up Table) registers
  17. * LUT registers are a look-up-table for sequences of instructions.
  18. * A valid sequence consists of four LUT registers.
  19. * Maximum 32 LUT sequences can be programmed simultaneously.
  20. *
  21. * LUTs are being created at run-time based on the commands passed
  22. * from the spi-mem framework, thus using single LUT index.
  23. *
  24. * Software triggered Flash read/write access by IP Bus.
  25. *
  26. * Memory mapped read access by AHB Bus.
  27. *
  28. * Based on SPI MEM interface and spi-fsl-qspi.c driver.
  29. *
  30. * Author:
  31. * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
  32. * Boris Brezillon <bbrezillon@kernel.org>
  33. * Frieder Schrempf <frieder.schrempf@kontron.de>
  34. */
  35. #include <common.h>
  36. #include <asm/io.h>
  37. #include <malloc.h>
  38. #include <spi.h>
  39. #include <spi-mem.h>
  40. #include <dm.h>
  41. #include <clk.h>
  42. #include <linux/kernel.h>
  43. #include <linux/sizes.h>
  44. #include <linux/iopoll.h>
  45. #include <linux/bug.h>
  46. #include <linux/err.h>
  47. /*
  48. * The driver only uses one single LUT entry, that is updated on
  49. * each call of exec_op(). Index 0 is preset at boot with a basic
  50. * read operation, so let's use the last entry (31).
  51. */
  52. #define SEQID_LUT 31
  53. /* Registers used by the driver */
  54. #define FSPI_MCR0 0x00
  55. #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
  56. #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
  57. #define FSPI_MCR0_LEARN_EN BIT(15)
  58. #define FSPI_MCR0_SCRFRUN_EN BIT(14)
  59. #define FSPI_MCR0_OCTCOMB_EN BIT(13)
  60. #define FSPI_MCR0_DOZE_EN BIT(12)
  61. #define FSPI_MCR0_HSEN BIT(11)
  62. #define FSPI_MCR0_SERCLKDIV BIT(8)
  63. #define FSPI_MCR0_ATDF_EN BIT(7)
  64. #define FSPI_MCR0_ARDF_EN BIT(6)
  65. #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
  66. #define FSPI_MCR0_END_CFG(x) ((x) << 2)
  67. #define FSPI_MCR0_MDIS BIT(1)
  68. #define FSPI_MCR0_SWRST BIT(0)
  69. #define FSPI_MCR1 0x04
  70. #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
  71. #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
  72. #define FSPI_MCR2 0x08
  73. #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
  74. #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
  75. #define FSPI_MCR2_CLRLRPHS BIT(14)
  76. #define FSPI_MCR2_ABRDATSZ BIT(8)
  77. #define FSPI_MCR2_ABRLEARN BIT(7)
  78. #define FSPI_MCR2_ABR_READ BIT(6)
  79. #define FSPI_MCR2_ABRWRITE BIT(5)
  80. #define FSPI_MCR2_ABRDUMMY BIT(4)
  81. #define FSPI_MCR2_ABR_MODE BIT(3)
  82. #define FSPI_MCR2_ABRCADDR BIT(2)
  83. #define FSPI_MCR2_ABRRADDR BIT(1)
  84. #define FSPI_MCR2_ABR_CMD BIT(0)
  85. #define FSPI_AHBCR 0x0c
  86. #define FSPI_AHBCR_RDADDROPT BIT(6)
  87. #define FSPI_AHBCR_PREF_EN BIT(5)
  88. #define FSPI_AHBCR_BUFF_EN BIT(4)
  89. #define FSPI_AHBCR_CACH_EN BIT(3)
  90. #define FSPI_AHBCR_CLRTXBUF BIT(2)
  91. #define FSPI_AHBCR_CLRRXBUF BIT(1)
  92. #define FSPI_AHBCR_PAR_EN BIT(0)
  93. #define FSPI_INTEN 0x10
  94. #define FSPI_INTEN_SCLKSBWR BIT(9)
  95. #define FSPI_INTEN_SCLKSBRD BIT(8)
  96. #define FSPI_INTEN_DATALRNFL BIT(7)
  97. #define FSPI_INTEN_IPTXWE BIT(6)
  98. #define FSPI_INTEN_IPRXWA BIT(5)
  99. #define FSPI_INTEN_AHBCMDERR BIT(4)
  100. #define FSPI_INTEN_IPCMDERR BIT(3)
  101. #define FSPI_INTEN_AHBCMDGE BIT(2)
  102. #define FSPI_INTEN_IPCMDGE BIT(1)
  103. #define FSPI_INTEN_IPCMDDONE BIT(0)
  104. #define FSPI_INTR 0x14
  105. #define FSPI_INTR_SCLKSBWR BIT(9)
  106. #define FSPI_INTR_SCLKSBRD BIT(8)
  107. #define FSPI_INTR_DATALRNFL BIT(7)
  108. #define FSPI_INTR_IPTXWE BIT(6)
  109. #define FSPI_INTR_IPRXWA BIT(5)
  110. #define FSPI_INTR_AHBCMDERR BIT(4)
  111. #define FSPI_INTR_IPCMDERR BIT(3)
  112. #define FSPI_INTR_AHBCMDGE BIT(2)
  113. #define FSPI_INTR_IPCMDGE BIT(1)
  114. #define FSPI_INTR_IPCMDDONE BIT(0)
  115. #define FSPI_LUTKEY 0x18
  116. #define FSPI_LUTKEY_VALUE 0x5AF05AF0
  117. #define FSPI_LCKCR 0x1C
  118. #define FSPI_LCKER_LOCK 0x1
  119. #define FSPI_LCKER_UNLOCK 0x2
  120. #define FSPI_BUFXCR_INVALID_MSTRID 0xE
  121. #define FSPI_AHBRX_BUF0CR0 0x20
  122. #define FSPI_AHBRX_BUF1CR0 0x24
  123. #define FSPI_AHBRX_BUF2CR0 0x28
  124. #define FSPI_AHBRX_BUF3CR0 0x2C
  125. #define FSPI_AHBRX_BUF4CR0 0x30
  126. #define FSPI_AHBRX_BUF5CR0 0x34
  127. #define FSPI_AHBRX_BUF6CR0 0x38
  128. #define FSPI_AHBRX_BUF7CR0 0x3C
  129. #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
  130. #define FSPI_AHBRX_BUF0CR1 0x40
  131. #define FSPI_AHBRX_BUF1CR1 0x44
  132. #define FSPI_AHBRX_BUF2CR1 0x48
  133. #define FSPI_AHBRX_BUF3CR1 0x4C
  134. #define FSPI_AHBRX_BUF4CR1 0x50
  135. #define FSPI_AHBRX_BUF5CR1 0x54
  136. #define FSPI_AHBRX_BUF6CR1 0x58
  137. #define FSPI_AHBRX_BUF7CR1 0x5C
  138. #define FSPI_FLSHA1CR0 0x60
  139. #define FSPI_FLSHA2CR0 0x64
  140. #define FSPI_FLSHB1CR0 0x68
  141. #define FSPI_FLSHB2CR0 0x6C
  142. #define FSPI_FLSHXCR0_SZ_KB 10
  143. #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
  144. #define FSPI_FLSHA1CR1 0x70
  145. #define FSPI_FLSHA2CR1 0x74
  146. #define FSPI_FLSHB1CR1 0x78
  147. #define FSPI_FLSHB2CR1 0x7C
  148. #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
  149. #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
  150. #define FSPI_FLSHXCR1_WA BIT(10)
  151. #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
  152. #define FSPI_FLSHXCR1_TCSS(x) (x)
  153. #define FSPI_FLSHA1CR2 0x80
  154. #define FSPI_FLSHA2CR2 0x84
  155. #define FSPI_FLSHB1CR2 0x88
  156. #define FSPI_FLSHB2CR2 0x8C
  157. #define FSPI_FLSHXCR2_CLRINSP BIT(24)
  158. #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
  159. #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
  160. #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
  161. #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
  162. #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
  163. #define FSPI_IPCR0 0xA0
  164. #define FSPI_IPCR1 0xA4
  165. #define FSPI_IPCR1_IPAREN BIT(31)
  166. #define FSPI_IPCR1_SEQNUM_SHIFT 24
  167. #define FSPI_IPCR1_SEQID_SHIFT 16
  168. #define FSPI_IPCR1_IDATSZ(x) (x)
  169. #define FSPI_IPCMD 0xB0
  170. #define FSPI_IPCMD_TRG BIT(0)
  171. #define FSPI_DLPR 0xB4
  172. #define FSPI_IPRXFCR 0xB8
  173. #define FSPI_IPRXFCR_CLR BIT(0)
  174. #define FSPI_IPRXFCR_DMA_EN BIT(1)
  175. #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
  176. #define FSPI_IPTXFCR 0xBC
  177. #define FSPI_IPTXFCR_CLR BIT(0)
  178. #define FSPI_IPTXFCR_DMA_EN BIT(1)
  179. #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
  180. #define FSPI_DLLACR 0xC0
  181. #define FSPI_DLLACR_OVRDEN BIT(8)
  182. #define FSPI_DLLBCR 0xC4
  183. #define FSPI_DLLBCR_OVRDEN BIT(8)
  184. #define FSPI_STS0 0xE0
  185. #define FSPI_STS0_DLPHB(x) ((x) << 8)
  186. #define FSPI_STS0_DLPHA(x) ((x) << 4)
  187. #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
  188. #define FSPI_STS0_ARB_IDLE BIT(1)
  189. #define FSPI_STS0_SEQ_IDLE BIT(0)
  190. #define FSPI_STS1 0xE4
  191. #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
  192. #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
  193. #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
  194. #define FSPI_STS1_AHB_ERRID(x) (x)
  195. #define FSPI_AHBSPNST 0xEC
  196. #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
  197. #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
  198. #define FSPI_AHBSPNST_ACTIVE BIT(0)
  199. #define FSPI_IPRXFSTS 0xF0
  200. #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
  201. #define FSPI_IPRXFSTS_FILL(x) (x)
  202. #define FSPI_IPTXFSTS 0xF4
  203. #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
  204. #define FSPI_IPTXFSTS_FILL(x) (x)
  205. #define FSPI_RFDR 0x100
  206. #define FSPI_TFDR 0x180
  207. #define FSPI_LUT_BASE 0x200
  208. #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  209. #define FSPI_LUT_REG(idx) \
  210. (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
  211. /* register map end */
  212. /* Instruction set for the LUT register. */
  213. #define LUT_STOP 0x00
  214. #define LUT_CMD 0x01
  215. #define LUT_ADDR 0x02
  216. #define LUT_CADDR_SDR 0x03
  217. #define LUT_MODE 0x04
  218. #define LUT_MODE2 0x05
  219. #define LUT_MODE4 0x06
  220. #define LUT_MODE8 0x07
  221. #define LUT_NXP_WRITE 0x08
  222. #define LUT_NXP_READ 0x09
  223. #define LUT_LEARN_SDR 0x0A
  224. #define LUT_DATSZ_SDR 0x0B
  225. #define LUT_DUMMY 0x0C
  226. #define LUT_DUMMY_RWDS_SDR 0x0D
  227. #define LUT_JMP_ON_CS 0x1F
  228. #define LUT_CMD_DDR 0x21
  229. #define LUT_ADDR_DDR 0x22
  230. #define LUT_CADDR_DDR 0x23
  231. #define LUT_MODE_DDR 0x24
  232. #define LUT_MODE2_DDR 0x25
  233. #define LUT_MODE4_DDR 0x26
  234. #define LUT_MODE8_DDR 0x27
  235. #define LUT_WRITE_DDR 0x28
  236. #define LUT_READ_DDR 0x29
  237. #define LUT_LEARN_DDR 0x2A
  238. #define LUT_DATSZ_DDR 0x2B
  239. #define LUT_DUMMY_DDR 0x2C
  240. #define LUT_DUMMY_RWDS_DDR 0x2D
  241. /*
  242. * Calculate number of required PAD bits for LUT register.
  243. *
  244. * The pad stands for the number of IO lines [0:7].
  245. * For example, the octal read needs eight IO lines,
  246. * so you should use LUT_PAD(8). This macro
  247. * returns 3 i.e. use eight (2^3) IP lines for read.
  248. */
  249. #define LUT_PAD(x) (fls(x) - 1)
  250. /*
  251. * Macro for constructing the LUT entries with the following
  252. * register layout:
  253. *
  254. * ---------------------------------------------------
  255. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  256. * ---------------------------------------------------
  257. */
  258. #define PAD_SHIFT 8
  259. #define INSTR_SHIFT 10
  260. #define OPRND_SHIFT 16
  261. /* Macros for constructing the LUT register. */
  262. #define LUT_DEF(idx, ins, pad, opr) \
  263. ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
  264. (opr)) << (((idx) % 2) * OPRND_SHIFT))
  265. #define POLL_TOUT 5000
  266. #define NXP_FSPI_MAX_CHIPSELECT 4
  267. struct nxp_fspi_devtype_data {
  268. unsigned int rxfifo;
  269. unsigned int txfifo;
  270. unsigned int ahb_buf_size;
  271. unsigned int quirks;
  272. bool little_endian;
  273. };
  274. static const struct nxp_fspi_devtype_data lx2160a_data = {
  275. .rxfifo = SZ_512, /* (64 * 64 bits) */
  276. .txfifo = SZ_1K, /* (128 * 64 bits) */
  277. .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
  278. .quirks = 0,
  279. .little_endian = true, /* little-endian */
  280. };
  281. struct nxp_fspi {
  282. struct udevice *dev;
  283. void __iomem *iobase;
  284. void __iomem *ahb_addr;
  285. u32 memmap_phy;
  286. u32 memmap_phy_size;
  287. struct clk clk, clk_en;
  288. const struct nxp_fspi_devtype_data *devtype_data;
  289. };
  290. /*
  291. * R/W functions for big- or little-endian registers:
  292. * The FSPI controller's endianness is independent of
  293. * the CPU core's endianness. So far, although the CPU
  294. * core is little-endian the FSPI controller can use
  295. * big-endian or little-endian.
  296. */
  297. static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
  298. {
  299. if (f->devtype_data->little_endian)
  300. out_le32(addr, val);
  301. else
  302. out_be32(addr, val);
  303. }
  304. static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
  305. {
  306. if (f->devtype_data->little_endian)
  307. return in_le32(addr);
  308. else
  309. return in_be32(addr);
  310. }
  311. static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
  312. {
  313. switch (width) {
  314. case 1:
  315. case 2:
  316. case 4:
  317. case 8:
  318. return 0;
  319. }
  320. return -ENOTSUPP;
  321. }
  322. static bool nxp_fspi_supports_op(struct spi_slave *slave,
  323. const struct spi_mem_op *op)
  324. {
  325. struct nxp_fspi *f;
  326. struct udevice *bus;
  327. int ret;
  328. bus = slave->dev->parent;
  329. f = dev_get_priv(bus);
  330. ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
  331. if (op->addr.nbytes)
  332. ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
  333. if (op->dummy.nbytes)
  334. ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
  335. if (op->data.nbytes)
  336. ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
  337. if (ret)
  338. return false;
  339. /*
  340. * The number of address bytes should be equal to or less than 4 bytes.
  341. */
  342. if (op->addr.nbytes > 4)
  343. return false;
  344. /*
  345. * If requested address value is greater than controller assigned
  346. * memory mapped space, return error as it didn't fit in the range
  347. * of assigned address space.
  348. */
  349. if (op->addr.val >= f->memmap_phy_size)
  350. return false;
  351. /* Max 64 dummy clock cycles supported */
  352. if (op->dummy.buswidth &&
  353. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  354. return false;
  355. /* Max data length, check controller limits and alignment */
  356. if (op->data.dir == SPI_MEM_DATA_IN &&
  357. (op->data.nbytes > f->devtype_data->ahb_buf_size ||
  358. (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
  359. !IS_ALIGNED(op->data.nbytes, 8))))
  360. return false;
  361. if (op->data.dir == SPI_MEM_DATA_OUT &&
  362. op->data.nbytes > f->devtype_data->txfifo)
  363. return false;
  364. return true;
  365. }
  366. /* Instead of busy looping invoke readl_poll_timeout functionality. */
  367. static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
  368. u32 mask, u32 delay_us,
  369. u32 timeout_us, bool c)
  370. {
  371. u32 reg;
  372. if (!f->devtype_data->little_endian)
  373. mask = (u32)cpu_to_be32(mask);
  374. if (c)
  375. return readl_poll_timeout(base, reg, (reg & mask),
  376. timeout_us);
  377. else
  378. return readl_poll_timeout(base, reg, !(reg & mask),
  379. timeout_us);
  380. }
  381. /*
  382. * If the slave device content being changed by Write/Erase, need to
  383. * invalidate the AHB buffer. This can be achieved by doing the reset
  384. * of controller after setting MCR0[SWRESET] bit.
  385. */
  386. static inline void nxp_fspi_invalid(struct nxp_fspi *f)
  387. {
  388. u32 reg;
  389. int ret;
  390. reg = fspi_readl(f, f->iobase + FSPI_MCR0);
  391. fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
  392. /* w1c register, wait unit clear */
  393. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  394. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  395. WARN_ON(ret);
  396. }
  397. static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
  398. const struct spi_mem_op *op)
  399. {
  400. void __iomem *base = f->iobase;
  401. u32 lutval[4] = {};
  402. int lutidx = 1, i;
  403. /* cmd */
  404. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  405. op->cmd.opcode);
  406. /* addr bytes */
  407. if (op->addr.nbytes) {
  408. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
  409. LUT_PAD(op->addr.buswidth),
  410. op->addr.nbytes * 8);
  411. lutidx++;
  412. }
  413. /* dummy bytes, if needed */
  414. if (op->dummy.nbytes) {
  415. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  416. /*
  417. * Due to FlexSPI controller limitation number of PAD for dummy
  418. * buswidth needs to be programmed as equal to data buswidth.
  419. */
  420. LUT_PAD(op->data.buswidth),
  421. op->dummy.nbytes * 8 /
  422. op->dummy.buswidth);
  423. lutidx++;
  424. }
  425. /* read/write data bytes */
  426. if (op->data.nbytes) {
  427. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  428. op->data.dir == SPI_MEM_DATA_IN ?
  429. LUT_NXP_READ : LUT_NXP_WRITE,
  430. LUT_PAD(op->data.buswidth),
  431. 0);
  432. lutidx++;
  433. }
  434. /* stop condition. */
  435. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  436. /* unlock LUT */
  437. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  438. fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
  439. /* fill LUT */
  440. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  441. fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
  442. dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  443. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  444. /* lock LUT */
  445. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  446. fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
  447. }
  448. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  449. static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
  450. {
  451. int ret;
  452. ret = clk_enable(&f->clk_en);
  453. if (ret)
  454. return ret;
  455. ret = clk_enable(&f->clk);
  456. if (ret) {
  457. clk_disable(&f->clk_en);
  458. return ret;
  459. }
  460. return 0;
  461. }
  462. static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
  463. {
  464. clk_disable(&f->clk);
  465. clk_disable(&f->clk_en);
  466. }
  467. #endif
  468. /*
  469. * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
  470. * register and start base address of the slave device.
  471. *
  472. * (Higher address)
  473. * -------- <-- FLSHB2CR0
  474. * | B2 |
  475. * | |
  476. * B2 start address --> -------- <-- FLSHB1CR0
  477. * | B1 |
  478. * | |
  479. * B1 start address --> -------- <-- FLSHA2CR0
  480. * | A2 |
  481. * | |
  482. * A2 start address --> -------- <-- FLSHA1CR0
  483. * | A1 |
  484. * | |
  485. * A1 start address --> -------- (Lower address)
  486. *
  487. *
  488. * Start base address defines the starting address range for given CS and
  489. * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
  490. *
  491. * But, different targets are having different combinations of number of CS,
  492. * some targets only have single CS or two CS covering controller's full
  493. * memory mapped space area.
  494. * Thus, implementation is being done as independent of the size and number
  495. * of the connected slave device.
  496. * Assign controller memory mapped space size as the size to the connected
  497. * slave device.
  498. * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
  499. * chip-select Flash configuration register.
  500. *
  501. * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
  502. * memory mapped size of the controller.
  503. * Value for rest of the CS FLSHxxCR0 register would be zero.
  504. *
  505. */
  506. static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
  507. {
  508. u64 size_kb;
  509. /* Reset FLSHxxCR0 registers */
  510. fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
  511. fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
  512. fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
  513. fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
  514. /* Assign controller memory mapped space as size, KBytes, of flash. */
  515. size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
  516. fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
  517. 4 * chip_select);
  518. dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
  519. }
  520. static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
  521. {
  522. u32 len = op->data.nbytes;
  523. /* Read out the data directly from the AHB buffer. */
  524. memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
  525. }
  526. static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
  527. const struct spi_mem_op *op)
  528. {
  529. void __iomem *base = f->iobase;
  530. int i, ret;
  531. u8 *buf = (u8 *)op->data.buf.out;
  532. /* clear the TX FIFO. */
  533. fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
  534. /*
  535. * Default value of water mark level is 8 bytes, hence in single
  536. * write request controller can write max 8 bytes of data.
  537. */
  538. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
  539. /* Wait for TXFIFO empty */
  540. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  541. FSPI_INTR_IPTXWE, 0,
  542. POLL_TOUT, true);
  543. WARN_ON(ret);
  544. fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
  545. fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
  546. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  547. }
  548. if (i < op->data.nbytes) {
  549. u32 data = 0;
  550. int j;
  551. /* Wait for TXFIFO empty */
  552. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  553. FSPI_INTR_IPTXWE, 0,
  554. POLL_TOUT, true);
  555. WARN_ON(ret);
  556. for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
  557. memcpy(&data, buf + i + j, 4);
  558. fspi_writel(f, data, base + FSPI_TFDR + j);
  559. }
  560. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  561. }
  562. }
  563. static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
  564. const struct spi_mem_op *op)
  565. {
  566. void __iomem *base = f->iobase;
  567. int i, ret;
  568. int len = op->data.nbytes;
  569. u8 *buf = (u8 *)op->data.buf.in;
  570. /*
  571. * Default value of water mark level is 8 bytes, hence in single
  572. * read request controller can read max 8 bytes of data.
  573. */
  574. for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
  575. /* Wait for RXFIFO available */
  576. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  577. FSPI_INTR_IPRXWA, 0,
  578. POLL_TOUT, true);
  579. WARN_ON(ret);
  580. *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
  581. *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
  582. /* move the FIFO pointer */
  583. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  584. }
  585. if (i < len) {
  586. u32 tmp;
  587. int size, j;
  588. buf = op->data.buf.in + i;
  589. /* Wait for RXFIFO available */
  590. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  591. FSPI_INTR_IPRXWA, 0,
  592. POLL_TOUT, true);
  593. WARN_ON(ret);
  594. len = op->data.nbytes - i;
  595. for (j = 0; j < op->data.nbytes - i; j += 4) {
  596. tmp = fspi_readl(f, base + FSPI_RFDR + j);
  597. size = min(len, 4);
  598. memcpy(buf + j, &tmp, size);
  599. len -= size;
  600. }
  601. }
  602. /* invalid the RXFIFO */
  603. fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
  604. /* move the FIFO pointer */
  605. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  606. }
  607. static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
  608. {
  609. void __iomem *base = f->iobase;
  610. int seqnum = 0;
  611. int err = 0;
  612. u32 reg;
  613. reg = fspi_readl(f, base + FSPI_IPRXFCR);
  614. /* invalid RXFIFO first */
  615. reg &= ~FSPI_IPRXFCR_DMA_EN;
  616. reg = reg | FSPI_IPRXFCR_CLR;
  617. fspi_writel(f, reg, base + FSPI_IPRXFCR);
  618. fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
  619. /*
  620. * Always start the sequence at the same index since we update
  621. * the LUT at each exec_op() call. And also specify the DATA
  622. * length, since it's has not been specified in the LUT.
  623. */
  624. fspi_writel(f, op->data.nbytes |
  625. (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
  626. (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
  627. base + FSPI_IPCR1);
  628. /* Trigger the LUT now. */
  629. fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
  630. /* Wait for the completion. */
  631. err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
  632. FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
  633. /* Invoke IP data read, if request is of data read. */
  634. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  635. nxp_fspi_read_rxfifo(f, op);
  636. return err;
  637. }
  638. static int nxp_fspi_exec_op(struct spi_slave *slave,
  639. const struct spi_mem_op *op)
  640. {
  641. struct nxp_fspi *f;
  642. struct udevice *bus;
  643. int err = 0;
  644. bus = slave->dev->parent;
  645. f = dev_get_priv(bus);
  646. /* Wait for controller being ready. */
  647. err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
  648. FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
  649. WARN_ON(err);
  650. nxp_fspi_prepare_lut(f, op);
  651. /*
  652. * If we have large chunks of data, we read them through the AHB bus
  653. * by accessing the mapped memory. In all other cases we use
  654. * IP commands to access the flash.
  655. */
  656. if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
  657. op->data.dir == SPI_MEM_DATA_IN) {
  658. nxp_fspi_read_ahb(f, op);
  659. } else {
  660. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  661. nxp_fspi_fill_txfifo(f, op);
  662. err = nxp_fspi_do_op(f, op);
  663. }
  664. /* Invalidate the data in the AHB buffer. */
  665. nxp_fspi_invalid(f);
  666. return err;
  667. }
  668. static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
  669. struct spi_mem_op *op)
  670. {
  671. struct nxp_fspi *f;
  672. struct udevice *bus;
  673. bus = slave->dev->parent;
  674. f = dev_get_priv(bus);
  675. if (op->data.dir == SPI_MEM_DATA_OUT) {
  676. if (op->data.nbytes > f->devtype_data->txfifo)
  677. op->data.nbytes = f->devtype_data->txfifo;
  678. } else {
  679. if (op->data.nbytes > f->devtype_data->ahb_buf_size)
  680. op->data.nbytes = f->devtype_data->ahb_buf_size;
  681. else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
  682. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  683. }
  684. return 0;
  685. }
  686. static int nxp_fspi_default_setup(struct nxp_fspi *f)
  687. {
  688. void __iomem *base = f->iobase;
  689. int ret, i;
  690. u32 reg;
  691. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  692. /* disable and unprepare clock to avoid glitch pass to controller */
  693. nxp_fspi_clk_disable_unprep(f);
  694. /* the default frequency, we will change it later if necessary. */
  695. ret = clk_set_rate(&f->clk, 20000000);
  696. if (ret)
  697. return ret;
  698. ret = nxp_fspi_clk_prep_enable(f);
  699. if (ret)
  700. return ret;
  701. #endif
  702. /* Reset the module */
  703. /* w1c register, wait unit clear */
  704. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  705. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  706. WARN_ON(ret);
  707. /* Disable the module */
  708. fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
  709. /* Reset the DLL register to default value */
  710. fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
  711. fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
  712. /* enable module */
  713. fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
  714. base + FSPI_MCR0);
  715. /*
  716. * Disable same device enable bit and configure all slave devices
  717. * independently.
  718. */
  719. reg = fspi_readl(f, f->iobase + FSPI_MCR2);
  720. reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
  721. fspi_writel(f, reg, base + FSPI_MCR2);
  722. /* AHB configuration for access buffer 0~7. */
  723. for (i = 0; i < 7; i++)
  724. fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
  725. /*
  726. * Set ADATSZ with the maximum AHB buffer size to improve the read
  727. * performance.
  728. */
  729. fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
  730. FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
  731. /* prefetch and no start address alignment limitation */
  732. fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
  733. base + FSPI_AHBCR);
  734. /* AHB Read - Set lut sequence ID for all CS. */
  735. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
  736. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
  737. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
  738. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
  739. return 0;
  740. }
  741. static int nxp_fspi_probe(struct udevice *bus)
  742. {
  743. struct nxp_fspi *f = dev_get_priv(bus);
  744. f->devtype_data =
  745. (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
  746. nxp_fspi_default_setup(f);
  747. return 0;
  748. }
  749. static int nxp_fspi_claim_bus(struct udevice *dev)
  750. {
  751. struct nxp_fspi *f;
  752. struct udevice *bus;
  753. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  754. bus = dev->parent;
  755. f = dev_get_priv(bus);
  756. nxp_fspi_select_mem(f, slave_plat->cs);
  757. return 0;
  758. }
  759. static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
  760. {
  761. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  762. struct nxp_fspi *f = dev_get_priv(bus);
  763. int ret;
  764. nxp_fspi_clk_disable_unprep(f);
  765. ret = clk_set_rate(&f->clk, speed);
  766. if (ret)
  767. return ret;
  768. ret = nxp_fspi_clk_prep_enable(f);
  769. if (ret)
  770. return ret;
  771. #endif
  772. return 0;
  773. }
  774. static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
  775. {
  776. /* Nothing to do */
  777. return 0;
  778. }
  779. static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
  780. {
  781. struct nxp_fspi *f = dev_get_priv(bus);
  782. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  783. int ret;
  784. #endif
  785. fdt_addr_t iobase;
  786. fdt_addr_t iobase_size;
  787. fdt_addr_t ahb_addr;
  788. fdt_addr_t ahb_size;
  789. f->dev = bus;
  790. iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
  791. if (iobase == FDT_ADDR_T_NONE) {
  792. dev_err(bus, "fspi_base regs missing\n");
  793. return -ENODEV;
  794. }
  795. f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
  796. ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
  797. if (ahb_addr == FDT_ADDR_T_NONE) {
  798. dev_err(bus, "fspi_mmap regs missing\n");
  799. return -ENODEV;
  800. }
  801. f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
  802. f->memmap_phy_size = ahb_size;
  803. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  804. ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
  805. if (ret) {
  806. dev_err(bus, "failed to get fspi_en clock\n");
  807. return ret;
  808. }
  809. ret = clk_get_by_name(bus, "fspi", &f->clk);
  810. if (ret) {
  811. dev_err(bus, "failed to get fspi clock\n");
  812. return ret;
  813. }
  814. #endif
  815. dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
  816. return 0;
  817. }
  818. static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
  819. .adjust_op_size = nxp_fspi_adjust_op_size,
  820. .supports_op = nxp_fspi_supports_op,
  821. .exec_op = nxp_fspi_exec_op,
  822. };
  823. static const struct dm_spi_ops nxp_fspi_ops = {
  824. .claim_bus = nxp_fspi_claim_bus,
  825. .set_speed = nxp_fspi_set_speed,
  826. .set_mode = nxp_fspi_set_mode,
  827. .mem_ops = &nxp_fspi_mem_ops,
  828. };
  829. static const struct udevice_id nxp_fspi_ids[] = {
  830. { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
  831. { }
  832. };
  833. U_BOOT_DRIVER(nxp_fspi) = {
  834. .name = "nxp_fspi",
  835. .id = UCLASS_SPI,
  836. .of_match = nxp_fspi_ids,
  837. .ops = &nxp_fspi_ops,
  838. .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
  839. .priv_auto_alloc_size = sizeof(struct nxp_fspi),
  840. .probe = nxp_fspi_probe,
  841. };