mt7621_spi.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Stefan Roese <sr@denx.de>
  4. *
  5. * Derived from the Linux driver version drivers/spi/spi-mt7621.c
  6. * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  7. * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  8. * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <spi.h>
  14. #include <wait_bit.h>
  15. #include <linux/io.h>
  16. #define MT7621_RX_FIFO_LEN 32
  17. #define MT7621_TX_FIFO_LEN 36
  18. #define MT7621_SPI_TRANS 0x00
  19. #define MT7621_SPI_TRANS_START BIT(8)
  20. #define MT7621_SPI_TRANS_BUSY BIT(16)
  21. #define TRANS_ADDR_SZ GENMASK(20, 19)
  22. #define TRANS_ADDR_SZ_SHIFT 19
  23. #define TRANS_MOSI_BCNT GENMASK(3, 0)
  24. #define TRANS_MOSI_BCNT_SHIFT 0
  25. #define MT7621_SPI_OPCODE 0x04
  26. #define MT7621_SPI_DATA0 0x08
  27. #define MT7621_SPI_DATA4 0x18
  28. #define MT7621_SPI_MASTER 0x28
  29. #define MT7621_SPI_MOREBUF 0x2c
  30. #define MT7621_SPI_POLAR 0x38
  31. #define MT7621_LSB_FIRST BIT(3)
  32. #define MT7621_CPOL BIT(4)
  33. #define MT7621_CPHA BIT(5)
  34. #define MASTER_MORE_BUFMODE BIT(2)
  35. #define MASTER_RS_CLK_SEL GENMASK(27, 16)
  36. #define MASTER_RS_CLK_SEL_SHIFT 16
  37. #define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
  38. #define MOREBUF_CMD_CNT GENMASK(29, 24)
  39. #define MOREBUF_CMD_CNT_SHIFT 24
  40. #define MOREBUF_MISO_CNT GENMASK(20, 12)
  41. #define MOREBUF_MISO_CNT_SHIFT 12
  42. #define MOREBUF_MOSI_CNT GENMASK(8, 0)
  43. #define MOREBUF_MOSI_CNT_SHIFT 0
  44. struct mt7621_spi {
  45. void __iomem *base;
  46. unsigned int sys_freq;
  47. };
  48. static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
  49. {
  50. debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
  51. if (enable) {
  52. setbits_le32(rs->base + MT7621_SPI_MASTER,
  53. MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
  54. iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR);
  55. } else {
  56. iowrite32(0, rs->base + MT7621_SPI_POLAR);
  57. iowrite32((2 << TRANS_ADDR_SZ_SHIFT) |
  58. (1 << TRANS_MOSI_BCNT_SHIFT),
  59. rs->base + MT7621_SPI_TRANS);
  60. clrbits_le32(rs->base + MT7621_SPI_MASTER,
  61. MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
  62. }
  63. }
  64. static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
  65. {
  66. struct mt7621_spi *rs = dev_get_priv(bus);
  67. u32 reg;
  68. debug("%s: mode=0x%08x\n", __func__, mode);
  69. reg = ioread32(rs->base + MT7621_SPI_MASTER);
  70. reg &= ~MT7621_LSB_FIRST;
  71. if (mode & SPI_LSB_FIRST)
  72. reg |= MT7621_LSB_FIRST;
  73. reg &= ~(MT7621_CPHA | MT7621_CPOL);
  74. switch (mode & (SPI_CPOL | SPI_CPHA)) {
  75. case SPI_MODE_0:
  76. break;
  77. case SPI_MODE_1:
  78. reg |= MT7621_CPHA;
  79. break;
  80. case SPI_MODE_2:
  81. reg |= MT7621_CPOL;
  82. break;
  83. case SPI_MODE_3:
  84. reg |= MT7621_CPOL | MT7621_CPHA;
  85. break;
  86. }
  87. iowrite32(reg, rs->base + MT7621_SPI_MASTER);
  88. return 0;
  89. }
  90. static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
  91. {
  92. struct mt7621_spi *rs = dev_get_priv(bus);
  93. u32 rate;
  94. u32 reg;
  95. debug("%s: speed=%d\n", __func__, speed);
  96. rate = DIV_ROUND_UP(rs->sys_freq, speed);
  97. debug("rate:%u\n", rate);
  98. if (rate > 4097)
  99. return -EINVAL;
  100. if (rate < 2)
  101. rate = 2;
  102. reg = ioread32(rs->base + MT7621_SPI_MASTER);
  103. reg &= ~MASTER_RS_CLK_SEL;
  104. reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
  105. iowrite32(reg, rs->base + MT7621_SPI_MASTER);
  106. return 0;
  107. }
  108. static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
  109. {
  110. int ret;
  111. ret = wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
  112. MT7621_SPI_TRANS_BUSY, 0, 10, 0);
  113. if (ret)
  114. pr_err("Timeout in %s!\n", __func__);
  115. return ret;
  116. }
  117. static int mt7621_spi_read(struct mt7621_spi *rs, u8 *buf, size_t len)
  118. {
  119. size_t rx_len;
  120. int i, ret;
  121. u32 val = 0;
  122. while (len) {
  123. rx_len = min_t(size_t, len, MT7621_RX_FIFO_LEN);
  124. iowrite32((rx_len * 8) << MOREBUF_MISO_CNT_SHIFT,
  125. rs->base + MT7621_SPI_MOREBUF);
  126. iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
  127. ret = mt7621_spi_wait_till_ready(rs);
  128. if (ret)
  129. return ret;
  130. for (i = 0; i < rx_len; i++) {
  131. if ((i % 4) == 0)
  132. val = ioread32(rs->base + MT7621_SPI_DATA0 + i);
  133. *buf++ = val & 0xff;
  134. val >>= 8;
  135. }
  136. len -= rx_len;
  137. }
  138. return ret;
  139. }
  140. static int mt7621_spi_write(struct mt7621_spi *rs, const u8 *buf, size_t len)
  141. {
  142. size_t tx_len, opcode_len, dido_len;
  143. int i, ret;
  144. u32 val;
  145. while (len) {
  146. tx_len = min_t(size_t, len, MT7621_TX_FIFO_LEN);
  147. opcode_len = min_t(size_t, tx_len, 4);
  148. dido_len = tx_len - opcode_len;
  149. val = 0;
  150. for (i = 0; i < opcode_len; i++) {
  151. val <<= 8;
  152. val |= *buf++;
  153. }
  154. iowrite32(val, rs->base + MT7621_SPI_OPCODE);
  155. val = 0;
  156. for (i = 0; i < dido_len; i++) {
  157. val |= (*buf++) << ((i % 4) * 8);
  158. if ((i % 4 == 3) || (i == dido_len - 1)) {
  159. iowrite32(val, rs->base + MT7621_SPI_DATA0 +
  160. (i & ~3));
  161. val = 0;
  162. }
  163. }
  164. iowrite32(((opcode_len * 8) << MOREBUF_CMD_CNT_SHIFT) |
  165. ((dido_len * 8) << MOREBUF_MOSI_CNT_SHIFT),
  166. rs->base + MT7621_SPI_MOREBUF);
  167. iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
  168. ret = mt7621_spi_wait_till_ready(rs);
  169. if (ret)
  170. return ret;
  171. len -= tx_len;
  172. }
  173. return 0;
  174. }
  175. static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
  176. const void *dout, void *din, unsigned long flags)
  177. {
  178. struct udevice *bus = dev->parent;
  179. struct mt7621_spi *rs = dev_get_priv(bus);
  180. int total_size = bitlen >> 3;
  181. int ret = 0;
  182. debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
  183. total_size, flags);
  184. /*
  185. * This driver only supports half-duplex, so complain and bail out
  186. * upon full-duplex messages
  187. */
  188. if (dout && din) {
  189. printf("Only half-duplex SPI transfer supported\n");
  190. return -EIO;
  191. }
  192. mt7621_spi_wait_till_ready(rs);
  193. /*
  194. * Set CS active upon start of SPI message. This message can
  195. * be split upon multiple calls to this xfer function
  196. */
  197. if (flags & SPI_XFER_BEGIN)
  198. mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
  199. if (din)
  200. ret = mt7621_spi_read(rs, din, total_size);
  201. else if (dout)
  202. ret = mt7621_spi_write(rs, dout, total_size);
  203. if (flags & SPI_XFER_END)
  204. mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
  205. return ret;
  206. }
  207. static int mt7621_spi_probe(struct udevice *dev)
  208. {
  209. struct mt7621_spi *rs = dev_get_priv(dev);
  210. struct clk clk;
  211. int ret;
  212. rs->base = dev_remap_addr(dev);
  213. if (!rs->base)
  214. return -EINVAL;
  215. ret = clk_get_by_index(dev, 0, &clk);
  216. if (ret < 0) {
  217. printf("Please provide a clock!\n");
  218. return ret;
  219. }
  220. clk_enable(&clk);
  221. rs->sys_freq = clk_get_rate(&clk);
  222. if (!rs->sys_freq) {
  223. printf("Please provide a valid clock!\n");
  224. return -EINVAL;
  225. }
  226. return 0;
  227. }
  228. static const struct dm_spi_ops mt7621_spi_ops = {
  229. .set_mode = mt7621_spi_set_mode,
  230. .set_speed = mt7621_spi_set_speed,
  231. .xfer = mt7621_spi_xfer,
  232. /*
  233. * cs_info is not needed, since we require all chip selects to be
  234. * in the device tree explicitly
  235. */
  236. };
  237. static const struct udevice_id mt7621_spi_ids[] = {
  238. { .compatible = "ralink,mt7621-spi" },
  239. { }
  240. };
  241. U_BOOT_DRIVER(mt7621_spi) = {
  242. .name = "mt7621_spi",
  243. .id = UCLASS_SPI,
  244. .of_match = mt7621_spi_ids,
  245. .ops = &mt7621_spi_ops,
  246. .priv_auto_alloc_size = sizeof(struct mt7621_spi),
  247. .probe = mt7621_spi_probe,
  248. };