kirkwood_spi.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * Derived from drivers/spi/mpc8xxx_spi.c
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/soc.h>
  15. #ifdef CONFIG_KIRKWOOD
  16. #include <asm/arch/mpp.h>
  17. #endif
  18. #include <asm/arch-mvebu/spi.h>
  19. static void _spi_cs_activate(struct kwspi_registers *reg)
  20. {
  21. setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
  22. }
  23. static void _spi_cs_deactivate(struct kwspi_registers *reg)
  24. {
  25. clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
  26. }
  27. static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
  28. const void *dout, void *din, unsigned long flags)
  29. {
  30. unsigned int tmpdout, tmpdin;
  31. int tm, isread = 0;
  32. debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
  33. if (flags & SPI_XFER_BEGIN)
  34. _spi_cs_activate(reg);
  35. /*
  36. * handle data in 8-bit chunks
  37. * TBD: 2byte xfer mode to be enabled
  38. */
  39. clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
  40. while (bitlen > 4) {
  41. debug("loopstart bitlen %d\n", bitlen);
  42. tmpdout = 0;
  43. /* Shift data so it's msb-justified */
  44. if (dout)
  45. tmpdout = *(u32 *)dout & 0xff;
  46. clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
  47. writel(tmpdout, &reg->dout); /* Write the data out */
  48. debug("*** spi_xfer: ... %08x written, bitlen %d\n",
  49. tmpdout, bitlen);
  50. /*
  51. * Wait for SPI transmit to get out
  52. * or time out (1 second = 1000 ms)
  53. * The NE event must be read and cleared first
  54. */
  55. for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
  56. if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
  57. isread = 1;
  58. tmpdin = readl(&reg->din);
  59. debug("spi_xfer: din %p..%08x read\n",
  60. din, tmpdin);
  61. if (din) {
  62. *((u8 *)din) = (u8)tmpdin;
  63. din += 1;
  64. }
  65. if (dout)
  66. dout += 1;
  67. bitlen -= 8;
  68. }
  69. if (isread)
  70. break;
  71. }
  72. if (tm >= KWSPI_TIMEOUT)
  73. printf("*** spi_xfer: Time out during SPI transfer\n");
  74. debug("loopend bitlen %d\n", bitlen);
  75. }
  76. if (flags & SPI_XFER_END)
  77. _spi_cs_deactivate(reg);
  78. return 0;
  79. }
  80. #ifndef CONFIG_DM_SPI
  81. static struct kwspi_registers *spireg =
  82. (struct kwspi_registers *)MVEBU_SPI_BASE;
  83. #ifdef CONFIG_KIRKWOOD
  84. static u32 cs_spi_mpp_back[2];
  85. #endif
  86. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  87. unsigned int max_hz, unsigned int mode)
  88. {
  89. struct spi_slave *slave;
  90. u32 data;
  91. #ifdef CONFIG_KIRKWOOD
  92. static const u32 kwspi_mpp_config[2][2] = {
  93. { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
  94. { MPP7_SPI_SCn, 0 } /* if cs != 0 */
  95. };
  96. #endif
  97. if (!spi_cs_is_valid(bus, cs))
  98. return NULL;
  99. slave = spi_alloc_slave_base(bus, cs);
  100. if (!slave)
  101. return NULL;
  102. writel(KWSPI_SMEMRDY, &spireg->ctrl);
  103. /* calculate spi clock prescaller using max_hz */
  104. data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
  105. data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
  106. data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
  107. /* program spi clock prescaller using max_hz */
  108. writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
  109. debug("data = 0x%08x\n", data);
  110. writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
  111. writel(KWSPI_IRQMASK, &spireg->irq_mask);
  112. #ifdef CONFIG_KIRKWOOD
  113. /* program mpp registers to select SPI_CSn */
  114. kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
  115. #endif
  116. return slave;
  117. }
  118. void spi_free_slave(struct spi_slave *slave)
  119. {
  120. #ifdef CONFIG_KIRKWOOD
  121. kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
  122. #endif
  123. free(slave);
  124. }
  125. __attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
  126. {
  127. return 0;
  128. }
  129. int spi_claim_bus(struct spi_slave *slave)
  130. {
  131. return board_spi_claim_bus(slave);
  132. }
  133. __attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
  134. {
  135. }
  136. void spi_release_bus(struct spi_slave *slave)
  137. {
  138. board_spi_release_bus(slave);
  139. }
  140. #ifndef CONFIG_SPI_CS_IS_VALID
  141. /*
  142. * you can define this function board specific
  143. * define above CONFIG in board specific config file and
  144. * provide the function in board specific src file
  145. */
  146. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  147. {
  148. return bus == 0 && (cs == 0 || cs == 1);
  149. }
  150. #endif
  151. void spi_init(void)
  152. {
  153. }
  154. void spi_cs_activate(struct spi_slave *slave)
  155. {
  156. _spi_cs_activate(spireg);
  157. }
  158. void spi_cs_deactivate(struct spi_slave *slave)
  159. {
  160. _spi_cs_deactivate(spireg);
  161. }
  162. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  163. const void *dout, void *din, unsigned long flags)
  164. {
  165. return _spi_xfer(spireg, bitlen, dout, din, flags);
  166. }
  167. #else
  168. /* Here now the DM part */
  169. struct mvebu_spi_dev {
  170. bool is_errata_50mhz_ac;
  171. };
  172. struct mvebu_spi_platdata {
  173. struct kwspi_registers *spireg;
  174. bool is_errata_50mhz_ac;
  175. };
  176. struct mvebu_spi_priv {
  177. struct kwspi_registers *spireg;
  178. };
  179. static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
  180. {
  181. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  182. struct kwspi_registers *reg = plat->spireg;
  183. u32 data;
  184. /* calculate spi clock prescaller using max_hz */
  185. data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
  186. data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
  187. data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
  188. /* program spi clock prescaler using max_hz */
  189. writel(KWSPI_ADRLEN_3BYTE | data, &reg->cfg);
  190. debug("data = 0x%08x\n", data);
  191. return 0;
  192. }
  193. static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
  194. {
  195. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  196. struct kwspi_registers *reg = plat->spireg;
  197. u32 data;
  198. /*
  199. * Erratum description: (Erratum NO. FE-9144572) The device
  200. * SPI interface supports frequencies of up to 50 MHz.
  201. * However, due to this erratum, when the device core clock is
  202. * 250 MHz and the SPI interfaces is configured for 50MHz SPI
  203. * clock and CPOL=CPHA=1 there might occur data corruption on
  204. * reads from the SPI device.
  205. * Erratum Workaround:
  206. * Work in one of the following configurations:
  207. * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
  208. * Register".
  209. * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
  210. * Register" before setting the interface.
  211. */
  212. data = readl(&reg->timing1);
  213. data &= ~KW_SPI_TMISO_SAMPLE_MASK;
  214. if (CONFIG_SYS_TCLK == 250000000 &&
  215. mode & SPI_CPOL &&
  216. mode & SPI_CPHA)
  217. data |= KW_SPI_TMISO_SAMPLE_2;
  218. else
  219. data |= KW_SPI_TMISO_SAMPLE_1;
  220. writel(data, &reg->timing1);
  221. }
  222. static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
  223. {
  224. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  225. struct kwspi_registers *reg = plat->spireg;
  226. u32 data = readl(&reg->cfg);
  227. data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
  228. if (mode & SPI_CPHA)
  229. data |= KWSPI_CPHA;
  230. if (mode & SPI_CPOL)
  231. data |= KWSPI_CPOL;
  232. if (mode & SPI_LSB_FIRST)
  233. data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
  234. writel(data, &reg->cfg);
  235. if (plat->is_errata_50mhz_ac)
  236. mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
  237. return 0;
  238. }
  239. static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
  240. const void *dout, void *din, unsigned long flags)
  241. {
  242. struct udevice *bus = dev->parent;
  243. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  244. return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
  245. }
  246. __attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
  247. {
  248. return 0;
  249. }
  250. static int mvebu_spi_claim_bus(struct udevice *dev)
  251. {
  252. struct udevice *bus = dev->parent;
  253. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  254. /* Configure the chip-select in the CTRL register */
  255. clrsetbits_le32(&plat->spireg->ctrl,
  256. KWSPI_CS_MASK << KWSPI_CS_SHIFT,
  257. spi_chip_select(dev) << KWSPI_CS_SHIFT);
  258. return mvebu_board_spi_claim_bus(dev);
  259. }
  260. __attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
  261. {
  262. return 0;
  263. }
  264. static int mvebu_spi_release_bus(struct udevice *dev)
  265. {
  266. return mvebu_board_spi_release_bus(dev);
  267. }
  268. static int mvebu_spi_probe(struct udevice *bus)
  269. {
  270. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  271. struct kwspi_registers *reg = plat->spireg;
  272. writel(KWSPI_SMEMRDY, &reg->ctrl);
  273. writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
  274. writel(KWSPI_IRQMASK, &reg->irq_mask);
  275. return 0;
  276. }
  277. static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
  278. {
  279. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  280. const struct mvebu_spi_dev *drvdata =
  281. (struct mvebu_spi_dev *)dev_get_driver_data(bus);
  282. plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
  283. plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
  284. return 0;
  285. }
  286. static const struct dm_spi_ops mvebu_spi_ops = {
  287. .claim_bus = mvebu_spi_claim_bus,
  288. .release_bus = mvebu_spi_release_bus,
  289. .xfer = mvebu_spi_xfer,
  290. .set_speed = mvebu_spi_set_speed,
  291. .set_mode = mvebu_spi_set_mode,
  292. /*
  293. * cs_info is not needed, since we require all chip selects to be
  294. * in the device tree explicitly
  295. */
  296. };
  297. static const struct mvebu_spi_dev armada_spi_dev_data = {
  298. .is_errata_50mhz_ac = false,
  299. };
  300. static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
  301. .is_errata_50mhz_ac = false,
  302. };
  303. static const struct mvebu_spi_dev armada_375_spi_dev_data = {
  304. .is_errata_50mhz_ac = false,
  305. };
  306. static const struct mvebu_spi_dev armada_380_spi_dev_data = {
  307. .is_errata_50mhz_ac = true,
  308. };
  309. static const struct udevice_id mvebu_spi_ids[] = {
  310. {
  311. .compatible = "marvell,orion-spi",
  312. .data = (ulong)&armada_spi_dev_data,
  313. },
  314. {
  315. .compatible = "marvell,armada-375-spi",
  316. .data = (ulong)&armada_375_spi_dev_data
  317. },
  318. {
  319. .compatible = "marvell,armada-380-spi",
  320. .data = (ulong)&armada_380_spi_dev_data
  321. },
  322. {
  323. .compatible = "marvell,armada-xp-spi",
  324. .data = (ulong)&armada_xp_spi_dev_data
  325. },
  326. { }
  327. };
  328. U_BOOT_DRIVER(mvebu_spi) = {
  329. .name = "mvebu_spi",
  330. .id = UCLASS_SPI,
  331. .of_match = mvebu_spi_ids,
  332. .ops = &mvebu_spi_ops,
  333. .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
  334. .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
  335. .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
  336. .probe = mvebu_spi_probe,
  337. };
  338. #endif