fsl_qspi.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale QuadSPI driver.
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. * Copyright (C) 2018 Bootlin
  7. * Copyright (C) 2018 exceet electronics GmbH
  8. * Copyright (C) 2018 Kontron Electronics GmbH
  9. * Copyright 2019-2020 NXP
  10. *
  11. * This driver is a ported version of Linux Freescale QSPI driver taken from
  12. * v5.5-rc1 tag having following information.
  13. *
  14. * Transition to SPI MEM interface:
  15. * Authors:
  16. * Boris Brezillon <bbrezillon@kernel.org>
  17. * Frieder Schrempf <frieder.schrempf@kontron.de>
  18. * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  19. * Suresh Gupta <suresh.gupta@nxp.com>
  20. *
  21. * Based on the original fsl-quadspi.c spi-nor driver.
  22. * Transition to spi-mem in spi-fsl-qspi.c
  23. */
  24. #include <common.h>
  25. #include <asm/io.h>
  26. #include <dm.h>
  27. #include <linux/iopoll.h>
  28. #include <linux/sizes.h>
  29. #include <linux/err.h>
  30. #include <spi.h>
  31. #include <spi-mem.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. /*
  34. * The driver only uses one single LUT entry, that is updated on
  35. * each call of exec_op(). Index 0 is preset at boot with a basic
  36. * read operation, so let's use the last entry (15).
  37. */
  38. #define SEQID_LUT 15
  39. /* Registers used by the driver */
  40. #define QUADSPI_MCR 0x00
  41. #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
  42. #define QUADSPI_MCR_MDIS_MASK BIT(14)
  43. #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
  44. #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
  45. #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
  46. #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
  47. #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
  48. #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
  49. #define QUADSPI_IPCR 0x08
  50. #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
  51. #define QUADSPI_FLSHCR 0x0c
  52. #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
  53. #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
  54. #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
  55. #define QUADSPI_BUF3CR 0x1c
  56. #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
  57. #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
  58. #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
  59. #define QUADSPI_BFGENCR 0x20
  60. #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
  61. #define QUADSPI_BUF0IND 0x30
  62. #define QUADSPI_BUF1IND 0x34
  63. #define QUADSPI_BUF2IND 0x38
  64. #define QUADSPI_SFAR 0x100
  65. #define QUADSPI_SMPR 0x108
  66. #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
  67. #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
  68. #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
  69. #define QUADSPI_SMPR_HSENA_MASK BIT(0)
  70. #define QUADSPI_RBCT 0x110
  71. #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
  72. #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
  73. #define QUADSPI_TBDR 0x154
  74. #define QUADSPI_SR 0x15c
  75. #define QUADSPI_SR_IP_ACC_MASK BIT(1)
  76. #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
  77. #define QUADSPI_FR 0x160
  78. #define QUADSPI_FR_TFF_MASK BIT(0)
  79. #define QUADSPI_RSER 0x164
  80. #define QUADSPI_RSER_TFIE BIT(0)
  81. #define QUADSPI_SPTRCLR 0x16c
  82. #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
  83. #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
  84. #define QUADSPI_SFA1AD 0x180
  85. #define QUADSPI_SFA2AD 0x184
  86. #define QUADSPI_SFB1AD 0x188
  87. #define QUADSPI_SFB2AD 0x18c
  88. #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
  89. #define QUADSPI_LUTKEY 0x300
  90. #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
  91. #define QUADSPI_LCKCR 0x304
  92. #define QUADSPI_LCKER_LOCK BIT(0)
  93. #define QUADSPI_LCKER_UNLOCK BIT(1)
  94. #define QUADSPI_LUT_BASE 0x310
  95. #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  96. #define QUADSPI_LUT_REG(idx) \
  97. (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
  98. /* Instruction set for the LUT register */
  99. #define LUT_STOP 0
  100. #define LUT_CMD 1
  101. #define LUT_ADDR 2
  102. #define LUT_DUMMY 3
  103. #define LUT_MODE 4
  104. #define LUT_MODE2 5
  105. #define LUT_MODE4 6
  106. #define LUT_FSL_READ 7
  107. #define LUT_FSL_WRITE 8
  108. #define LUT_JMP_ON_CS 9
  109. #define LUT_ADDR_DDR 10
  110. #define LUT_MODE_DDR 11
  111. #define LUT_MODE2_DDR 12
  112. #define LUT_MODE4_DDR 13
  113. #define LUT_FSL_READ_DDR 14
  114. #define LUT_FSL_WRITE_DDR 15
  115. #define LUT_DATA_LEARN 16
  116. /*
  117. * The PAD definitions for LUT register.
  118. *
  119. * The pad stands for the number of IO lines [0:3].
  120. * For example, the quad read needs four IO lines,
  121. * so you should use LUT_PAD(4).
  122. */
  123. #define LUT_PAD(x) (fls(x) - 1)
  124. /*
  125. * Macro for constructing the LUT entries with the following
  126. * register layout:
  127. *
  128. * ---------------------------------------------------
  129. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  130. * ---------------------------------------------------
  131. */
  132. #define LUT_DEF(idx, ins, pad, opr) \
  133. ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
  134. /* Controller needs driver to swap endianness */
  135. #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  136. /* Controller needs 4x internal clock */
  137. #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
  138. /*
  139. * TKT253890, the controller needs the driver to fill the txfifo with
  140. * 16 bytes at least to trigger a data transfer, even though the extra
  141. * data won't be transferred.
  142. */
  143. #define QUADSPI_QUIRK_TKT253890 BIT(2)
  144. /* TKT245618, the controller cannot wake up from wait mode */
  145. #define QUADSPI_QUIRK_TKT245618 BIT(3)
  146. /*
  147. * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
  148. * internally. No need to add it when setting SFXXAD and SFAR registers
  149. */
  150. #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
  151. /*
  152. * Controller uses TDH bits in register QUADSPI_FLSHCR.
  153. * They need to be set in accordance with the DDR/SDR mode.
  154. */
  155. #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
  156. struct fsl_qspi_devtype_data {
  157. unsigned int rxfifo;
  158. unsigned int txfifo;
  159. unsigned int ahb_buf_size;
  160. unsigned int quirks;
  161. bool little_endian;
  162. };
  163. static const struct fsl_qspi_devtype_data vybrid_data = {
  164. .rxfifo = SZ_128,
  165. .txfifo = SZ_64,
  166. .ahb_buf_size = SZ_1K,
  167. .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  168. .little_endian = true,
  169. };
  170. static const struct fsl_qspi_devtype_data imx6sx_data = {
  171. .rxfifo = SZ_128,
  172. .txfifo = SZ_512,
  173. .ahb_buf_size = SZ_1K,
  174. .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  175. .little_endian = true,
  176. };
  177. static const struct fsl_qspi_devtype_data imx7d_data = {
  178. .rxfifo = SZ_128,
  179. .txfifo = SZ_512,
  180. .ahb_buf_size = SZ_1K,
  181. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  182. QUADSPI_QUIRK_USE_TDH_SETTING,
  183. .little_endian = true,
  184. };
  185. static const struct fsl_qspi_devtype_data imx6ul_data = {
  186. .rxfifo = SZ_128,
  187. .txfifo = SZ_512,
  188. .ahb_buf_size = SZ_1K,
  189. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  190. QUADSPI_QUIRK_USE_TDH_SETTING,
  191. .little_endian = true,
  192. };
  193. static const struct fsl_qspi_devtype_data ls1021a_data = {
  194. .rxfifo = SZ_128,
  195. .txfifo = SZ_64,
  196. .ahb_buf_size = SZ_1K,
  197. .quirks = 0,
  198. .little_endian = false,
  199. };
  200. static const struct fsl_qspi_devtype_data ls1088a_data = {
  201. .rxfifo = SZ_128,
  202. .txfifo = SZ_128,
  203. .ahb_buf_size = SZ_1K,
  204. .quirks = QUADSPI_QUIRK_TKT253890,
  205. .little_endian = true,
  206. };
  207. static const struct fsl_qspi_devtype_data ls2080a_data = {
  208. .rxfifo = SZ_128,
  209. .txfifo = SZ_64,
  210. .ahb_buf_size = SZ_1K,
  211. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  212. .little_endian = true,
  213. };
  214. struct fsl_qspi {
  215. struct udevice *dev;
  216. void __iomem *iobase;
  217. void __iomem *ahb_addr;
  218. u32 memmap_phy;
  219. const struct fsl_qspi_devtype_data *devtype_data;
  220. int selected;
  221. };
  222. static inline int needs_swap_endian(struct fsl_qspi *q)
  223. {
  224. return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
  225. }
  226. static inline int needs_4x_clock(struct fsl_qspi *q)
  227. {
  228. return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
  229. }
  230. static inline int needs_fill_txfifo(struct fsl_qspi *q)
  231. {
  232. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
  233. }
  234. static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  235. {
  236. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
  237. }
  238. static inline int needs_amba_base_offset(struct fsl_qspi *q)
  239. {
  240. return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
  241. }
  242. static inline int needs_tdh_setting(struct fsl_qspi *q)
  243. {
  244. return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
  245. }
  246. /*
  247. * An IC bug makes it necessary to rearrange the 32-bit data.
  248. * Later chips, such as IMX6SLX, have fixed this bug.
  249. */
  250. static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
  251. {
  252. return needs_swap_endian(q) ? __swab32(a) : a;
  253. }
  254. /*
  255. * R/W functions for big- or little-endian registers:
  256. * The QSPI controller's endianness is independent of
  257. * the CPU core's endianness. So far, although the CPU
  258. * core is little-endian the QSPI controller can use
  259. * big-endian or little-endian.
  260. */
  261. static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
  262. {
  263. if (q->devtype_data->little_endian)
  264. out_le32(addr, val);
  265. else
  266. out_be32(addr, val);
  267. }
  268. static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  269. {
  270. if (q->devtype_data->little_endian)
  271. return in_le32(addr);
  272. return in_be32(addr);
  273. }
  274. static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
  275. {
  276. switch (width) {
  277. case 1:
  278. case 2:
  279. case 4:
  280. return 0;
  281. }
  282. return -ENOTSUPP;
  283. }
  284. static bool fsl_qspi_supports_op(struct spi_slave *slave,
  285. const struct spi_mem_op *op)
  286. {
  287. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  288. int ret;
  289. ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
  290. if (op->addr.nbytes)
  291. ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
  292. if (op->dummy.nbytes)
  293. ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
  294. if (op->data.nbytes)
  295. ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
  296. if (ret)
  297. return false;
  298. /*
  299. * The number of instructions needed for the op, needs
  300. * to fit into a single LUT entry.
  301. */
  302. if (op->addr.nbytes +
  303. (op->dummy.nbytes ? 1 : 0) +
  304. (op->data.nbytes ? 1 : 0) > 6)
  305. return false;
  306. /* Max 64 dummy clock cycles supported */
  307. if (op->dummy.nbytes &&
  308. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  309. return false;
  310. /* Max data length, check controller limits and alignment */
  311. if (op->data.dir == SPI_MEM_DATA_IN &&
  312. (op->data.nbytes > q->devtype_data->ahb_buf_size ||
  313. (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
  314. !IS_ALIGNED(op->data.nbytes, 8))))
  315. return false;
  316. if (op->data.dir == SPI_MEM_DATA_OUT &&
  317. op->data.nbytes > q->devtype_data->txfifo)
  318. return false;
  319. return true;
  320. }
  321. static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
  322. const struct spi_mem_op *op)
  323. {
  324. void __iomem *base = q->iobase;
  325. u32 lutval[4] = {};
  326. int lutidx = 1, i;
  327. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  328. op->cmd.opcode);
  329. /*
  330. * For some unknown reason, using LUT_ADDR doesn't work in some
  331. * cases (at least with only one byte long addresses), so
  332. * let's use LUT_MODE to write the address bytes one by one
  333. */
  334. for (i = 0; i < op->addr.nbytes; i++) {
  335. u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  336. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
  337. LUT_PAD(op->addr.buswidth),
  338. addrbyte);
  339. lutidx++;
  340. }
  341. if (op->dummy.nbytes) {
  342. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  343. LUT_PAD(op->dummy.buswidth),
  344. op->dummy.nbytes * 8 /
  345. op->dummy.buswidth);
  346. lutidx++;
  347. }
  348. if (op->data.nbytes) {
  349. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  350. op->data.dir == SPI_MEM_DATA_IN ?
  351. LUT_FSL_READ : LUT_FSL_WRITE,
  352. LUT_PAD(op->data.buswidth),
  353. 0);
  354. lutidx++;
  355. }
  356. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  357. /* unlock LUT */
  358. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  359. qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
  360. dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  361. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  362. /* fill LUT */
  363. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  364. qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
  365. /* lock LUT */
  366. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  367. qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
  368. }
  369. /*
  370. * If we have changed the content of the flash by writing or erasing, or if we
  371. * read from flash with a different offset into the page buffer, we need to
  372. * invalidate the AHB buffer. If we do not do so, we may read out the wrong
  373. * data. The spec tells us reset the AHB domain and Serial Flash domain at
  374. * the same time.
  375. */
  376. static void fsl_qspi_invalidate(struct fsl_qspi *q)
  377. {
  378. u32 reg;
  379. reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  380. reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
  381. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  382. /*
  383. * The minimum delay : 1 AHB + 2 SFCK clocks.
  384. * Delay 1 us is enough.
  385. */
  386. udelay(1);
  387. reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
  388. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  389. }
  390. static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
  391. {
  392. struct dm_spi_slave_platdata *plat =
  393. dev_get_parent_platdata(slave->dev);
  394. if (q->selected == plat->cs)
  395. return;
  396. q->selected = plat->cs;
  397. fsl_qspi_invalidate(q);
  398. }
  399. static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
  400. {
  401. memcpy_fromio(op->data.buf.in,
  402. q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
  403. op->data.nbytes);
  404. }
  405. static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
  406. const struct spi_mem_op *op)
  407. {
  408. void __iomem *base = q->iobase;
  409. int i;
  410. u32 val;
  411. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  412. memcpy(&val, op->data.buf.out + i, 4);
  413. val = fsl_qspi_endian_xchg(q, val);
  414. qspi_writel(q, val, base + QUADSPI_TBDR);
  415. }
  416. if (i < op->data.nbytes) {
  417. memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
  418. val = fsl_qspi_endian_xchg(q, val);
  419. qspi_writel(q, val, base + QUADSPI_TBDR);
  420. }
  421. if (needs_fill_txfifo(q)) {
  422. for (i = op->data.nbytes; i < 16; i += 4)
  423. qspi_writel(q, 0, base + QUADSPI_TBDR);
  424. }
  425. }
  426. static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
  427. const struct spi_mem_op *op)
  428. {
  429. void __iomem *base = q->iobase;
  430. int i;
  431. u8 *buf = op->data.buf.in;
  432. u32 val;
  433. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  434. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  435. val = fsl_qspi_endian_xchg(q, val);
  436. memcpy(buf + i, &val, 4);
  437. }
  438. if (i < op->data.nbytes) {
  439. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  440. val = fsl_qspi_endian_xchg(q, val);
  441. memcpy(buf + i, &val, op->data.nbytes - i);
  442. }
  443. }
  444. static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
  445. u32 mask, u32 delay_us, u32 timeout_us)
  446. {
  447. u32 reg;
  448. if (!q->devtype_data->little_endian)
  449. mask = (u32)cpu_to_be32(mask);
  450. return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
  451. }
  452. static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
  453. {
  454. void __iomem *base = q->iobase;
  455. int err = 0;
  456. /*
  457. * Always start the sequence at the same index since we update
  458. * the LUT at each exec_op() call. And also specify the DATA
  459. * length, since it's has not been specified in the LUT.
  460. */
  461. qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
  462. base + QUADSPI_IPCR);
  463. /* wait for the controller being ready */
  464. err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
  465. (QUADSPI_SR_IP_ACC_MASK |
  466. QUADSPI_SR_AHB_ACC_MASK),
  467. 10, 1000);
  468. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  469. fsl_qspi_read_rxfifo(q, op);
  470. return err;
  471. }
  472. static int fsl_qspi_exec_op(struct spi_slave *slave,
  473. const struct spi_mem_op *op)
  474. {
  475. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  476. void __iomem *base = q->iobase;
  477. u32 addr_offset = 0;
  478. int err = 0;
  479. /* wait for the controller being ready */
  480. fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
  481. QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
  482. fsl_qspi_select_mem(q, slave);
  483. if (needs_amba_base_offset(q))
  484. addr_offset = q->memmap_phy;
  485. qspi_writel(q,
  486. q->selected * q->devtype_data->ahb_buf_size + addr_offset,
  487. base + QUADSPI_SFAR);
  488. qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
  489. QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
  490. base + QUADSPI_MCR);
  491. qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
  492. base + QUADSPI_SPTRCLR);
  493. fsl_qspi_prepare_lut(q, op);
  494. /*
  495. * If we have large chunks of data, we read them through the AHB bus
  496. * by accessing the mapped memory. In all other cases we use
  497. * IP commands to access the flash.
  498. */
  499. if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
  500. op->data.dir == SPI_MEM_DATA_IN) {
  501. fsl_qspi_read_ahb(q, op);
  502. } else {
  503. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
  504. QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
  505. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  506. fsl_qspi_fill_txfifo(q, op);
  507. err = fsl_qspi_do_op(q, op);
  508. }
  509. /* Invalidate the data in the AHB buffer. */
  510. fsl_qspi_invalidate(q);
  511. return err;
  512. }
  513. static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
  514. struct spi_mem_op *op)
  515. {
  516. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  517. if (op->data.dir == SPI_MEM_DATA_OUT) {
  518. if (op->data.nbytes > q->devtype_data->txfifo)
  519. op->data.nbytes = q->devtype_data->txfifo;
  520. } else {
  521. if (op->data.nbytes > q->devtype_data->ahb_buf_size)
  522. op->data.nbytes = q->devtype_data->ahb_buf_size;
  523. else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
  524. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  525. }
  526. return 0;
  527. }
  528. static int fsl_qspi_default_setup(struct fsl_qspi *q)
  529. {
  530. void __iomem *base = q->iobase;
  531. u32 reg, addr_offset = 0;
  532. /* Reset the module */
  533. qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
  534. base + QUADSPI_MCR);
  535. udelay(1);
  536. /* Disable the module */
  537. qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
  538. base + QUADSPI_MCR);
  539. /*
  540. * Previous boot stages (BootROM, bootloader) might have used DDR
  541. * mode and did not clear the TDH bits. As we currently use SDR mode
  542. * only, clear the TDH bits if necessary.
  543. */
  544. if (needs_tdh_setting(q))
  545. qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
  546. ~QUADSPI_FLSHCR_TDH_MASK,
  547. base + QUADSPI_FLSHCR);
  548. reg = qspi_readl(q, base + QUADSPI_SMPR);
  549. qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
  550. | QUADSPI_SMPR_FSPHS_MASK
  551. | QUADSPI_SMPR_HSENA_MASK
  552. | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
  553. /* We only use the buffer3 for AHB read */
  554. qspi_writel(q, 0, base + QUADSPI_BUF0IND);
  555. qspi_writel(q, 0, base + QUADSPI_BUF1IND);
  556. qspi_writel(q, 0, base + QUADSPI_BUF2IND);
  557. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
  558. q->iobase + QUADSPI_BFGENCR);
  559. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
  560. qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
  561. QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
  562. base + QUADSPI_BUF3CR);
  563. if (needs_amba_base_offset(q))
  564. addr_offset = q->memmap_phy;
  565. /*
  566. * In HW there can be a maximum of four chips on two buses with
  567. * two chip selects on each bus. We use four chip selects in SW
  568. * to differentiate between the four chips.
  569. * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
  570. * SFB2AD accordingly.
  571. */
  572. qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
  573. base + QUADSPI_SFA1AD);
  574. qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
  575. base + QUADSPI_SFA2AD);
  576. qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
  577. base + QUADSPI_SFB1AD);
  578. qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
  579. base + QUADSPI_SFB2AD);
  580. q->selected = -1;
  581. /* Enable the module */
  582. qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
  583. base + QUADSPI_MCR);
  584. return 0;
  585. }
  586. static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
  587. .adjust_op_size = fsl_qspi_adjust_op_size,
  588. .supports_op = fsl_qspi_supports_op,
  589. .exec_op = fsl_qspi_exec_op,
  590. };
  591. static int fsl_qspi_probe(struct udevice *bus)
  592. {
  593. struct dm_spi_bus *dm_bus = bus->uclass_priv;
  594. struct fsl_qspi *q = dev_get_priv(bus);
  595. const void *blob = gd->fdt_blob;
  596. int node = dev_of_offset(bus);
  597. struct fdt_resource res;
  598. int ret;
  599. q->dev = bus;
  600. q->devtype_data = (struct fsl_qspi_devtype_data *)
  601. dev_get_driver_data(bus);
  602. /* find the resources */
  603. ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
  604. &res);
  605. if (ret) {
  606. dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
  607. return -ENOMEM;
  608. }
  609. q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  610. ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  611. "QuadSPI-memory", &res);
  612. if (ret) {
  613. dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
  614. return -ENOMEM;
  615. }
  616. q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  617. q->memmap_phy = res.start;
  618. dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  619. 66000000);
  620. fsl_qspi_default_setup(q);
  621. return 0;
  622. }
  623. static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  624. const void *dout, void *din, unsigned long flags)
  625. {
  626. return 0;
  627. }
  628. static int fsl_qspi_claim_bus(struct udevice *dev)
  629. {
  630. return 0;
  631. }
  632. static int fsl_qspi_release_bus(struct udevice *dev)
  633. {
  634. return 0;
  635. }
  636. static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
  637. {
  638. return 0;
  639. }
  640. static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
  641. {
  642. return 0;
  643. }
  644. static const struct dm_spi_ops fsl_qspi_ops = {
  645. .claim_bus = fsl_qspi_claim_bus,
  646. .release_bus = fsl_qspi_release_bus,
  647. .xfer = fsl_qspi_xfer,
  648. .set_speed = fsl_qspi_set_speed,
  649. .set_mode = fsl_qspi_set_mode,
  650. .mem_ops = &fsl_qspi_mem_ops,
  651. };
  652. static const struct udevice_id fsl_qspi_ids[] = {
  653. { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
  654. { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
  655. { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
  656. { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
  657. { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
  658. { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
  659. { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
  660. { }
  661. };
  662. U_BOOT_DRIVER(fsl_qspi) = {
  663. .name = "fsl_qspi",
  664. .id = UCLASS_SPI,
  665. .of_match = fsl_qspi_ids,
  666. .ops = &fsl_qspi_ops,
  667. .priv_auto_alloc_size = sizeof(struct fsl_qspi),
  668. .probe = fsl_qspi_probe,
  669. };