fsl_dspi.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. * Chao Fu (B44548@freescale.com)
  9. * Haikun Wang (B53464@freescale.com)
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <common.h>
  15. #include <spi.h>
  16. #include <malloc.h>
  17. #include <asm/io.h>
  18. #include <fdtdec.h>
  19. #ifndef CONFIG_M68K
  20. #include <asm/arch/clock.h>
  21. #endif
  22. #include <fsl_dspi.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* fsl_dspi_platdata flags */
  25. #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
  26. /* idle data value */
  27. #define DSPI_IDLE_VAL 0x0
  28. /* max chipselect signals number */
  29. #define FSL_DSPI_MAX_CHIPSELECT 6
  30. /* default SCK frequency, unit: HZ */
  31. #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
  32. /* tx/rx data wait timeout value, unit: us */
  33. #define DSPI_TXRX_WAIT_TIMEOUT 1000000
  34. /* CTAR register pre-configure value */
  35. #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
  36. DSPI_CTAR_PCSSCK_1CLK | \
  37. DSPI_CTAR_PASC(0) | \
  38. DSPI_CTAR_PDT(0) | \
  39. DSPI_CTAR_CSSCK(0) | \
  40. DSPI_CTAR_ASC(0) | \
  41. DSPI_CTAR_DT(0))
  42. /* CTAR register pre-configure mask */
  43. #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
  44. DSPI_CTAR_PCSSCK(3) | \
  45. DSPI_CTAR_PASC(3) | \
  46. DSPI_CTAR_PDT(3) | \
  47. DSPI_CTAR_CSSCK(15) | \
  48. DSPI_CTAR_ASC(15) | \
  49. DSPI_CTAR_DT(15))
  50. /**
  51. * struct fsl_dspi_platdata - platform data for Freescale DSPI
  52. *
  53. * @flags: Flags for DSPI DSPI_FLAG_...
  54. * @speed_hz: Default SCK frequency
  55. * @num_chipselect: Number of DSPI chipselect signals
  56. * @regs_addr: Base address of DSPI registers
  57. */
  58. struct fsl_dspi_platdata {
  59. uint flags;
  60. uint speed_hz;
  61. uint num_chipselect;
  62. fdt_addr_t regs_addr;
  63. };
  64. /**
  65. * struct fsl_dspi_priv - private data for Freescale DSPI
  66. *
  67. * @flags: Flags for DSPI DSPI_FLAG_...
  68. * @mode: SPI mode to use for slave device (see SPI mode flags)
  69. * @mcr_val: MCR register configure value
  70. * @bus_clk: DSPI input clk frequency
  71. * @speed_hz: Default SCK frequency
  72. * @charbit: How many bits in every transfer
  73. * @num_chipselect: Number of DSPI chipselect signals
  74. * @ctar_val: CTAR register configure value of per chipselect slave device
  75. * @regs: Point to DSPI register structure for I/O access
  76. */
  77. struct fsl_dspi_priv {
  78. uint flags;
  79. uint mode;
  80. uint mcr_val;
  81. uint bus_clk;
  82. uint speed_hz;
  83. uint charbit;
  84. uint num_chipselect;
  85. uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
  86. struct dspi *regs;
  87. };
  88. #ifndef CONFIG_DM_SPI
  89. struct fsl_dspi {
  90. struct spi_slave slave;
  91. struct fsl_dspi_priv priv;
  92. };
  93. #endif
  94. __weak void cpu_dspi_port_conf(void)
  95. {
  96. }
  97. __weak int cpu_dspi_claim_bus(uint bus, uint cs)
  98. {
  99. return 0;
  100. }
  101. __weak void cpu_dspi_release_bus(uint bus, uint cs)
  102. {
  103. }
  104. static uint dspi_read32(uint flags, uint *addr)
  105. {
  106. return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  107. in_be32(addr) : in_le32(addr);
  108. }
  109. static void dspi_write32(uint flags, uint *addr, uint val)
  110. {
  111. flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  112. out_be32(addr, val) : out_le32(addr, val);
  113. }
  114. static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
  115. {
  116. uint mcr_val;
  117. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  118. if (halt)
  119. mcr_val |= DSPI_MCR_HALT;
  120. else
  121. mcr_val &= ~DSPI_MCR_HALT;
  122. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  123. }
  124. static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
  125. {
  126. /* halt DSPI module */
  127. dspi_halt(priv, 1);
  128. dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
  129. /* resume module */
  130. dspi_halt(priv, 0);
  131. priv->mcr_val = cfg_val;
  132. }
  133. static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
  134. uint cs, uint state)
  135. {
  136. uint mcr_val;
  137. dspi_halt(priv, 1);
  138. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  139. if (state & SPI_CS_HIGH)
  140. /* CSx inactive state is low */
  141. mcr_val &= ~DSPI_MCR_PCSIS(cs);
  142. else
  143. /* CSx inactive state is high */
  144. mcr_val |= DSPI_MCR_PCSIS(cs);
  145. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  146. dspi_halt(priv, 0);
  147. }
  148. static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
  149. uint cs, uint mode)
  150. {
  151. uint bus_setup;
  152. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  153. bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
  154. bus_setup |= priv->ctar_val[cs];
  155. bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
  156. if (mode & SPI_CPOL)
  157. bus_setup |= DSPI_CTAR_CPOL;
  158. if (mode & SPI_CPHA)
  159. bus_setup |= DSPI_CTAR_CPHA;
  160. if (mode & SPI_LSB_FIRST)
  161. bus_setup |= DSPI_CTAR_LSBFE;
  162. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  163. priv->charbit =
  164. ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
  165. DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
  166. return 0;
  167. }
  168. static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
  169. {
  170. uint mcr_val;
  171. dspi_halt(priv, 1);
  172. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  173. /* flush RX and TX FIFO */
  174. mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  175. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  176. dspi_halt(priv, 0);
  177. }
  178. static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
  179. {
  180. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  181. /* wait for empty entries in TXFIFO or timeout */
  182. while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
  183. timeout--)
  184. udelay(1);
  185. if (timeout >= 0)
  186. dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
  187. else
  188. debug("dspi_tx: waiting timeout!\n");
  189. }
  190. static u16 dspi_rx(struct fsl_dspi_priv *priv)
  191. {
  192. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  193. /* wait for valid entries in RXFIFO or timeout */
  194. while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
  195. timeout--)
  196. udelay(1);
  197. if (timeout >= 0)
  198. return (u16)DSPI_RFR_RXDATA(
  199. dspi_read32(priv->flags, &priv->regs->rfr));
  200. else {
  201. debug("dspi_rx: waiting timeout!\n");
  202. return (u16)(~0);
  203. }
  204. }
  205. static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
  206. const void *dout, void *din, unsigned long flags)
  207. {
  208. u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
  209. u8 *spi_rd = NULL, *spi_wr = NULL;
  210. static u32 ctrl;
  211. uint len = bitlen >> 3;
  212. if (priv->charbit == 16) {
  213. bitlen >>= 1;
  214. spi_wr16 = (u16 *)dout;
  215. spi_rd16 = (u16 *)din;
  216. } else {
  217. spi_wr = (u8 *)dout;
  218. spi_rd = (u8 *)din;
  219. }
  220. if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
  221. ctrl |= DSPI_TFR_CONT;
  222. ctrl = ctrl & DSPI_TFR_CONT;
  223. ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
  224. if (len > 1) {
  225. int tmp_len = len - 1;
  226. while (tmp_len--) {
  227. if ((dout != NULL) && (din != NULL)) {
  228. if (priv->charbit == 16) {
  229. dspi_tx(priv, ctrl, *spi_wr16++);
  230. *spi_rd16++ = dspi_rx(priv);
  231. }
  232. else {
  233. dspi_tx(priv, ctrl, *spi_wr++);
  234. *spi_rd++ = dspi_rx(priv);
  235. }
  236. }
  237. else if (dout != NULL) {
  238. if (priv->charbit == 16)
  239. dspi_tx(priv, ctrl, *spi_wr16++);
  240. else
  241. dspi_tx(priv, ctrl, *spi_wr++);
  242. dspi_rx(priv);
  243. }
  244. else if (din != NULL) {
  245. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  246. if (priv->charbit == 16)
  247. *spi_rd16++ = dspi_rx(priv);
  248. else
  249. *spi_rd++ = dspi_rx(priv);
  250. }
  251. }
  252. len = 1; /* remaining byte */
  253. }
  254. if ((flags & SPI_XFER_END) == SPI_XFER_END)
  255. ctrl &= ~DSPI_TFR_CONT;
  256. if (len) {
  257. if ((dout != NULL) && (din != NULL)) {
  258. if (priv->charbit == 16) {
  259. dspi_tx(priv, ctrl, *spi_wr16++);
  260. *spi_rd16++ = dspi_rx(priv);
  261. }
  262. else {
  263. dspi_tx(priv, ctrl, *spi_wr++);
  264. *spi_rd++ = dspi_rx(priv);
  265. }
  266. }
  267. else if (dout != NULL) {
  268. if (priv->charbit == 16)
  269. dspi_tx(priv, ctrl, *spi_wr16);
  270. else
  271. dspi_tx(priv, ctrl, *spi_wr);
  272. dspi_rx(priv);
  273. }
  274. else if (din != NULL) {
  275. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  276. if (priv->charbit == 16)
  277. *spi_rd16 = dspi_rx(priv);
  278. else
  279. *spi_rd = dspi_rx(priv);
  280. }
  281. } else {
  282. /* dummy read */
  283. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  284. dspi_rx(priv);
  285. }
  286. return 0;
  287. }
  288. /**
  289. * Calculate the divide value between input clk frequency and expected SCK frequency
  290. * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
  291. * Dbr: use default value 0
  292. *
  293. * @pbr: return Baud Rate Prescaler value
  294. * @br: return Baud Rate Scaler value
  295. * @speed_hz: expected SCK frequency
  296. * @clkrate: input clk frequency
  297. */
  298. static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
  299. int speed_hz, uint clkrate)
  300. {
  301. /* Valid baud rate pre-scaler values */
  302. int pbr_tbl[4] = {2, 3, 5, 7};
  303. int brs[16] = {2, 4, 6, 8,
  304. 16, 32, 64, 128,
  305. 256, 512, 1024, 2048,
  306. 4096, 8192, 16384, 32768};
  307. int temp, i = 0, j = 0;
  308. temp = clkrate / speed_hz;
  309. for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
  310. for (j = 0; j < ARRAY_SIZE(brs); j++) {
  311. if (pbr_tbl[i] * brs[j] >= temp) {
  312. *pbr = i;
  313. *br = j;
  314. return 0;
  315. }
  316. }
  317. debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
  318. debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
  319. *pbr = ARRAY_SIZE(pbr_tbl) - 1;
  320. *br = ARRAY_SIZE(brs) - 1;
  321. return -EINVAL;
  322. }
  323. static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
  324. {
  325. int ret;
  326. uint bus_setup;
  327. int best_i, best_j, bus_clk;
  328. bus_clk = priv->bus_clk;
  329. debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
  330. speed, bus_clk);
  331. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  332. bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
  333. ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  334. if (ret) {
  335. speed = priv->speed_hz;
  336. debug("DSPI set_speed use default SCK rate %u.\n", speed);
  337. fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  338. }
  339. bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
  340. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  341. priv->speed_hz = speed;
  342. return 0;
  343. }
  344. #ifndef CONFIG_DM_SPI
  345. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  346. {
  347. if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
  348. return 1;
  349. else
  350. return 0;
  351. }
  352. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  353. unsigned int max_hz, unsigned int mode)
  354. {
  355. struct fsl_dspi *dspi;
  356. uint mcr_cfg_val;
  357. dspi = spi_alloc_slave(struct fsl_dspi, bus, cs);
  358. if (!dspi)
  359. return NULL;
  360. cpu_dspi_port_conf();
  361. #ifdef CONFIG_SYS_FSL_DSPI_BE
  362. dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
  363. #endif
  364. dspi->priv.regs = (struct dspi *)MMAP_DSPI;
  365. #ifdef CONFIG_M68K
  366. dspi->priv.bus_clk = gd->bus_clk;
  367. #else
  368. dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK);
  369. #endif
  370. dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ;
  371. /* default: all CS signals inactive state is high */
  372. mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  373. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  374. fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val);
  375. for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++)
  376. dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE;
  377. #ifdef CONFIG_SYS_DSPI_CTAR0
  378. if (FSL_DSPI_MAX_CHIPSELECT > 0)
  379. dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0;
  380. #endif
  381. #ifdef CONFIG_SYS_DSPI_CTAR1
  382. if (FSL_DSPI_MAX_CHIPSELECT > 1)
  383. dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1;
  384. #endif
  385. #ifdef CONFIG_SYS_DSPI_CTAR2
  386. if (FSL_DSPI_MAX_CHIPSELECT > 2)
  387. dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2;
  388. #endif
  389. #ifdef CONFIG_SYS_DSPI_CTAR3
  390. if (FSL_DSPI_MAX_CHIPSELECT > 3)
  391. dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3;
  392. #endif
  393. #ifdef CONFIG_SYS_DSPI_CTAR4
  394. if (FSL_DSPI_MAX_CHIPSELECT > 4)
  395. dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4;
  396. #endif
  397. #ifdef CONFIG_SYS_DSPI_CTAR5
  398. if (FSL_DSPI_MAX_CHIPSELECT > 5)
  399. dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5;
  400. #endif
  401. #ifdef CONFIG_SYS_DSPI_CTAR6
  402. if (FSL_DSPI_MAX_CHIPSELECT > 6)
  403. dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6;
  404. #endif
  405. #ifdef CONFIG_SYS_DSPI_CTAR7
  406. if (FSL_DSPI_MAX_CHIPSELECT > 7)
  407. dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7;
  408. #endif
  409. fsl_dspi_cfg_speed(&dspi->priv, max_hz);
  410. /* configure transfer mode */
  411. fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode);
  412. /* configure active state of CSX */
  413. fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode);
  414. return &dspi->slave;
  415. }
  416. void spi_free_slave(struct spi_slave *slave)
  417. {
  418. free(slave);
  419. }
  420. int spi_claim_bus(struct spi_slave *slave)
  421. {
  422. uint sr_val;
  423. struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
  424. cpu_dspi_claim_bus(slave->bus, slave->cs);
  425. fsl_dspi_clr_fifo(&dspi->priv);
  426. /* check module TX and RX status */
  427. sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr);
  428. if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
  429. debug("DSPI RX/TX not ready!\n");
  430. return -EIO;
  431. }
  432. return 0;
  433. }
  434. void spi_release_bus(struct spi_slave *slave)
  435. {
  436. struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
  437. dspi_halt(&dspi->priv, 1);
  438. cpu_dspi_release_bus(slave->bus.slave->cs);
  439. }
  440. int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  441. void *din, unsigned long flags)
  442. {
  443. struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
  444. return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags);
  445. }
  446. #else
  447. static int fsl_dspi_child_pre_probe(struct udevice *dev)
  448. {
  449. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  450. struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
  451. if (slave_plat->cs >= priv->num_chipselect) {
  452. debug("DSPI invalid chipselect number %d(max %d)!\n",
  453. slave_plat->cs, priv->num_chipselect - 1);
  454. return -EINVAL;
  455. }
  456. priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
  457. debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
  458. slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
  459. return 0;
  460. }
  461. static int fsl_dspi_probe(struct udevice *bus)
  462. {
  463. struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
  464. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  465. struct dm_spi_bus *dm_spi_bus;
  466. uint mcr_cfg_val;
  467. dm_spi_bus = bus->uclass_priv;
  468. /* cpu speical pin muxing configure */
  469. cpu_dspi_port_conf();
  470. /* get input clk frequency */
  471. priv->regs = (struct dspi *)plat->regs_addr;
  472. priv->flags = plat->flags;
  473. #ifdef CONFIG_M68K
  474. priv->bus_clk = gd->bus_clk;
  475. #else
  476. priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
  477. #endif
  478. priv->num_chipselect = plat->num_chipselect;
  479. priv->speed_hz = plat->speed_hz;
  480. /* frame data length in bits, default 8bits */
  481. priv->charbit = 8;
  482. dm_spi_bus->max_hz = plat->speed_hz;
  483. /* default: all CS signals inactive state is high */
  484. mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  485. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  486. fsl_dspi_init_mcr(priv, mcr_cfg_val);
  487. debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
  488. return 0;
  489. }
  490. static int fsl_dspi_claim_bus(struct udevice *dev)
  491. {
  492. uint sr_val;
  493. struct fsl_dspi_priv *priv;
  494. struct udevice *bus = dev->parent;
  495. struct dm_spi_slave_platdata *slave_plat =
  496. dev_get_parent_platdata(dev);
  497. priv = dev_get_priv(bus);
  498. /* processor special preparation work */
  499. cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
  500. /* configure transfer mode */
  501. fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
  502. /* configure active state of CSX */
  503. fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
  504. priv->mode);
  505. fsl_dspi_clr_fifo(priv);
  506. /* check module TX and RX status */
  507. sr_val = dspi_read32(priv->flags, &priv->regs->sr);
  508. if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
  509. debug("DSPI RX/TX not ready!\n");
  510. return -EIO;
  511. }
  512. return 0;
  513. }
  514. static int fsl_dspi_release_bus(struct udevice *dev)
  515. {
  516. struct udevice *bus = dev->parent;
  517. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  518. struct dm_spi_slave_platdata *slave_plat =
  519. dev_get_parent_platdata(dev);
  520. /* halt module */
  521. dspi_halt(priv, 1);
  522. /* processor special release work */
  523. cpu_dspi_release_bus(bus->seq, slave_plat->cs);
  524. return 0;
  525. }
  526. /**
  527. * This function doesn't do anything except help with debugging
  528. */
  529. static int fsl_dspi_bind(struct udevice *bus)
  530. {
  531. debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq);
  532. return 0;
  533. }
  534. static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
  535. {
  536. fdt_addr_t addr;
  537. struct fsl_dspi_platdata *plat = bus->platdata;
  538. const void *blob = gd->fdt_blob;
  539. int node = dev_of_offset(bus);
  540. if (fdtdec_get_bool(blob, node, "big-endian"))
  541. plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
  542. plat->num_chipselect =
  543. fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
  544. addr = devfdt_get_addr(bus);
  545. if (addr == FDT_ADDR_T_NONE) {
  546. debug("DSPI: Can't get base address or size\n");
  547. return -ENOMEM;
  548. }
  549. plat->regs_addr = addr;
  550. plat->speed_hz = fdtdec_get_int(blob,
  551. node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
  552. debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
  553. &plat->regs_addr, plat->speed_hz,
  554. plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
  555. plat->num_chipselect);
  556. return 0;
  557. }
  558. static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
  559. const void *dout, void *din, unsigned long flags)
  560. {
  561. struct fsl_dspi_priv *priv;
  562. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  563. struct udevice *bus;
  564. bus = dev->parent;
  565. priv = dev_get_priv(bus);
  566. return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
  567. }
  568. static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
  569. {
  570. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  571. return fsl_dspi_cfg_speed(priv, speed);
  572. }
  573. static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
  574. {
  575. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  576. debug("DSPI set_mode: mode 0x%x.\n", mode);
  577. /*
  578. * We store some chipselect special configure value in priv->ctar_val,
  579. * and we can't get the correct chipselect number here,
  580. * so just store mode value.
  581. * Do really configuration when claim_bus.
  582. */
  583. priv->mode = mode;
  584. return 0;
  585. }
  586. static const struct dm_spi_ops fsl_dspi_ops = {
  587. .claim_bus = fsl_dspi_claim_bus,
  588. .release_bus = fsl_dspi_release_bus,
  589. .xfer = fsl_dspi_xfer,
  590. .set_speed = fsl_dspi_set_speed,
  591. .set_mode = fsl_dspi_set_mode,
  592. };
  593. static const struct udevice_id fsl_dspi_ids[] = {
  594. { .compatible = "fsl,vf610-dspi" },
  595. { }
  596. };
  597. U_BOOT_DRIVER(fsl_dspi) = {
  598. .name = "fsl_dspi",
  599. .id = UCLASS_SPI,
  600. .of_match = fsl_dspi_ids,
  601. .ops = &fsl_dspi_ops,
  602. .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
  603. .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
  604. .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
  605. .probe = fsl_dspi_probe,
  606. .child_pre_probe = fsl_dspi_child_pre_probe,
  607. .bind = fsl_dspi_bind,
  608. };
  609. #endif