cf_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. *
  10. * Support for DM and DT, non-DM code removed.
  11. * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
  12. *
  13. * TODO: fsl_dspi.c should work as a driver for the DSPI module.
  14. */
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <dm/platform_data/spi_coldfire.h>
  18. #include <spi.h>
  19. #include <malloc.h>
  20. #include <asm/coldfire/dspi.h>
  21. #include <asm/io.h>
  22. struct coldfire_spi_priv {
  23. struct dspi *regs;
  24. uint baudrate;
  25. int mode;
  26. int charbit;
  27. };
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #ifndef CONFIG_SPI_IDLE_VAL
  30. #if defined(CONFIG_SPI_MMC)
  31. #define CONFIG_SPI_IDLE_VAL 0xFFFF
  32. #else
  33. #define CONFIG_SPI_IDLE_VAL 0x0
  34. #endif
  35. #endif
  36. /*
  37. * DSPI specific mode
  38. *
  39. * bit 31 - 28: Transfer size 3 to 16 bits
  40. * 27 - 26: PCS to SCK delay prescaler
  41. * 25 - 24: After SCK delay prescaler
  42. * 23 - 22: Delay after transfer prescaler
  43. * 21 : Allow overwrite for bit 31-22 and bit 20-8
  44. * 20 : Double baud rate
  45. * 19 - 16: PCS to SCK delay scaler
  46. * 15 - 12: After SCK delay scaler
  47. * 11 - 8: Delay after transfer scaler
  48. * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
  49. */
  50. #define SPI_MODE_MOD 0x00200000
  51. #define SPI_MODE_DBLRATE 0x00100000
  52. #define SPI_MODE_XFER_SZ_MASK 0xf0000000
  53. #define SPI_MODE_DLY_PRE_MASK 0x0fc00000
  54. #define SPI_MODE_DLY_SCA_MASK 0x000fff00
  55. #define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
  56. #define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
  57. #define MCF_DSPI_MAX_CTAR_REGS 8
  58. /* Default values */
  59. #define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
  60. #define MCF_DSPI_DEFAULT_MAX_CS 4
  61. #define MCF_DSPI_DEFAULT_MODE 0
  62. #define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
  63. DSPI_CTAR_PCSSCK_1CLK | \
  64. DSPI_CTAR_PASC(0) | \
  65. DSPI_CTAR_PDT(0) | \
  66. DSPI_CTAR_CSSCK(0) | \
  67. DSPI_CTAR_ASC(0) | \
  68. DSPI_CTAR_DT(1) | \
  69. DSPI_CTAR_BR(6))
  70. #define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
  71. DSPI_CTAR_PCSSCK(3) | \
  72. DSPI_CTAR_PASC_7CLK | \
  73. DSPI_CTAR_PDT(3) | \
  74. DSPI_CTAR_CSSCK(0x0f) | \
  75. DSPI_CTAR_ASC(0x0f) | \
  76. DSPI_CTAR_DT(0x0f))
  77. #define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
  78. static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
  79. u32 ctrl, u16 data)
  80. {
  81. /*
  82. * Need to check fifo level here
  83. */
  84. while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
  85. ;
  86. writel(ctrl | data, &cfspi->regs->tfr);
  87. }
  88. static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
  89. {
  90. while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
  91. ;
  92. return readw(&cfspi->regs->rfr);
  93. }
  94. static int coldfire_spi_claim_bus(struct udevice *dev)
  95. {
  96. struct udevice *bus = dev->parent;
  97. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  98. struct dspi *dspi = cfspi->regs;
  99. struct dm_spi_slave_platdata *slave_plat =
  100. dev_get_parent_platdata(dev);
  101. if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
  102. return -1;
  103. /* Clear FIFO and resume transfer */
  104. clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  105. dspi_chip_select(slave_plat->cs);
  106. return 0;
  107. }
  108. static int coldfire_spi_release_bus(struct udevice *dev)
  109. {
  110. struct udevice *bus = dev->parent;
  111. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  112. struct dspi *dspi = cfspi->regs;
  113. struct dm_spi_slave_platdata *slave_plat =
  114. dev_get_parent_platdata(dev);
  115. /* Clear FIFO */
  116. clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  117. dspi_chip_unselect(slave_plat->cs);
  118. return 0;
  119. }
  120. static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
  121. const void *dout, void *din,
  122. unsigned long flags)
  123. {
  124. struct udevice *bus = dev_get_parent(dev);
  125. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  126. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  127. u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
  128. u8 *spi_rd = NULL, *spi_wr = NULL;
  129. static u32 ctrl;
  130. uint len = bitlen >> 3;
  131. if (cfspi->charbit == 16) {
  132. bitlen >>= 1;
  133. spi_wr16 = (u16 *)dout;
  134. spi_rd16 = (u16 *)din;
  135. } else {
  136. spi_wr = (u8 *)dout;
  137. spi_rd = (u8 *)din;
  138. }
  139. if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
  140. ctrl |= DSPI_TFR_CONT;
  141. ctrl = setup_ctrl(ctrl, slave_plat->cs);
  142. if (len > 1) {
  143. int tmp_len = len - 1;
  144. while (tmp_len--) {
  145. if (dout) {
  146. if (cfspi->charbit == 16)
  147. cfspi_tx(cfspi, ctrl, *spi_wr16++);
  148. else
  149. cfspi_tx(cfspi, ctrl, *spi_wr++);
  150. cfspi_rx(cfspi);
  151. }
  152. if (din) {
  153. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  154. if (cfspi->charbit == 16)
  155. *spi_rd16++ = cfspi_rx(cfspi);
  156. else
  157. *spi_rd++ = cfspi_rx(cfspi);
  158. }
  159. }
  160. len = 1; /* remaining byte */
  161. }
  162. if (flags & SPI_XFER_END)
  163. ctrl &= ~DSPI_TFR_CONT;
  164. if (len) {
  165. if (dout) {
  166. if (cfspi->charbit == 16)
  167. cfspi_tx(cfspi, ctrl, *spi_wr16);
  168. else
  169. cfspi_tx(cfspi, ctrl, *spi_wr);
  170. cfspi_rx(cfspi);
  171. }
  172. if (din) {
  173. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  174. if (cfspi->charbit == 16)
  175. *spi_rd16 = cfspi_rx(cfspi);
  176. else
  177. *spi_rd = cfspi_rx(cfspi);
  178. }
  179. } else {
  180. /* dummy read */
  181. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  182. cfspi_rx(cfspi);
  183. }
  184. return 0;
  185. }
  186. static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
  187. {
  188. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  189. struct dspi *dspi = cfspi->regs;
  190. int prescaler[] = { 2, 3, 5, 7 };
  191. int scaler[] = {
  192. 2, 4, 6, 8,
  193. 16, 32, 64, 128,
  194. 256, 512, 1024, 2048,
  195. 4096, 8192, 16384, 32768
  196. };
  197. int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
  198. int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
  199. u32 bus_setup;
  200. cfspi->baudrate = max_hz;
  201. /* Read current setup */
  202. bus_setup = readl(&dspi->ctar[bus->seq]);
  203. tmp = (prescaler[3] * scaler[15]);
  204. /* Maximum and minimum baudrate it can handle */
  205. if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
  206. (cfspi->baudrate < (gd->bus_clk / tmp))) {
  207. printf("Exceed baudrate limitation: Max %d - Min %d\n",
  208. (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
  209. return -1;
  210. }
  211. /* Activate Double Baud when it exceed 1/4 the bus clk */
  212. if ((bus_setup & DSPI_CTAR_DBR) ||
  213. (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
  214. bus_setup |= DSPI_CTAR_DBR;
  215. dbr = 1;
  216. }
  217. /* Overwrite default value set in platform configuration file */
  218. if (cfspi->mode & SPI_MODE_MOD) {
  219. /*
  220. * Check to see if it is enabled by default in platform
  221. * config, or manual setting passed by mode parameter
  222. */
  223. if (cfspi->mode & SPI_MODE_DBLRATE) {
  224. bus_setup |= DSPI_CTAR_DBR;
  225. dbr = 1;
  226. }
  227. }
  228. pbrcnt = sizeof(prescaler) / sizeof(int);
  229. brcnt = sizeof(scaler) / sizeof(int);
  230. /* baudrate calculation - to closer value, may not be exact match */
  231. for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
  232. baud_speed = gd->bus_clk / prescaler[i];
  233. for (j = 0; j < brcnt; j++) {
  234. tmp = (baud_speed / scaler[j]) * (1 + dbr);
  235. if (tmp > cfspi->baudrate)
  236. diff = tmp - cfspi->baudrate;
  237. else
  238. diff = cfspi->baudrate - tmp;
  239. if (diff < bestmatch) {
  240. bestmatch = diff;
  241. best_i = i;
  242. best_j = j;
  243. }
  244. }
  245. }
  246. bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
  247. bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
  248. writel(bus_setup, &dspi->ctar[bus->seq]);
  249. return 0;
  250. }
  251. static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
  252. {
  253. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  254. struct dspi *dspi = cfspi->regs;
  255. u32 bus_setup = 0;
  256. cfspi->mode = mode;
  257. if (cfspi->mode & SPI_CPOL)
  258. bus_setup |= DSPI_CTAR_CPOL;
  259. if (cfspi->mode & SPI_CPHA)
  260. bus_setup |= DSPI_CTAR_CPHA;
  261. if (cfspi->mode & SPI_LSB_FIRST)
  262. bus_setup |= DSPI_CTAR_LSBFE;
  263. /* Overwrite default value set in platform configuration file */
  264. if (cfspi->mode & SPI_MODE_MOD) {
  265. if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
  266. bus_setup |=
  267. readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
  268. else
  269. bus_setup |=
  270. ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
  271. /* PSCSCK, PASC, PDT */
  272. bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
  273. /* CSSCK, ASC, DT */
  274. bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
  275. } else {
  276. bus_setup |=
  277. (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
  278. }
  279. cfspi->charbit =
  280. ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
  281. MCF_FRM_SZ_16BIT) ? 16 : 8;
  282. setbits_be32(&dspi->ctar[bus->seq], bus_setup);
  283. return 0;
  284. }
  285. static int coldfire_spi_probe(struct udevice *bus)
  286. {
  287. struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
  288. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  289. struct dspi *dspi = cfspi->regs;
  290. int i;
  291. cfspi->regs = (struct dspi *)plat->regs_addr;
  292. cfspi->baudrate = plat->speed_hz;
  293. cfspi->mode = plat->mode;
  294. for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
  295. unsigned int ctar = 0;
  296. if (plat->ctar[i][0] == 0)
  297. break;
  298. ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
  299. DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
  300. DSPI_CTAR_PASC(plat->ctar[i][2]) |
  301. DSPI_CTAR_PDT(plat->ctar[i][3]) |
  302. DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
  303. DSPI_CTAR_ASC(plat->ctar[i][5]) |
  304. DSPI_CTAR_DT(plat->ctar[i][6]) |
  305. DSPI_CTAR_BR(plat->ctar[i][7]);
  306. writel(ctar, &cfspi->regs->ctar[i]);
  307. }
  308. /* Default CTARs */
  309. for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
  310. writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
  311. dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
  312. DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
  313. DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
  314. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  315. return 0;
  316. }
  317. void spi_init(void)
  318. {
  319. }
  320. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  321. static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
  322. {
  323. fdt_addr_t addr;
  324. struct coldfire_spi_platdata *plat = bus->platdata;
  325. const void *blob = gd->fdt_blob;
  326. int node = dev_of_offset(bus);
  327. int *ctar, len;
  328. addr = devfdt_get_addr(bus);
  329. if (addr == FDT_ADDR_T_NONE)
  330. return -ENOMEM;
  331. plat->regs_addr = addr;
  332. plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
  333. MCF_DSPI_DEFAULT_MAX_CS);
  334. plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  335. MCF_DSPI_DEFAULT_SCK_FREQ);
  336. plat->mode = fdtdec_get_int(blob, node, "spi-mode",
  337. MCF_DSPI_DEFAULT_MODE);
  338. memset(plat->ctar, 0, sizeof(plat->ctar));
  339. ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
  340. if (ctar && len) {
  341. int i, q, ctar_regs;
  342. ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
  343. if (ctar_regs > MAX_CTAR_REGS)
  344. ctar_regs = MAX_CTAR_REGS;
  345. for (i = 0; i < ctar_regs; i++) {
  346. for (q = 0; q < MAX_CTAR_FIELDS; q++)
  347. plat->ctar[i][q] = *ctar++;
  348. }
  349. }
  350. debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
  351. (void *)plat->regs_addr,
  352. plat->speed_hz, plat->num_cs, plat->mode);
  353. return 0;
  354. }
  355. static const struct udevice_id coldfire_spi_ids[] = {
  356. { .compatible = "fsl,mcf-dspi" },
  357. { }
  358. };
  359. #endif
  360. static const struct dm_spi_ops coldfire_spi_ops = {
  361. .claim_bus = coldfire_spi_claim_bus,
  362. .release_bus = coldfire_spi_release_bus,
  363. .xfer = coldfire_spi_xfer,
  364. .set_speed = coldfire_spi_set_speed,
  365. .set_mode = coldfire_spi_set_mode,
  366. };
  367. U_BOOT_DRIVER(coldfire_spi) = {
  368. .name = "spi_coldfire",
  369. .id = UCLASS_SPI,
  370. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  371. .of_match = coldfire_spi_ids,
  372. .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
  373. .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
  374. #endif
  375. .probe = coldfire_spi_probe,
  376. .ops = &coldfire_spi_ops,
  377. .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
  378. };