cadence_qspi.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012
  4. * Altera Corporation <www.altera.com>
  5. */
  6. #ifndef __CADENCE_QSPI_H__
  7. #define __CADENCE_QSPI_H__
  8. #include <reset.h>
  9. #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
  10. #define CQSPI_NO_DECODER_MAX_CS 4
  11. #define CQSPI_DECODER_MAX_CS 16
  12. #define CQSPI_READ_CAPTURE_MAX_DELAY 16
  13. struct cadence_spi_platdata {
  14. unsigned int ref_clk_hz;
  15. unsigned int max_hz;
  16. void *regbase;
  17. void *ahbbase;
  18. bool is_decoded_cs;
  19. u32 fifo_depth;
  20. u32 fifo_width;
  21. u32 trigger_address;
  22. fdt_addr_t ahbsize;
  23. bool use_dac_mode;
  24. /* Flash parameters */
  25. u32 page_size;
  26. u32 block_size;
  27. u32 tshsl_ns;
  28. u32 tsd2d_ns;
  29. u32 tchsh_ns;
  30. u32 tslch_ns;
  31. };
  32. struct cadence_spi_priv {
  33. void *regbase;
  34. void *ahbbase;
  35. size_t cmd_len;
  36. u8 cmd_buf[32];
  37. size_t data_len;
  38. int qspi_is_init;
  39. unsigned int qspi_calibrated_hz;
  40. unsigned int qspi_calibrated_cs;
  41. unsigned int previous_hz;
  42. struct reset_ctl_bulk resets;
  43. };
  44. /* Functions call declaration */
  45. void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
  46. void cadence_qspi_apb_controller_enable(void *reg_base_addr);
  47. void cadence_qspi_apb_controller_disable(void *reg_base_addr);
  48. void cadence_qspi_apb_dac_mode_enable(void *reg_base);
  49. int cadence_qspi_apb_command_read(void *reg_base_addr,
  50. const struct spi_mem_op *op);
  51. int cadence_qspi_apb_command_write(void *reg_base_addr,
  52. const struct spi_mem_op *op);
  53. int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
  54. const struct spi_mem_op *op);
  55. int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
  56. const struct spi_mem_op *op);
  57. int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
  58. const struct spi_mem_op *op);
  59. int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
  60. const struct spi_mem_op *op);
  61. void cadence_qspi_apb_chipselect(void *reg_base,
  62. unsigned int chip_select, unsigned int decoder_enable);
  63. void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
  64. void cadence_qspi_apb_config_baudrate_div(void *reg_base,
  65. unsigned int ref_clk_hz, unsigned int sclk_hz);
  66. void cadence_qspi_apb_delay(void *reg_base,
  67. unsigned int ref_clk, unsigned int sclk_hz,
  68. unsigned int tshsl_ns, unsigned int tsd2d_ns,
  69. unsigned int tchsh_ns, unsigned int tslch_ns);
  70. void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
  71. void cadence_qspi_apb_readdata_capture(void *reg_base,
  72. unsigned int bypass, unsigned int delay);
  73. #endif /* __CADENCE_QSPI_H__ */