cadence_qspi.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012
  4. * Altera Corporation <www.altera.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <asm-generic/io.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <malloc.h>
  12. #include <reset.h>
  13. #include <spi.h>
  14. #include <spi-mem.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/err.h>
  17. #include <linux/errno.h>
  18. #include <linux/sizes.h>
  19. #include "cadence_qspi.h"
  20. #define CQSPI_STIG_READ 0
  21. #define CQSPI_STIG_WRITE 1
  22. #define CQSPI_READ 2
  23. #define CQSPI_WRITE 3
  24. static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  25. {
  26. struct cadence_spi_platdata *plat = bus->platdata;
  27. struct cadence_spi_priv *priv = dev_get_priv(bus);
  28. cadence_qspi_apb_config_baudrate_div(priv->regbase,
  29. plat->ref_clk_hz, hz);
  30. /* Reconfigure delay timing if speed is changed. */
  31. cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
  32. plat->tshsl_ns, plat->tsd2d_ns,
  33. plat->tchsh_ns, plat->tslch_ns);
  34. return 0;
  35. }
  36. static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
  37. {
  38. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
  39. SPI_MEM_OP_NO_ADDR,
  40. SPI_MEM_OP_NO_DUMMY,
  41. SPI_MEM_OP_DATA_IN(len, idcode, 1));
  42. return cadence_qspi_apb_command_read(reg_base, &op);
  43. }
  44. /* Calibration sequence to determine the read data capture delay register */
  45. static int spi_calibration(struct udevice *bus, uint hz)
  46. {
  47. struct cadence_spi_priv *priv = dev_get_priv(bus);
  48. void *base = priv->regbase;
  49. unsigned int idcode = 0, temp = 0;
  50. int err = 0, i, range_lo = -1, range_hi = -1;
  51. /* start with slowest clock (1 MHz) */
  52. cadence_spi_write_speed(bus, 1000000);
  53. /* configure the read data capture delay register to 0 */
  54. cadence_qspi_apb_readdata_capture(base, 1, 0);
  55. /* Enable QSPI */
  56. cadence_qspi_apb_controller_enable(base);
  57. /* read the ID which will be our golden value */
  58. err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
  59. if (err) {
  60. puts("SF: Calibration failed (read)\n");
  61. return err;
  62. }
  63. /* use back the intended clock and find low range */
  64. cadence_spi_write_speed(bus, hz);
  65. for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  66. /* Disable QSPI */
  67. cadence_qspi_apb_controller_disable(base);
  68. /* reconfigure the read data capture delay register */
  69. cadence_qspi_apb_readdata_capture(base, 1, i);
  70. /* Enable back QSPI */
  71. cadence_qspi_apb_controller_enable(base);
  72. /* issue a RDID to get the ID value */
  73. err = cadence_spi_read_id(base, 3, (u8 *)&temp);
  74. if (err) {
  75. puts("SF: Calibration failed (read)\n");
  76. return err;
  77. }
  78. /* search for range lo */
  79. if (range_lo == -1 && temp == idcode) {
  80. range_lo = i;
  81. continue;
  82. }
  83. /* search for range hi */
  84. if (range_lo != -1 && temp != idcode) {
  85. range_hi = i - 1;
  86. break;
  87. }
  88. range_hi = i;
  89. }
  90. if (range_lo == -1) {
  91. puts("SF: Calibration failed (low range)\n");
  92. return err;
  93. }
  94. /* Disable QSPI for subsequent initialization */
  95. cadence_qspi_apb_controller_disable(base);
  96. /* configure the final value for read data capture delay register */
  97. cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
  98. debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
  99. (range_hi + range_lo) / 2, range_lo, range_hi);
  100. /* just to ensure we do once only when speed or chip select change */
  101. priv->qspi_calibrated_hz = hz;
  102. priv->qspi_calibrated_cs = spi_chip_select(bus);
  103. return 0;
  104. }
  105. static int cadence_spi_set_speed(struct udevice *bus, uint hz)
  106. {
  107. struct cadence_spi_platdata *plat = bus->platdata;
  108. struct cadence_spi_priv *priv = dev_get_priv(bus);
  109. int err;
  110. if (hz > plat->max_hz)
  111. hz = plat->max_hz;
  112. /* Disable QSPI */
  113. cadence_qspi_apb_controller_disable(priv->regbase);
  114. /*
  115. * Calibration required for different current SCLK speed, requested
  116. * SCLK speed or chip select
  117. */
  118. if (priv->previous_hz != hz ||
  119. priv->qspi_calibrated_hz != hz ||
  120. priv->qspi_calibrated_cs != spi_chip_select(bus)) {
  121. err = spi_calibration(bus, hz);
  122. if (err)
  123. return err;
  124. /* prevent calibration run when same as previous request */
  125. priv->previous_hz = hz;
  126. }
  127. /* Enable QSPI */
  128. cadence_qspi_apb_controller_enable(priv->regbase);
  129. debug("%s: speed=%d\n", __func__, hz);
  130. return 0;
  131. }
  132. static int cadence_spi_probe(struct udevice *bus)
  133. {
  134. struct cadence_spi_platdata *plat = bus->platdata;
  135. struct cadence_spi_priv *priv = dev_get_priv(bus);
  136. struct clk clk;
  137. int ret;
  138. priv->regbase = plat->regbase;
  139. priv->ahbbase = plat->ahbbase;
  140. if (plat->ref_clk_hz == 0) {
  141. ret = clk_get_by_index(bus, 0, &clk);
  142. if (ret) {
  143. #ifdef CONFIG_CQSPI_REF_CLK
  144. plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
  145. #else
  146. return ret;
  147. #endif
  148. } else {
  149. plat->ref_clk_hz = clk_get_rate(&clk);
  150. clk_free(&clk);
  151. if (IS_ERR_VALUE(plat->ref_clk_hz))
  152. return plat->ref_clk_hz;
  153. }
  154. }
  155. ret = reset_get_bulk(bus, &priv->resets);
  156. if (ret)
  157. dev_warn(bus, "Can't get reset: %d\n", ret);
  158. else
  159. reset_deassert_bulk(&priv->resets);
  160. if (!priv->qspi_is_init) {
  161. cadence_qspi_apb_controller_init(plat);
  162. priv->qspi_is_init = 1;
  163. }
  164. return 0;
  165. }
  166. static int cadence_spi_remove(struct udevice *dev)
  167. {
  168. struct cadence_spi_priv *priv = dev_get_priv(dev);
  169. return reset_release_bulk(&priv->resets);
  170. }
  171. static int cadence_spi_set_mode(struct udevice *bus, uint mode)
  172. {
  173. struct cadence_spi_platdata *plat = bus->platdata;
  174. struct cadence_spi_priv *priv = dev_get_priv(bus);
  175. /* Disable QSPI */
  176. cadence_qspi_apb_controller_disable(priv->regbase);
  177. /* Set SPI mode */
  178. cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
  179. /* Enable Direct Access Controller */
  180. if (plat->use_dac_mode)
  181. cadence_qspi_apb_dac_mode_enable(priv->regbase);
  182. /* Enable QSPI */
  183. cadence_qspi_apb_controller_enable(priv->regbase);
  184. return 0;
  185. }
  186. static int cadence_spi_mem_exec_op(struct spi_slave *spi,
  187. const struct spi_mem_op *op)
  188. {
  189. struct udevice *bus = spi->dev->parent;
  190. struct cadence_spi_platdata *plat = bus->platdata;
  191. struct cadence_spi_priv *priv = dev_get_priv(bus);
  192. void *base = priv->regbase;
  193. int err = 0;
  194. u32 mode;
  195. /* Set Chip select */
  196. cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
  197. plat->is_decoded_cs);
  198. if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
  199. if (!op->addr.nbytes)
  200. mode = CQSPI_STIG_READ;
  201. else
  202. mode = CQSPI_READ;
  203. } else {
  204. if (!op->addr.nbytes || !op->data.buf.out)
  205. mode = CQSPI_STIG_WRITE;
  206. else
  207. mode = CQSPI_WRITE;
  208. }
  209. switch (mode) {
  210. case CQSPI_STIG_READ:
  211. err = cadence_qspi_apb_command_read(base, op);
  212. break;
  213. case CQSPI_STIG_WRITE:
  214. err = cadence_qspi_apb_command_write(base, op);
  215. break;
  216. case CQSPI_READ:
  217. err = cadence_qspi_apb_read_setup(plat, op);
  218. if (!err)
  219. err = cadence_qspi_apb_read_execute(plat, op);
  220. break;
  221. case CQSPI_WRITE:
  222. err = cadence_qspi_apb_write_setup(plat, op);
  223. if (!err)
  224. err = cadence_qspi_apb_write_execute(plat, op);
  225. break;
  226. default:
  227. err = -1;
  228. break;
  229. }
  230. return err;
  231. }
  232. static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
  233. {
  234. struct cadence_spi_platdata *plat = bus->platdata;
  235. ofnode subnode;
  236. plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
  237. plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
  238. &plat->ahbsize);
  239. plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
  240. plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
  241. plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
  242. plat->trigger_address = dev_read_u32_default(bus,
  243. "cdns,trigger-address",
  244. 0);
  245. /* Use DAC mode only when MMIO window is at least 8M wide */
  246. if (plat->ahbsize >= SZ_8M)
  247. plat->use_dac_mode = true;
  248. /* All other paramters are embedded in the child node */
  249. subnode = dev_read_first_subnode(bus);
  250. if (!ofnode_valid(subnode)) {
  251. printf("Error: subnode with SPI flash config missing!\n");
  252. return -ENODEV;
  253. }
  254. /* Use 500 KHz as a suitable default */
  255. plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
  256. 500000);
  257. /* Read other parameters from DT */
  258. plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
  259. plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
  260. plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
  261. 200);
  262. plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
  263. 255);
  264. plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
  265. plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
  266. debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
  267. __func__, plat->regbase, plat->ahbbase, plat->max_hz,
  268. plat->page_size);
  269. return 0;
  270. }
  271. static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
  272. .exec_op = cadence_spi_mem_exec_op,
  273. };
  274. static const struct dm_spi_ops cadence_spi_ops = {
  275. .set_speed = cadence_spi_set_speed,
  276. .set_mode = cadence_spi_set_mode,
  277. .mem_ops = &cadence_spi_mem_ops,
  278. /*
  279. * cs_info is not needed, since we require all chip selects to be
  280. * in the device tree explicitly
  281. */
  282. };
  283. static const struct udevice_id cadence_spi_ids[] = {
  284. { .compatible = "cdns,qspi-nor" },
  285. { .compatible = "ti,am654-ospi" },
  286. { }
  287. };
  288. U_BOOT_DRIVER(cadence_spi) = {
  289. .name = "cadence_spi",
  290. .id = UCLASS_SPI,
  291. .of_match = cadence_spi_ids,
  292. .ops = &cadence_spi_ops,
  293. .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
  294. .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
  295. .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
  296. .probe = cadence_spi_probe,
  297. .remove = cadence_spi_remove,
  298. .flags = DM_FLAG_OS_PREPARE,
  299. };