bcm63xx_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/spi/spi-bcm63xx.c:
  6. * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
  7. * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <reset.h>
  15. #include <wait_bit.h>
  16. #include <asm/io.h>
  17. /* BCM6348 SPI core */
  18. #define SPI_6348_CLK 0x06
  19. #define SPI_6348_CMD 0x00
  20. #define SPI_6348_CTL 0x40
  21. #define SPI_6348_CTL_SHIFT 6
  22. #define SPI_6348_FILL 0x07
  23. #define SPI_6348_IR_MASK 0x04
  24. #define SPI_6348_IR_STAT 0x02
  25. #define SPI_6348_RX 0x80
  26. #define SPI_6348_RX_SIZE 0x3f
  27. #define SPI_6348_TX 0x41
  28. #define SPI_6348_TX_SIZE 0x3f
  29. /* BCM6358 SPI core */
  30. #define SPI_6358_CLK 0x706
  31. #define SPI_6358_CMD 0x700
  32. #define SPI_6358_CTL 0x000
  33. #define SPI_6358_CTL_SHIFT 14
  34. #define SPI_6358_FILL 0x707
  35. #define SPI_6358_IR_MASK 0x702
  36. #define SPI_6358_IR_STAT 0x704
  37. #define SPI_6358_RX 0x400
  38. #define SPI_6358_RX_SIZE 0x220
  39. #define SPI_6358_TX 0x002
  40. #define SPI_6358_TX_SIZE 0x21e
  41. /* SPI Clock register */
  42. #define SPI_CLK_SHIFT 0
  43. #define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT)
  44. #define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT)
  45. #define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT)
  46. #define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT)
  47. #define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT)
  48. #define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT)
  49. #define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT)
  50. #define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT)
  51. #define SPI_CLK_MASK (7 << SPI_CLK_SHIFT)
  52. #define SPI_CLK_SSOFF_SHIFT 3
  53. #define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT)
  54. #define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
  55. #define SPI_CLK_BSWAP_SHIFT 7
  56. #define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)
  57. /* SPI Command register */
  58. #define SPI_CMD_OP_SHIFT 0
  59. #define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT)
  60. #define SPI_CMD_SLAVE_SHIFT 4
  61. #define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT)
  62. #define SPI_CMD_PREPEND_SHIFT 8
  63. #define SPI_CMD_PREPEND_BYTES 0xf
  64. #define SPI_CMD_3WIRE_SHIFT 12
  65. #define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)
  66. /* SPI Control register */
  67. #define SPI_CTL_TYPE_FD_RW 0
  68. #define SPI_CTL_TYPE_HD_W 1
  69. #define SPI_CTL_TYPE_HD_R 2
  70. /* SPI Interrupt registers */
  71. #define SPI_IR_DONE_SHIFT 0
  72. #define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT)
  73. #define SPI_IR_RXOVER_SHIFT 1
  74. #define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT)
  75. #define SPI_IR_TXUNDER_SHIFT 2
  76. #define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT)
  77. #define SPI_IR_TXOVER_SHIFT 3
  78. #define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT)
  79. #define SPI_IR_RXUNDER_SHIFT 4
  80. #define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT)
  81. #define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\
  82. SPI_IR_RXOVER_MASK |\
  83. SPI_IR_TXUNDER_MASK |\
  84. SPI_IR_TXOVER_MASK |\
  85. SPI_IR_RXUNDER_MASK)
  86. enum bcm63xx_regs_spi {
  87. SPI_CLK,
  88. SPI_CMD,
  89. SPI_CTL,
  90. SPI_CTL_SHIFT,
  91. SPI_FILL,
  92. SPI_IR_MASK,
  93. SPI_IR_STAT,
  94. SPI_RX,
  95. SPI_RX_SIZE,
  96. SPI_TX,
  97. SPI_TX_SIZE,
  98. };
  99. struct bcm63xx_spi_priv {
  100. const unsigned long *regs;
  101. void __iomem *base;
  102. size_t tx_bytes;
  103. uint8_t num_cs;
  104. };
  105. #define SPI_CLK_CNT 8
  106. static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {
  107. { 25000000, SPI_CLK_25MHZ },
  108. { 20000000, SPI_CLK_20MHZ },
  109. { 12500000, SPI_CLK_12_50MHZ },
  110. { 6250000, SPI_CLK_6_250MHZ },
  111. { 3125000, SPI_CLK_3_125MHZ },
  112. { 1563000, SPI_CLK_1_563MHZ },
  113. { 781000, SPI_CLK_0_781MHZ },
  114. { 391000, SPI_CLK_0_391MHZ }
  115. };
  116. static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,
  117. struct spi_cs_info *info)
  118. {
  119. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  120. if (cs >= priv->num_cs) {
  121. printf("no cs %u\n", cs);
  122. return -EINVAL;
  123. }
  124. return 0;
  125. }
  126. static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode)
  127. {
  128. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  129. const unsigned long *regs = priv->regs;
  130. if (mode & SPI_LSB_FIRST)
  131. setbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
  132. else
  133. clrbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
  134. return 0;
  135. }
  136. static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed)
  137. {
  138. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  139. const unsigned long *regs = priv->regs;
  140. uint8_t clk_cfg;
  141. int i;
  142. /* default to lowest clock configuration */
  143. clk_cfg = SPI_CLK_0_391MHZ;
  144. /* find the closest clock configuration */
  145. for (i = 0; i < SPI_CLK_CNT; i++) {
  146. if (speed >= bcm63xx_spi_freq_table[i][0]) {
  147. clk_cfg = bcm63xx_spi_freq_table[i][1];
  148. break;
  149. }
  150. }
  151. /* write clock configuration */
  152. clrsetbits_8(priv->base + regs[SPI_CLK],
  153. SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
  154. clk_cfg | SPI_CLK_SSOFF_2);
  155. return 0;
  156. }
  157. /*
  158. * BCM63xx SPI driver doesn't allow keeping CS active between transfers since
  159. * they are HW controlled.
  160. * However, it provides a mechanism to prepend write transfers prior to read
  161. * transfers (with a maximum prepend of 15 bytes), which is usually enough for
  162. * SPI-connected flashes since reading requires prepending a write transfer of
  163. * 5 bytes.
  164. *
  165. * This implementation takes advantage of the prepend mechanism and combines
  166. * multiple transfers into a single one where possible (single/multiple write
  167. * transfer(s) followed by a final read/write transfer).
  168. * However, it's not possible to buffer reads, which means that read transfers
  169. * should always be done as the final ones.
  170. * On the other hand, take into account that combining write transfers into
  171. * a single one is just buffering and doesn't require prepend mechanism.
  172. */
  173. static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
  174. const void *dout, void *din, unsigned long flags)
  175. {
  176. struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  177. const unsigned long *regs = priv->regs;
  178. size_t data_bytes = bitlen / 8;
  179. if (flags & SPI_XFER_BEGIN) {
  180. /* clear prepends */
  181. priv->tx_bytes = 0;
  182. /* initialize hardware */
  183. writeb_be(0, priv->base + regs[SPI_IR_MASK]);
  184. }
  185. if (din) {
  186. /* buffering reads not possible since cs is hw controlled */
  187. if (!(flags & SPI_XFER_END)) {
  188. printf("unable to buffer reads\n");
  189. return -EINVAL;
  190. }
  191. /* check rx size */
  192. if (data_bytes > regs[SPI_RX_SIZE]) {
  193. printf("max rx bytes exceeded\n");
  194. return -EMSGSIZE;
  195. }
  196. }
  197. if (dout) {
  198. /* check tx size */
  199. if (priv->tx_bytes + data_bytes > regs[SPI_TX_SIZE]) {
  200. printf("max tx bytes exceeded\n");
  201. return -EMSGSIZE;
  202. }
  203. /* copy tx data */
  204. memcpy_toio(priv->base + regs[SPI_TX] + priv->tx_bytes,
  205. dout, data_bytes);
  206. priv->tx_bytes += data_bytes;
  207. }
  208. if (flags & SPI_XFER_END) {
  209. struct dm_spi_slave_platdata *plat =
  210. dev_get_parent_platdata(dev);
  211. uint16_t val, cmd;
  212. int ret;
  213. /* determine control config */
  214. if (dout && !din) {
  215. /* buffered write transfers */
  216. val = priv->tx_bytes;
  217. val |= (SPI_CTL_TYPE_HD_W << regs[SPI_CTL_SHIFT]);
  218. priv->tx_bytes = 0;
  219. } else {
  220. if (dout && din && (flags & SPI_XFER_ONCE)) {
  221. /* full duplex read/write */
  222. val = data_bytes;
  223. val |= (SPI_CTL_TYPE_FD_RW <<
  224. regs[SPI_CTL_SHIFT]);
  225. priv->tx_bytes = 0;
  226. } else {
  227. /* prepended write transfer */
  228. val = data_bytes;
  229. val |= (SPI_CTL_TYPE_HD_R <<
  230. regs[SPI_CTL_SHIFT]);
  231. if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
  232. printf("max prepend bytes exceeded\n");
  233. return -EMSGSIZE;
  234. }
  235. }
  236. }
  237. if (regs[SPI_CTL_SHIFT] >= 8)
  238. writew_be(val, priv->base + regs[SPI_CTL]);
  239. else
  240. writeb_be(val, priv->base + regs[SPI_CTL]);
  241. /* clear interrupts */
  242. writeb_be(SPI_IR_CLEAR_MASK, priv->base + regs[SPI_IR_STAT]);
  243. /* issue the transfer */
  244. cmd = SPI_CMD_OP_START;
  245. cmd |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
  246. cmd |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
  247. if (plat->mode & SPI_3WIRE)
  248. cmd |= SPI_CMD_3WIRE_MASK;
  249. writew_be(cmd, priv->base + regs[SPI_CMD]);
  250. /* enable interrupts */
  251. writeb_be(SPI_IR_DONE_MASK, priv->base + regs[SPI_IR_MASK]);
  252. ret = wait_for_bit_8(priv->base + regs[SPI_IR_STAT],
  253. SPI_IR_DONE_MASK, true, 1000, false);
  254. if (ret) {
  255. printf("interrupt timeout\n");
  256. return ret;
  257. }
  258. /* copy rx data */
  259. if (din)
  260. memcpy_fromio(din, priv->base + regs[SPI_RX],
  261. data_bytes);
  262. }
  263. return 0;
  264. }
  265. static const struct dm_spi_ops bcm63xx_spi_ops = {
  266. .cs_info = bcm63xx_spi_cs_info,
  267. .set_mode = bcm63xx_spi_set_mode,
  268. .set_speed = bcm63xx_spi_set_speed,
  269. .xfer = bcm63xx_spi_xfer,
  270. };
  271. static const unsigned long bcm6348_spi_regs[] = {
  272. [SPI_CLK] = SPI_6348_CLK,
  273. [SPI_CMD] = SPI_6348_CMD,
  274. [SPI_CTL] = SPI_6348_CTL,
  275. [SPI_CTL_SHIFT] = SPI_6348_CTL_SHIFT,
  276. [SPI_FILL] = SPI_6348_FILL,
  277. [SPI_IR_MASK] = SPI_6348_IR_MASK,
  278. [SPI_IR_STAT] = SPI_6348_IR_STAT,
  279. [SPI_RX] = SPI_6348_RX,
  280. [SPI_RX_SIZE] = SPI_6348_RX_SIZE,
  281. [SPI_TX] = SPI_6348_TX,
  282. [SPI_TX_SIZE] = SPI_6348_TX_SIZE,
  283. };
  284. static const unsigned long bcm6358_spi_regs[] = {
  285. [SPI_CLK] = SPI_6358_CLK,
  286. [SPI_CMD] = SPI_6358_CMD,
  287. [SPI_CTL] = SPI_6358_CTL,
  288. [SPI_CTL_SHIFT] = SPI_6358_CTL_SHIFT,
  289. [SPI_FILL] = SPI_6358_FILL,
  290. [SPI_IR_MASK] = SPI_6358_IR_MASK,
  291. [SPI_IR_STAT] = SPI_6358_IR_STAT,
  292. [SPI_RX] = SPI_6358_RX,
  293. [SPI_RX_SIZE] = SPI_6358_RX_SIZE,
  294. [SPI_TX] = SPI_6358_TX,
  295. [SPI_TX_SIZE] = SPI_6358_TX_SIZE,
  296. };
  297. static const struct udevice_id bcm63xx_spi_ids[] = {
  298. {
  299. .compatible = "brcm,bcm6348-spi",
  300. .data = (ulong)&bcm6348_spi_regs,
  301. }, {
  302. .compatible = "brcm,bcm6358-spi",
  303. .data = (ulong)&bcm6358_spi_regs,
  304. }, { /* sentinel */ }
  305. };
  306. static int bcm63xx_spi_child_pre_probe(struct udevice *dev)
  307. {
  308. struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  309. const unsigned long *regs = priv->regs;
  310. struct spi_slave *slave = dev_get_parent_priv(dev);
  311. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  312. /* check cs */
  313. if (plat->cs >= priv->num_cs) {
  314. printf("no cs %u\n", plat->cs);
  315. return -ENODEV;
  316. }
  317. /* max read/write sizes */
  318. slave->max_read_size = regs[SPI_RX_SIZE];
  319. slave->max_write_size = regs[SPI_TX_SIZE];
  320. return 0;
  321. }
  322. static int bcm63xx_spi_probe(struct udevice *dev)
  323. {
  324. struct bcm63xx_spi_priv *priv = dev_get_priv(dev);
  325. const unsigned long *regs =
  326. (const unsigned long *)dev_get_driver_data(dev);
  327. struct reset_ctl rst_ctl;
  328. struct clk clk;
  329. int ret;
  330. priv->base = dev_remap_addr(dev);
  331. if (!priv->base)
  332. return -EINVAL;
  333. priv->regs = regs;
  334. priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
  335. /* enable clock */
  336. ret = clk_get_by_index(dev, 0, &clk);
  337. if (ret < 0)
  338. return ret;
  339. ret = clk_enable(&clk);
  340. if (ret < 0)
  341. return ret;
  342. ret = clk_free(&clk);
  343. if (ret < 0)
  344. return ret;
  345. /* perform reset */
  346. ret = reset_get_by_index(dev, 0, &rst_ctl);
  347. if (ret < 0)
  348. return ret;
  349. ret = reset_deassert(&rst_ctl);
  350. if (ret < 0)
  351. return ret;
  352. ret = reset_free(&rst_ctl);
  353. if (ret < 0)
  354. return ret;
  355. /* initialize hardware */
  356. writeb_be(0, priv->base + regs[SPI_IR_MASK]);
  357. /* set fill register */
  358. writeb_be(0xff, priv->base + regs[SPI_FILL]);
  359. return 0;
  360. }
  361. U_BOOT_DRIVER(bcm63xx_spi) = {
  362. .name = "bcm63xx_spi",
  363. .id = UCLASS_SPI,
  364. .of_match = bcm63xx_spi_ids,
  365. .ops = &bcm63xx_spi_ops,
  366. .priv_auto_alloc_size = sizeof(struct bcm63xx_spi_priv),
  367. .child_pre_probe = bcm63xx_spi_child_pre_probe,
  368. .probe = bcm63xx_spi_probe,
  369. };