bcm63xx_hsspi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
  6. * Copyright (C) 2000-2010 Broadcom Corporation
  7. * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <reset.h>
  15. #include <wait_bit.h>
  16. #include <asm/io.h>
  17. #define HSSPI_PP 0
  18. #define SPI_MAX_SYNC_CLOCK 30000000
  19. /* SPI Control register */
  20. #define SPI_CTL_REG 0x000
  21. #define SPI_CTL_CS_POL_SHIFT 0
  22. #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
  23. #define SPI_CTL_CLK_GATE_SHIFT 16
  24. #define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
  25. #define SPI_CTL_CLK_POL_SHIFT 17
  26. #define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
  27. /* SPI Interrupts registers */
  28. #define SPI_IR_STAT_REG 0x008
  29. #define SPI_IR_ST_MASK_REG 0x00c
  30. #define SPI_IR_MASK_REG 0x010
  31. #define SPI_IR_CLEAR_ALL 0xff001f1f
  32. /* SPI Ping-Pong Command registers */
  33. #define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
  34. #define SPI_CMD_OP_SHIFT 0
  35. #define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
  36. #define SPI_CMD_PFL_SHIFT 8
  37. #define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
  38. #define SPI_CMD_SLAVE_SHIFT 12
  39. #define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
  40. /* SPI Ping-Pong Status registers */
  41. #define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
  42. #define SPI_STAT_SRCBUSY_SHIFT 1
  43. #define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
  44. /* SPI Profile Clock registers */
  45. #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
  46. #define SPI_PFL_CLK_FREQ_SHIFT 0
  47. #define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
  48. #define SPI_PFL_CLK_RSTLOOP_SHIFT 15
  49. #define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
  50. /* SPI Profile Signal registers */
  51. #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
  52. #define SPI_PFL_SIG_LATCHRIS_SHIFT 12
  53. #define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
  54. #define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
  55. #define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
  56. #define SPI_PFL_SIG_ASYNCIN_SHIFT 16
  57. #define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
  58. /* SPI Profile Mode registers */
  59. #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
  60. #define SPI_PFL_MODE_FILL_SHIFT 0
  61. #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
  62. #define SPI_PFL_MODE_MDRDSZ_SHIFT 16
  63. #define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
  64. #define SPI_PFL_MODE_MDWRSZ_SHIFT 18
  65. #define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
  66. #define SPI_PFL_MODE_3WIRE_SHIFT 20
  67. #define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
  68. /* SPI Ping-Pong FIFO registers */
  69. #define HSSPI_FIFO_SIZE 0x200
  70. #define HSSPI_FIFO_BASE (0x200 + \
  71. (HSSPI_FIFO_SIZE * HSSPI_PP))
  72. /* SPI Ping-Pong FIFO OP register */
  73. #define HSSPI_FIFO_OP_SIZE 0x2
  74. #define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
  75. #define HSSPI_FIFO_OP_BYTES_SHIFT 0
  76. #define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
  77. #define HSSPI_FIFO_OP_MBIT_SHIFT 11
  78. #define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
  79. #define HSSPI_FIFO_OP_CODE_SHIFT 13
  80. #define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
  81. #define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
  82. #define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
  83. struct bcm63xx_hsspi_priv {
  84. void __iomem *regs;
  85. ulong clk_rate;
  86. uint8_t num_cs;
  87. uint8_t cs_pols;
  88. uint speed;
  89. };
  90. static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
  91. struct spi_cs_info *info)
  92. {
  93. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  94. if (cs >= priv->num_cs) {
  95. printf("no cs %u\n", cs);
  96. return -EINVAL;
  97. }
  98. return 0;
  99. }
  100. static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
  101. {
  102. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  103. /* clock polarity */
  104. if (mode & SPI_CPOL)
  105. setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  106. else
  107. clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  108. return 0;
  109. }
  110. static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
  111. {
  112. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  113. priv->speed = speed;
  114. return 0;
  115. }
  116. static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
  117. struct dm_spi_slave_platdata *plat)
  118. {
  119. uint32_t clr, set;
  120. /* profile clock */
  121. set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
  122. set = DIV_ROUND_UP(2048, set);
  123. set &= SPI_PFL_CLK_FREQ_MASK;
  124. set |= SPI_PFL_CLK_RSTLOOP_MASK;
  125. writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
  126. /* profile signal */
  127. set = 0;
  128. clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
  129. SPI_PFL_SIG_LATCHRIS_MASK |
  130. SPI_PFL_SIG_ASYNCIN_MASK;
  131. /* latch/launch config */
  132. if (plat->mode & SPI_CPHA)
  133. set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
  134. else
  135. set |= SPI_PFL_SIG_LATCHRIS_MASK;
  136. /* async clk */
  137. if (priv->speed > SPI_MAX_SYNC_CLOCK)
  138. set |= SPI_PFL_SIG_ASYNCIN_MASK;
  139. clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
  140. /* global control */
  141. set = 0;
  142. clr = 0;
  143. /* invert cs polarity */
  144. if (priv->cs_pols & BIT(plat->cs))
  145. clr |= BIT(plat->cs);
  146. else
  147. set |= BIT(plat->cs);
  148. /* invert dummy cs polarity */
  149. if (priv->cs_pols & BIT(!plat->cs))
  150. clr |= BIT(!plat->cs);
  151. else
  152. set |= BIT(!plat->cs);
  153. clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
  154. }
  155. static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
  156. {
  157. /* restore cs polarities */
  158. clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
  159. priv->cs_pols);
  160. }
  161. /*
  162. * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
  163. * because they are controlled by HW.
  164. * However, it provides a mechanism to prepend write transfers prior to read
  165. * transfers (with a maximum prepend of 15 bytes), which is usually enough for
  166. * SPI-connected flashes since reading requires prepending a write transfer of
  167. * 5 bytes. On the other hand it also provides a way to invert each CS
  168. * polarity, not only between transfers like the older BCM63xx SPI driver, but
  169. * also the rest of the time.
  170. *
  171. * Instead of using the prepend mechanism, this implementation inverts the
  172. * polarity of both the desired CS and another dummy CS when the bus is
  173. * claimed. This way, the dummy CS is restored to its inactive value when
  174. * transfers are issued and the desired CS is preserved in its active value
  175. * all the time. This hack is also used in the upstream linux driver and
  176. * allows keeping CS active between trasnfers even if the HW doesn't give
  177. * this possibility.
  178. */
  179. static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
  180. const void *dout, void *din, unsigned long flags)
  181. {
  182. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  183. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  184. size_t data_bytes = bitlen / 8;
  185. size_t step_size = HSSPI_FIFO_SIZE;
  186. uint16_t opcode = 0;
  187. uint32_t val;
  188. const uint8_t *tx = dout;
  189. uint8_t *rx = din;
  190. if (flags & SPI_XFER_BEGIN)
  191. bcm63xx_hsspi_activate_cs(priv, plat);
  192. /* fifo operation */
  193. if (tx && rx)
  194. opcode = HSSPI_FIFO_OP_READ_WRITE;
  195. else if (rx)
  196. opcode = HSSPI_FIFO_OP_CODE_R;
  197. else if (tx)
  198. opcode = HSSPI_FIFO_OP_CODE_W;
  199. if (opcode != HSSPI_FIFO_OP_CODE_R)
  200. step_size -= HSSPI_FIFO_OP_SIZE;
  201. /* dual mode */
  202. if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
  203. (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
  204. opcode |= HSSPI_FIFO_OP_MBIT_MASK;
  205. /* profile mode */
  206. val = SPI_PFL_MODE_FILL_MASK |
  207. SPI_PFL_MODE_MDRDSZ_MASK |
  208. SPI_PFL_MODE_MDWRSZ_MASK;
  209. if (plat->mode & SPI_3WIRE)
  210. val |= SPI_PFL_MODE_3WIRE_MASK;
  211. writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
  212. /* transfer loop */
  213. while (data_bytes > 0) {
  214. size_t curr_step = min(step_size, data_bytes);
  215. int ret;
  216. /* copy tx data */
  217. if (tx) {
  218. memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
  219. HSSPI_FIFO_OP_SIZE, tx, curr_step);
  220. tx += curr_step;
  221. }
  222. /* set fifo operation */
  223. writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
  224. priv->regs + HSSPI_FIFO_OP_REG);
  225. /* issue the transfer */
  226. val = SPI_CMD_OP_START;
  227. val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
  228. SPI_CMD_PFL_MASK;
  229. val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
  230. SPI_CMD_SLAVE_MASK;
  231. writel(val, priv->regs + SPI_CMD_REG);
  232. /* wait for completion */
  233. ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
  234. SPI_STAT_SRCBUSY_MASK, false,
  235. 1000, false);
  236. if (ret) {
  237. printf("interrupt timeout\n");
  238. return ret;
  239. }
  240. /* copy rx data */
  241. if (rx) {
  242. memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
  243. curr_step);
  244. rx += curr_step;
  245. }
  246. data_bytes -= curr_step;
  247. }
  248. if (flags & SPI_XFER_END)
  249. bcm63xx_hsspi_deactivate_cs(priv);
  250. return 0;
  251. }
  252. static const struct dm_spi_ops bcm63xx_hsspi_ops = {
  253. .cs_info = bcm63xx_hsspi_cs_info,
  254. .set_mode = bcm63xx_hsspi_set_mode,
  255. .set_speed = bcm63xx_hsspi_set_speed,
  256. .xfer = bcm63xx_hsspi_xfer,
  257. };
  258. static const struct udevice_id bcm63xx_hsspi_ids[] = {
  259. { .compatible = "brcm,bcm6328-hsspi", },
  260. { /* sentinel */ }
  261. };
  262. static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
  263. {
  264. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  265. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  266. /* check cs */
  267. if (plat->cs >= priv->num_cs) {
  268. printf("no cs %u\n", plat->cs);
  269. return -ENODEV;
  270. }
  271. /* cs polarity */
  272. if (plat->mode & SPI_CS_HIGH)
  273. priv->cs_pols |= BIT(plat->cs);
  274. else
  275. priv->cs_pols &= ~BIT(plat->cs);
  276. return 0;
  277. }
  278. static int bcm63xx_hsspi_probe(struct udevice *dev)
  279. {
  280. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
  281. struct reset_ctl rst_ctl;
  282. struct clk clk;
  283. int ret;
  284. priv->regs = dev_remap_addr(dev);
  285. if (!priv->regs)
  286. return -EINVAL;
  287. priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
  288. /* enable clock */
  289. ret = clk_get_by_name(dev, "hsspi", &clk);
  290. if (ret < 0)
  291. return ret;
  292. ret = clk_enable(&clk);
  293. if (ret < 0 && ret != -ENOSYS)
  294. return ret;
  295. ret = clk_free(&clk);
  296. if (ret < 0 && ret != -ENOSYS)
  297. return ret;
  298. /* get clock rate */
  299. ret = clk_get_by_name(dev, "pll", &clk);
  300. if (ret < 0 && ret != -ENOSYS)
  301. return ret;
  302. priv->clk_rate = clk_get_rate(&clk);
  303. ret = clk_free(&clk);
  304. if (ret < 0 && ret != -ENOSYS)
  305. return ret;
  306. /* perform reset */
  307. ret = reset_get_by_index(dev, 0, &rst_ctl);
  308. if (ret >= 0) {
  309. ret = reset_deassert(&rst_ctl);
  310. if (ret < 0)
  311. return ret;
  312. }
  313. ret = reset_free(&rst_ctl);
  314. if (ret < 0)
  315. return ret;
  316. /* initialize hardware */
  317. writel(0, priv->regs + SPI_IR_MASK_REG);
  318. /* clear pending interrupts */
  319. writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
  320. /* enable clk gate */
  321. setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
  322. /* read default cs polarities */
  323. priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
  324. SPI_CTL_CS_POL_MASK;
  325. return 0;
  326. }
  327. U_BOOT_DRIVER(bcm63xx_hsspi) = {
  328. .name = "bcm63xx_hsspi",
  329. .id = UCLASS_SPI,
  330. .of_match = bcm63xx_hsspi_ids,
  331. .ops = &bcm63xx_hsspi_ops,
  332. .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
  333. .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
  334. .probe = bcm63xx_hsspi_probe,
  335. };