atmel_spi.h 2.8 KB

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  1. /*
  2. * Register definitions for the Atmel AT32/AT91 SPI Controller
  3. */
  4. /* Register offsets */
  5. #define ATMEL_SPI_CR 0x0000
  6. #define ATMEL_SPI_MR 0x0004
  7. #define ATMEL_SPI_RDR 0x0008
  8. #define ATMEL_SPI_TDR 0x000c
  9. #define ATMEL_SPI_SR 0x0010
  10. #define ATMEL_SPI_IER 0x0014
  11. #define ATMEL_SPI_IDR 0x0018
  12. #define ATMEL_SPI_IMR 0x001c
  13. #define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x))
  14. #define ATMEL_SPI_VERSION 0x00fc
  15. /* Bits in CR */
  16. #define ATMEL_SPI_CR_SPIEN BIT(0)
  17. #define ATMEL_SPI_CR_SPIDIS BIT(1)
  18. #define ATMEL_SPI_CR_SWRST BIT(7)
  19. #define ATMEL_SPI_CR_LASTXFER BIT(24)
  20. /* Bits in MR */
  21. #define ATMEL_SPI_MR_MSTR BIT(0)
  22. #define ATMEL_SPI_MR_PS BIT(1)
  23. #define ATMEL_SPI_MR_PCSDEC BIT(2)
  24. #define ATMEL_SPI_MR_FDIV BIT(3)
  25. #define ATMEL_SPI_MR_MODFDIS BIT(4)
  26. #define ATMEL_SPI_MR_WDRBT BIT(5)
  27. #define ATMEL_SPI_MR_LLB BIT(7)
  28. #define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16)
  29. #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
  30. /* Bits in RDR */
  31. #define ATMEL_SPI_RDR_RD(x) (x)
  32. #define ATMEL_SPI_RDR_PCS(x) ((x) << 16)
  33. /* Bits in TDR */
  34. #define ATMEL_SPI_TDR_TD(x) (x)
  35. #define ATMEL_SPI_TDR_PCS(x) ((x) << 16)
  36. #define ATMEL_SPI_TDR_LASTXFER BIT(24)
  37. /* Bits in SR/IER/IDR/IMR */
  38. #define ATMEL_SPI_SR_RDRF BIT(0)
  39. #define ATMEL_SPI_SR_TDRE BIT(1)
  40. #define ATMEL_SPI_SR_MODF BIT(2)
  41. #define ATMEL_SPI_SR_OVRES BIT(3)
  42. #define ATMEL_SPI_SR_ENDRX BIT(4)
  43. #define ATMEL_SPI_SR_ENDTX BIT(5)
  44. #define ATMEL_SPI_SR_RXBUFF BIT(6)
  45. #define ATMEL_SPI_SR_TXBUFE BIT(7)
  46. #define ATMEL_SPI_SR_NSSR BIT(8)
  47. #define ATMEL_SPI_SR_TXEMPTY BIT(9)
  48. #define ATMEL_SPI_SR_SPIENS BIT(16)
  49. /* Bits in CSRx */
  50. #define ATMEL_SPI_CSRx_CPOL BIT(0)
  51. #define ATMEL_SPI_CSRx_NCPHA BIT(1)
  52. #define ATMEL_SPI_CSRx_CSAAT BIT(3)
  53. #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
  54. #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
  55. #define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0)
  56. #define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16)
  57. #define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24)
  58. /* Bits in VERSION */
  59. #define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff)
  60. #define ATMEL_SPI_VERSION_MFN(x) ((x) << 16)
  61. /* Constants for CSRx:BITS */
  62. #define ATMEL_SPI_BITS_8 0
  63. #define ATMEL_SPI_BITS_9 1
  64. #define ATMEL_SPI_BITS_10 2
  65. #define ATMEL_SPI_BITS_11 3
  66. #define ATMEL_SPI_BITS_12 4
  67. #define ATMEL_SPI_BITS_13 5
  68. #define ATMEL_SPI_BITS_14 6
  69. #define ATMEL_SPI_BITS_15 7
  70. #define ATMEL_SPI_BITS_16 8
  71. struct atmel_spi_slave {
  72. struct spi_slave slave;
  73. void *regs;
  74. u32 mr;
  75. };
  76. static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave)
  77. {
  78. return container_of(slave, struct atmel_spi_slave, slave);
  79. }
  80. /* Register access macros */
  81. #define spi_readl(as, reg) \
  82. readl(as->regs + ATMEL_SPI_##reg)
  83. #define spi_writel(as, reg, value) \
  84. writel(value, as->regs + ATMEL_SPI_##reg)
  85. #if !defined(CONFIG_SYS_SPI_WRITE_TOUT)
  86. #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
  87. #endif